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optical/EMBOS/Users/EmbBase/embfpga.h

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调试完成
2025-09-04 01:45:08 +00:00
#ifndef __EMBFPGA_H__
#define __EMBFPGA_H__
#include "config.h"
//------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
// <20><><EFBFBD><EFBFBD>FPGA
// <20><><EFBFBD>Կ<EFBFBD><D4BF><EFBFBD>6·<36><C2B7><EFBFBD><EFBFBD><EFBFBD>ź<EFBFBD>
// ÿ·<C3BF><C2B7><EFBFBD><EFBFBD><EFBFBD>źŰ<C5BA><C5B0><EFBFBD>2·<32><C2B7><EFBFBD>ٲ<EFBFBD><D9B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>źţ<C5BA>3<EFBFBD><33><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>źź<C5BA>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ź<EFBFBD>
// FPGA<47><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD>16·<36><C2B7>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD><EFBFBD>źţ<C5BA><C5A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD>½<EFBFBD><C2BD><EFBFBD><EFBFBD>ⲿ<EFBFBD>ж<EFBFBD>
// FPGA<47><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD>8·<38><C2B7><EFBFBD><EFBFBD><EFBFBD>ź<EFBFBD>,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ΪPWM<57><4D><EFBFBD><EFBFBD>
// FPGA<47><41><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ·<D2BB><C2B7><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD>źţ<C5BA>λ<EFBFBD><CEBB><EFBFBD>źſ<C5BA><C5BF><EFBFBD><EFBFBD><EFBFBD>12·ʵ<C2B7><CAB5><EFBFBD><EFBFBD><EFBFBD>壬<EFBFBD><E5A3AC>·<EFBFBD><C2B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>4<EFBFBD><34><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>źŻ<C5BA><C5BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><D1A1>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,Ҳ<><D2B2><EFBFBD><EFBFBD>ֱ<EFBFBD>ӿ<EFBFBD><D3BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//------------------------------------------------------------------------------------------------
#define FPGA_VER_101 0x0101 // FPGA<47>汾v1.0.1
#define FPGA_VER_ERR 0xFFFF // FPGA<47><41><EFBFBD>ߴ<EFBFBD><DFB4><EFBFBD>
//------------------------------------------------------------------------------------------------
#define FPGA_CLK 72000000L
//------------------------------------------------------------------------------------------------
#define VAXIS (CORE_FPGA_ADDR_BEG+0x0000) // <20><><EFBFBD><EFBFBD>
#define AXIS(i) (CORE_FPGA_ADDR_BEG+((i)<<7)) // ʵ<><CAB5>
//------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
// <20><><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA>λĬ<CEBB><C4AC>״̬
// <20><><EFBFBD><EFBFBD>
// д<>˿ڵ<CBBF>ַ
//---------------------------------------------------------------
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƶ˿<C6B6>
#define VAXIS_CONTROL (VAXIS+0x00)
// <20><><EFBFBD><EFBFBD><EFBFBD>ƶ˿<C6B6>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʵ<EEA3AC><CAB5><EFBFBD><EFBFBD>Ӧ<EFBFBD>Ĺ<EFBFBD><C4B9>ܣ<EFBFBD><DCA3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>£<EFBFBD>
#define VCTR_LOCK 0x0000 // <20><>ǰƵ<C7B0><C6B5>/<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define VCTR_INPUT_ALM_INT 0x0001 // <20><><EFBFBD><EFBFBD>Input<75>ӿ<EFBFBD><D3BF>½<EFBFBD><C2BD><EFBFBD><EFBFBD>жϱ<D0B6>־
#define VCTR_AXIS_ALM_INT 0x0002 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־
#define VCTR_ZP1_INT 0x0003 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1:<3A><><EFBFBD><EFBFBD>ZP1<50><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϱ<D0B6>־
#define VCTR_ZP2_INT 0x0004 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2:<3A><><EFBFBD><EFBFBD>ZP2<50><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϱ<D0B6>־
#define EXOUT_EN_ON 0x0010 // <20>ⲿ<EFBFBD><E2B2BF><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>:<3A><>(<28><>չIO)
#define EXOUT_EN_OFF 0x0011 // <20>ⲿ<EFBFBD><E2B2BF><EFBFBD><EFBFBD>ʹ<EFBFBD><CAB9>:<3A>ء<EFBFBD>
#define VCTR_VAXIS1_STOP 0x0100 // <20><><EFBFBD><EFBFBD>1:ֹͣ<CDA3><D6B9>
#define VCTR_VAXIS1_RUN 0x0101 // <20><><EFBFBD><EFBFBD>1:<3A><><EFBFBD><EFBFBD>
#define VCTR_VAXIS1_DIS_BUF1 0x0110 // <20><><EFBFBD><EFBFBD>1:<3A>˶<EFBFBD><CBB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1ʧЧ<CAA7><D0A7>
#define VCTR_VAXIS1_DIS_BUF2 0x0111 // <20><><EFBFBD><EFBFBD>1:<3A>˶<EFBFBD><CBB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2ʧЧ<CAA7><D0A7>
#define VCTR_VAXIS1_DIS_BUF3 0x0112 // <20><><EFBFBD><EFBFBD>1:<3A>˶<EFBFBD><CBB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>3ʧЧ<CAA7><D0A7>
#define VCTR_VAXIS1_CLEAN_OV1 0x0120 // <20><><EFBFBD><EFBFBD>1:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD>ɱ<EFBFBD>־
#define VCTR_VAXIS1_CLEAN_OV2 0x0121 // <20><><EFBFBD><EFBFBD>1:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><32><EFBFBD>ɱ<EFBFBD>־
#define VCTR_VAXIS1_DIS_OV1INT 0x0130 // <20><><EFBFBD><EFBFBD>1:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϹرա<D8B1>
#define VCTR_VAXIS1_EN_OV1INT 0x0131 // <20><><EFBFBD><EFBFBD>1:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϴ<D0B6><CFB4><EFBFBD>(<28><>δʹ<CEB4><CAB9>)
#define VCTR_ECD1_CLEAR 0x0200 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define VCTR_ZP1_DIS_INT 0x0210 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1:<3A>ر<EFBFBD>ZP1<50>жϡ<D0B6>
#define VCTR_ZP1_EN_INT 0x0211 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1:<3A><><EFBFBD><EFBFBD>ZP1<50>ж<EFBFBD>
#define VCTR_ECD1_LEVEL_RST 0x0220 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1:ABZP<5A><50>ƽ<EFBFBD>źŸ<C5BA>λ<EFBFBD><CEBB>
#define VCTR_AP1_LEVEL_NEG 0x0221 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1:AP<41><50>ƽ<EFBFBD>ź<EFBFBD>ȡ<EFBFBD><C8A1>
#define VCTR_AZ1_LEVEL_NEG 0x0222 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1:APZP<5A><50>ƽ<EFBFBD>ź<EFBFBD>ȡ<EFBFBD><C8A1>
#define VCTR_ZP1_LEVEL_NEG 0x0223 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1:ZP<5A><50>ƽ<EFBFBD>ź<EFBFBD>ȡ<EFBFBD><C8A1>
#define VCTR_ZP1_FM_ECDZP 0x0230 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:ZP1<50><31>
#define VCTR_ZP1_FM_NONE 0x023F // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>: <20><>ZP(<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)
#define VCTR_ZP1_FM_INPUT1 0x0240 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT1
#define VCTR_ZP1_FM_INPUT2 0x0241 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT2
#define VCTR_ZP1_FM_INPUT3 0x0242 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT3
#define VCTR_ZP1_FM_INPUT4 0x0243 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT4
#define VCTR_ZP1_FM_INPUT5 0x0244 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT5
#define VCTR_ZP1_FM_INPUT6 0x0245 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT6
#define VCTR_ZP1_FM_INPUT7 0x0246 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT7
#define VCTR_ZP1_FM_INPUT8 0x0247 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT8
#define VCTR_ZP1_FM_INPUT9 0x0248 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT9
#define VCTR_ZP1_FM_INPUT10 0x0249 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT10
#define VCTR_ZP1_FM_INPUT11 0x024A // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT11
#define VCTR_ZP1_FM_INPUT12 0x024B // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT12
#define VCTR_ZP1_FM_INPUT13 0x024C // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT13
#define VCTR_ZP1_FM_INPUT14 0x024D // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT14
#define VCTR_ZP1_FM_INPUT15 0x024E // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT15
#define VCTR_ZP1_FM_INPUT16 0x024F // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT16
#define VCTR_ECD2_CLEAR 0x0300 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define VCTR_ZP2_DIS_INT 0x0310 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2:<3A>ر<EFBFBD>ZP2<50>жϡ<D0B6>
#define VCTR_ZP2_EN_INT 0x0311 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2:<3A><><EFBFBD><EFBFBD>ZP2<50>ж<EFBFBD>
#define VCTR_ECD2_LEVEL_RST 0x0320 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2:ABZP<5A><50>ƽ<EFBFBD>źŸ<C5BA>λ<EFBFBD><CEBB>
#define VCTR_AP2_LEVEL_NEG 0x0321 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2:AP<41><50>ƽ<EFBFBD>ź<EFBFBD>ȡ<EFBFBD><C8A1>
#define VCTR_AZ2_LEVEL_NEG 0x0322 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2:APZP<5A><50>ƽ<EFBFBD>ź<EFBFBD>ȡ<EFBFBD><C8A1>
#define VCTR_ZP2_LEVEL_NEG 0x0323 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2:ZP<5A><50>ƽ<EFBFBD>ź<EFBFBD>ȡ<EFBFBD><C8A1>
#define VCTR_ZP2_FM_ECDZP 0x0330 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:ZP2<50><32>
#define VCTR_ZP2_FM_NONE 0x033F // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>: <20><>ZP(<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)
#define VCTR_ZP2_FM_INPUT1 0x0340 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT1
#define VCTR_ZP2_FM_INPUT2 0x0341 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT2
#define VCTR_ZP2_FM_INPUT3 0x0342 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT3
#define VCTR_ZP2_FM_INPUT4 0x0343 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT4
#define VCTR_ZP2_FM_INPUT5 0x0344 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT5
#define VCTR_ZP2_FM_INPUT6 0x0345 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT6
#define VCTR_ZP2_FM_INPUT7 0x0346 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT7
#define VCTR_ZP2_FM_INPUT8 0x0347 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT8
#define VCTR_ZP2_FM_INPUT9 0x0348 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT9
#define VCTR_ZP2_FM_INPUT10 0x0349 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT10
#define VCTR_ZP2_FM_INPUT11 0x034A // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT11
#define VCTR_ZP2_FM_INPUT12 0x034B // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT12
#define VCTR_ZP2_FM_INPUT13 0x034C // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT13
#define VCTR_ZP2_FM_INPUT14 0x034D // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT14
#define VCTR_ZP2_FM_INPUT15 0x034E // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT15
#define VCTR_ZP2_FM_INPUT16 0x034F // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2:ZP<5A>ж<EFBFBD>ͨ<EFBFBD><CDA8>ѡ<EFBFBD><D1A1>:INPUT16
#define VCTR_OPOS_NONE 0x0400 // OP<4F><50><EFBFBD><EFBFBD>:<3A>ء<EFBFBD>
#define VCTR_OPOS_ON 0x0401 // OP<4F><50><EFBFBD><EFBFBD>:<3A><>
#define VCTR_OPOS_VAXIS1 0x0402 // OP<4F><50><EFBFBD><EFBFBD>:<3A><><EFBFBD><EFBFBD>1
#define VCTR_OPOS_AXIS1_P 0x0411 // OP<4F><50><EFBFBD><EFBFBD>:ʵ<><CAB5>1 pulse<73>ź<EFBFBD>
#define VCTR_OPOS_AXIS1_S 0x0412 // OP<4F><50><EFBFBD><EFBFBD>:ʵ<><CAB5>1 sign<67>ź<EFBFBD>
#define VCTR_OPOS_AXIS2_P 0x0421 // OP<4F><50><EFBFBD><EFBFBD>:ʵ<><CAB5>2 pulse<73>ź<EFBFBD>
#define VCTR_OPOS_AXIS2_S 0x0422 // OP<4F><50><EFBFBD><EFBFBD>:ʵ<><CAB5>2 sign<67>ź<EFBFBD>
#define VCTR_OPOS_AXIS3_P 0x0431 // OP<4F><50><EFBFBD><EFBFBD>:ʵ<><CAB5>3 pulse<73>ź<EFBFBD>
#define VCTR_OPOS_AXIS3_S 0x0432 // OP<4F><50><EFBFBD><EFBFBD>:ʵ<><CAB5>3 sign<67>ź<EFBFBD>
#define VCTR_OPOS_AXIS4_P 0x0441 // OP<4F><50><EFBFBD><EFBFBD>:ʵ<><CAB5>4 pulse<73>ź<EFBFBD>
#define VCTR_OPOS_AXIS4_S 0x0442 // OP<4F><50><EFBFBD><EFBFBD>:ʵ<><CAB5>4 sign<67>ź<EFBFBD>
#define VCTR_OPOS_AXIS5_P 0x0451 // OP<4F><50><EFBFBD><EFBFBD>:ʵ<><CAB5>5 pulse<73>ź<EFBFBD>
#define VCTR_OPOS_AXIS5_S 0x0452 // OP<4F><50><EFBFBD><EFBFBD>:ʵ<><CAB5>5 sign<67>ź<EFBFBD>
#define VCTR_OPOS_AXIS6_P 0x0461 // OP<4F><50><EFBFBD><EFBFBD>:ʵ<><CAB5>6 pulse<73>ź<EFBFBD>
#define VCTR_OPOS_AXIS6_S 0x0462 // OP<4F><50><EFBFBD><EFBFBD>:ʵ<><CAB5>6 sign<67>ź<EFBFBD>
#define VCTR_OPOS_AP1 0x0471 // OP<4F><50><EFBFBD><EFBFBD>:AP1
#define VCTR_OPOS_BP1 0x0472 // OP<4F><50><EFBFBD><EFBFBD>:BP1
#define VCTR_OPOS_ZP1 0x0473 // OP<4F><50><EFBFBD><EFBFBD>:ZP1
#define VCTR_OPOS_AP2 0x0481 // OP<4F><50><EFBFBD><EFBFBD>:AP2
#define VCTR_OPOS_BP2 0x0482 // OP<4F><50><EFBFBD><EFBFBD>:BP2
#define VCTR_OPOS_ZP2 0x0483 // OP<4F><50><EFBFBD><EFBFBD>:ZP2
#define VCTR_ZPOS_NONE 0x0500 // ZP<5A><50><EFBFBD><EFBFBD>:<3A>ء<EFBFBD>
#define VCTR_ZPOS_ON 0x0501 // ZP<5A><50><EFBFBD><EFBFBD>:<3A><>
#define VCTR_ZPOS_INPUT1 0x0510 // ZP<5A><50><EFBFBD><EFBFBD>:input1
#define VCTR_ZPOS_INPUT2 0x0511 // ZP<5A><50><EFBFBD><EFBFBD>:input2
#define VCTR_ZPOS_INPUT3 0x0512 // ZP<5A><50><EFBFBD><EFBFBD>:input3
#define VCTR_ZPOS_INPUT4 0x0513 // ZP<5A><50><EFBFBD><EFBFBD>:input4
#define VCTR_ZPOS_INPUT5 0x0514 // ZP<5A><50><EFBFBD><EFBFBD>:input5
#define VCTR_ZPOS_INPUT6 0x0515 // ZP<5A><50><EFBFBD><EFBFBD>:input6
#define VCTR_ZPOS_INPUT7 0x0516 // ZP<5A><50><EFBFBD><EFBFBD>:input7
#define VCTR_ZPOS_INPUT8 0x0517 // ZP<5A><50><EFBFBD><EFBFBD>:input8
#define VCTR_ZPOS_INPUT9 0x0518 // ZP<5A><50><EFBFBD><EFBFBD>:input9
#define VCTR_ZPOS_INPUT10 0x0519 // ZP<5A><50><EFBFBD><EFBFBD>:input10
#define VCTR_ZPOS_INPUT11 0x051A // ZP<5A><50><EFBFBD><EFBFBD>:input11
#define VCTR_ZPOS_INPUT12 0x051B // ZP<5A><50><EFBFBD><EFBFBD>:input12
#define VCTR_ZPOS_INPUT13 0x051C // ZP<5A><50><EFBFBD><EFBFBD>:input13
#define VCTR_ZPOS_INPUT14 0x051D // ZP<5A><50><EFBFBD><EFBFBD>:input14
#define VCTR_ZPOS_INPUT15 0x051E // ZP<5A><50><EFBFBD><EFBFBD>:input15
#define VCTR_ZPOS_INPUT16 0x051F // ZP<5A><50><EFBFBD><EFBFBD>:input16
#define VCTR_ZPOS_ECD1 0x0520 // ZP<5A><50><EFBFBD><EFBFBD>:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1
#define VCTR_ZPOS_ECD2 0x0521 // ZP<5A><50><EFBFBD><EFBFBD>:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2
#define VCTR_AXIS1_ALM_STOP_DIS 0x0610 // ʵ<><CAB5>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͣ<EFBFBD><CDA3><EFBFBD><EFBFBD>
#define VCTR_AXIS1_ALM_STOP_EN 0x0611 // ʵ<><CAB5>1<EFBFBD><31><EFBFBD><EFBFBD>ͣ<EFBFBD><CDA3>
#define VCTR_AXIS1_ALM_LEV_LOW 0x0612 // ʵ<><CAB5>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƽΪ<C6BD>͡<EFBFBD>
#define VCTR_AXIS1_ALM_LEV_HIGH 0x0613 // ʵ<><CAB5>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƽΪ<C6BD><CEAA>
#define VCTR_AXIS2_ALM_STOP_DIS 0x0620 // ʵ<><CAB5>2<EFBFBD><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͣ<EFBFBD><CDA3><EFBFBD><EFBFBD>
#define VCTR_AXIS2_ALM_STOP_EN 0x0621 // ʵ<><CAB5>2<EFBFBD><32><EFBFBD><EFBFBD>ͣ<EFBFBD><CDA3>
#define VCTR_AXIS2_ALM_LEV_LOW 0x0622 // ʵ<><CAB5>2<EFBFBD><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƽΪ<C6BD>͡<EFBFBD>
#define VCTR_AXIS2_ALM_LEV_HIGH 0x0623 // ʵ<><CAB5>2<EFBFBD><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƽΪ<C6BD><CEAA>
#define VCTR_AXIS3_ALM_STOP_DIS 0x0630 // ʵ<><CAB5>3<EFBFBD><33><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͣ<EFBFBD><CDA3><EFBFBD><EFBFBD>
#define VCTR_AXIS3_ALM_STOP_EN 0x0631 // ʵ<><CAB5>3<EFBFBD><33><EFBFBD><EFBFBD>ͣ<EFBFBD><CDA3>
#define VCTR_AXIS3_ALM_LEV_LOW 0x0632 // ʵ<><CAB5>3<EFBFBD><33><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƽΪ<C6BD>͡<EFBFBD>
#define VCTR_AXIS3_ALM_LEV_HIGH 0x0633 // ʵ<><CAB5>3<EFBFBD><33><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƽΪ<C6BD><CEAA>
#define VCTR_AXIS4_ALM_STOP_DIS 0x0640 // ʵ<><CAB5>4<EFBFBD><34><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͣ<EFBFBD><CDA3><EFBFBD><EFBFBD>
#define VCTR_AXIS4_ALM_STOP_EN 0x0641 // ʵ<><CAB5>4<EFBFBD><34><EFBFBD><EFBFBD>ͣ<EFBFBD><CDA3>
#define VCTR_AXIS4_ALM_LEV_LOW 0x0642 // ʵ<><CAB5>4<EFBFBD><34><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƽΪ<C6BD>͡<EFBFBD>
#define VCTR_AXIS4_ALM_LEV_HIGH 0x0643 // ʵ<><CAB5>4<EFBFBD><34><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƽΪ<C6BD><CEAA>
#define VCTR_AXIS5_ALM_STOP_DIS 0x0650 // ʵ<><CAB5>5<EFBFBD><35><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͣ<EFBFBD><CDA3><EFBFBD><EFBFBD>
#define VCTR_AXIS5_ALM_STOP_EN 0x0651 // ʵ<><CAB5>5<EFBFBD><35><EFBFBD><EFBFBD>ͣ<EFBFBD><CDA3>
#define VCTR_AXIS5_ALM_LEV_LOW 0x0652 // ʵ<><CAB5>5<EFBFBD><35><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƽΪ<C6BD>͡<EFBFBD>
#define VCTR_AXIS5_ALM_LEV_HIGH 0x0653 // ʵ<><CAB5>5<EFBFBD><35><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƽΪ<C6BD><CEAA>
#define VCTR_AXIS6_ALM_STOP_DIS 0x0660 // ʵ<><CAB5>6<EFBFBD><36><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͣ<EFBFBD><CDA3><EFBFBD><EFBFBD>
#define VCTR_AXIS6_ALM_STOP_EN 0x0661 // ʵ<><CAB5>6<EFBFBD><36><EFBFBD><EFBFBD>ͣ<EFBFBD><CDA3>
#define VCTR_AXIS6_ALM_LEV_LOW 0x0662 // ʵ<><CAB5>6<EFBFBD><36><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƽΪ<C6BD>͡<EFBFBD>
#define VCTR_AXIS6_ALM_LEV_HIGH 0x0663 // ʵ<><CAB5>6<EFBFBD><36><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƽΪ<C6BD><CEAA>
#define ALM_CONFIG_BASE 0x0600
#define ALM_STOP_DIS 0x0000
#define ALM_STOP_EN 0x0001
#define ALM_LEV_LOW 0x0002
#define ALM_LEV_HIGH 0x0003
#define MAKE_VCTR_AXIS_ALM_CMD(id, alm) (ALM_CONFIG_BASE|((id<<4)&0xF0)|((alm)&0x0F))
#define IS_VAXIS_CMD(cmd) ( ((cmd) == VCTR_LOCK ) ||\
((cmd) == VCTR_INPUT_ALM_INT ) ||\
((cmd) == VCTR_AXIS_ALM_INT ) ||\
((cmd) == VCTR_ZP1_INT ) ||\
((cmd) == VCTR_ZP2_INT ) ||\
((cmd) == EXOUT_EN_ON ) ||\
((cmd) == EXOUT_EN_OFF ) ||\
((cmd) == VCTR_VAXIS1_STOP ) ||\
((cmd) == VCTR_VAXIS1_RUN ) ||\
((cmd) == VCTR_VAXIS1_DIS_BUF1 ) ||\
((cmd) == VCTR_VAXIS1_DIS_BUF2 ) ||\
((cmd) == VCTR_VAXIS1_DIS_BUF3 ) ||\
((cmd) == VCTR_VAXIS1_CLEAN_OV1 ) ||\
((cmd) == VCTR_VAXIS1_CLEAN_OV2 ) ||\
((cmd) == VCTR_ECD1_CLEAR ) ||\
((cmd) == VCTR_ZP1_DIS_INT ) ||\
((cmd) == VCTR_ZP1_EN_INT ) ||\
((cmd) == VCTR_ECD1_LEVEL_RST ) ||\
((cmd) == VCTR_AP1_LEVEL_NEG ) ||\
((cmd) == VCTR_AZ1_LEVEL_NEG ) ||\
((cmd) == VCTR_ZP1_LEVEL_NEG ) ||\
((cmd) == VCTR_ZP1_FM_ECDZP ) ||\
((cmd) == VCTR_ZP1_FM_NONE ) ||\
((cmd) == VCTR_ZP1_FM_INPUT1 ) ||\
((cmd) == VCTR_ZP1_FM_INPUT2 ) ||\
((cmd) == VCTR_ZP1_FM_INPUT3 ) ||\
((cmd) == VCTR_ZP1_FM_INPUT4 ) ||\
((cmd) == VCTR_ZP1_FM_INPUT5 ) ||\
((cmd) == VCTR_ZP1_FM_INPUT6 ) ||\
((cmd) == VCTR_ZP1_FM_INPUT7 ) ||\
((cmd) == VCTR_ZP1_FM_INPUT8 ) ||\
((cmd) == VCTR_ZP1_FM_INPUT9 ) ||\
((cmd) == VCTR_ZP1_FM_INPUT10 ) ||\
((cmd) == VCTR_ZP1_FM_INPUT11 ) ||\
((cmd) == VCTR_ZP1_FM_INPUT12 ) ||\
((cmd) == VCTR_ZP1_FM_INPUT13 ) ||\
((cmd) == VCTR_ZP1_FM_INPUT14 ) ||\
((cmd) == VCTR_ZP1_FM_INPUT15 ) ||\
((cmd) == VCTR_ZP1_FM_INPUT16 ) ||\
((cmd) == VCTR_ECD2_CLEAR ) ||\
((cmd) == VCTR_ZP2_DIS_INT ) ||\
((cmd) == VCTR_ZP2_EN_INT ) ||\
((cmd) == VCTR_ECD2_LEVEL_RST ) ||\
((cmd) == VCTR_AP2_LEVEL_NEG ) ||\
((cmd) == VCTR_AZ2_LEVEL_NEG ) ||\
((cmd) == VCTR_ZP2_LEVEL_NEG ) ||\
((cmd) == VCTR_ZP2_FM_ECDZP ) ||\
((cmd) == VCTR_ZP2_FM_NONE ) ||\
((cmd) == VCTR_ZP2_FM_INPUT1 ) ||\
((cmd) == VCTR_ZP2_FM_INPUT2 ) ||\
((cmd) == VCTR_ZP2_FM_INPUT3 ) ||\
((cmd) == VCTR_ZP2_FM_INPUT4 ) ||\
((cmd) == VCTR_ZP2_FM_INPUT5 ) ||\
((cmd) == VCTR_ZP2_FM_INPUT6 ) ||\
((cmd) == VCTR_ZP2_FM_INPUT7 ) ||\
((cmd) == VCTR_ZP2_FM_INPUT8 ) ||\
((cmd) == VCTR_ZP2_FM_INPUT9 ) ||\
((cmd) == VCTR_ZP2_FM_INPUT10 ) ||\
((cmd) == VCTR_ZP2_FM_INPUT11 ) ||\
((cmd) == VCTR_ZP2_FM_INPUT12 ) ||\
((cmd) == VCTR_ZP2_FM_INPUT13 ) ||\
((cmd) == VCTR_ZP2_FM_INPUT14 ) ||\
((cmd) == VCTR_ZP2_FM_INPUT15 ) ||\
((cmd) == VCTR_ZP2_FM_INPUT16 ) ||\
((cmd) == VCTR_OPOS_NONE ) ||\
((cmd) == VCTR_OPOS_ON ) ||\
((cmd) == VCTR_OPOS_VAXIS1 ) ||\
((cmd) == VCTR_OPOS_AXIS1_P ) ||\
((cmd) == VCTR_OPOS_AXIS1_S ) ||\
((cmd) == VCTR_OPOS_AXIS2_P ) ||\
((cmd) == VCTR_OPOS_AXIS2_S ) ||\
((cmd) == VCTR_OPOS_AXIS3_P ) ||\
((cmd) == VCTR_OPOS_AXIS3_S ) ||\
((cmd) == VCTR_OPOS_AXIS4_P ) ||\
((cmd) == VCTR_OPOS_AXIS4_S ) ||\
((cmd) == VCTR_OPOS_AXIS5_P ) ||\
((cmd) == VCTR_OPOS_AXIS5_S ) ||\
((cmd) == VCTR_OPOS_AXIS6_P ) ||\
((cmd) == VCTR_OPOS_AXIS6_S ) ||\
((cmd) == VCTR_OPOS_AP1 ) ||\
((cmd) == VCTR_OPOS_BP1 ) ||\
((cmd) == VCTR_OPOS_ZP1 ) ||\
((cmd) == VCTR_OPOS_AP2 ) ||\
((cmd) == VCTR_OPOS_BP2 ) ||\
((cmd) == VCTR_OPOS_ZP2 ) ||\
((cmd) == VCTR_ZPOS_NONE ) ||\
((cmd) == VCTR_ZPOS_ON ) ||\
((cmd) == VCTR_ZPOS_INPUT1 ) ||\
((cmd) == VCTR_ZPOS_INPUT2 ) ||\
((cmd) == VCTR_ZPOS_INPUT3 ) ||\
((cmd) == VCTR_ZPOS_INPUT4 ) ||\
((cmd) == VCTR_ZPOS_INPUT5 ) ||\
((cmd) == VCTR_ZPOS_INPUT6 ) ||\
((cmd) == VCTR_ZPOS_INPUT7 ) ||\
((cmd) == VCTR_ZPOS_INPUT8 ) ||\
((cmd) == VCTR_ZPOS_INPUT9 ) ||\
((cmd) == VCTR_ZPOS_INPUT10 ) ||\
((cmd) == VCTR_ZPOS_INPUT11 ) ||\
((cmd) == VCTR_ZPOS_INPUT12 ) ||\
((cmd) == VCTR_ZPOS_INPUT13 ) ||\
((cmd) == VCTR_ZPOS_INPUT14 ) ||\
((cmd) == VCTR_ZPOS_INPUT15 ) ||\
((cmd) == VCTR_ZPOS_INPUT16 ) ||\
((cmd) == VCTR_ZPOS_ECD1 ) ||\
((cmd) == VCTR_ZPOS_ECD2 ) ||\
((cmd) == VCTR_AXIS1_ALM_STOP_DIS ) ||\
((cmd) == VCTR_AXIS1_ALM_STOP_EN ) ||\
((cmd) == VCTR_AXIS1_ALM_LEV_LOW ) ||\
((cmd) == VCTR_AXIS1_ALM_LEV_HIGH ) ||\
((cmd) == VCTR_AXIS2_ALM_STOP_DIS ) ||\
((cmd) == VCTR_AXIS2_ALM_STOP_EN ) ||\
((cmd) == VCTR_AXIS2_ALM_LEV_LOW ) ||\
((cmd) == VCTR_AXIS2_ALM_LEV_HIGH ) ||\
((cmd) == VCTR_AXIS3_ALM_STOP_DIS ) ||\
((cmd) == VCTR_AXIS3_ALM_STOP_EN ) ||\
((cmd) == VCTR_AXIS3_ALM_LEV_LOW ) ||\
((cmd) == VCTR_AXIS3_ALM_LEV_HIGH ) ||\
((cmd) == VCTR_AXIS4_ALM_STOP_DIS ) ||\
((cmd) == VCTR_AXIS4_ALM_STOP_EN ) ||\
((cmd) == VCTR_AXIS4_ALM_LEV_LOW ) ||\
((cmd) == VCTR_AXIS4_ALM_LEV_HIGH ) ||\
((cmd) == VCTR_AXIS5_ALM_STOP_DIS ) ||\
((cmd) == VCTR_AXIS5_ALM_STOP_EN ) ||\
((cmd) == VCTR_AXIS5_ALM_LEV_LOW ) ||\
((cmd) == VCTR_AXIS5_ALM_LEV_HIGH ) ||\
((cmd) == VCTR_AXIS6_ALM_STOP_DIS ) ||\
((cmd) == VCTR_AXIS6_ALM_STOP_EN ) ||\
((cmd) == VCTR_AXIS6_ALM_LEV_LOW ) ||\
((cmd) == VCTR_AXIS6_ALM_LEV_HIGH ) ||\
0)
//---------------------------------------------------------------
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define VAXIS1_BUF1_PARA (VAXIS+0x02) // <20><><EFBFBD><EFBFBD>1:<3A><><EFBFBD><EFBFBD><EEBBBA><EFBFBD><EFBFBD>1д<31><D0B4><EFBFBD><EFBFBD><EFBFBD>˿<EFBFBD>
#define VAXIS1_BUF2_PARA (VAXIS+0x04) // <20><><EFBFBD><EFBFBD>1:<3A><><EFBFBD><EFBFBD><EEBBBA><EFBFBD><EFBFBD>2д<32><D0B4><EFBFBD><EFBFBD><EFBFBD>˿<EFBFBD>
#define VAXIS1_BUF3_PARA (VAXIS+0x06) // <20><><EFBFBD><EFBFBD>1:<3A><><EFBFBD><EFBFBD><EEBBBA><EFBFBD><EFBFBD>3
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>д<EFBFBD><D0B4><EFBFBD>˶<EFBFBD><CBB6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ƶ˿<C6B6>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EEA3AC><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>塣
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1ִ<31>й<EFBFBD><D0B9><EFBFBD><EFBFBD>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>򻺳<EFBFBD><F2BBBAB3><EFBFBD>2д<32><D0B4><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD>˶<EFBFBD><CBB6><EFBFBD><EFBFBD>һ<EEA1A3><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ִ<EFBFBD><D6B4><EFBFBD><EFBFBD><EFBFBD>ɺ<EFBFBD><C9BA>Զ<EFBFBD><D4B6>л<EFBFBD><D0BB><EFBFBD><EFBFBD><EFBFBD>һ<EFBFBD><D2BB><EFBFBD><EFBFBD>
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EEBBBA><EFBFBD><EFBFBD><EFBFBD>ṹ<EFBFBD><E1B9B9><EFBFBD><EFBFBD>
typedef struct
{
u16 vaxisId; // <20><><EFBFBD><EFBFBD>ѡ<EFBFBD><D1A1> (VAXIS_ID1 ~ VAXIS_ECD)
u16 bufSel; // buf ѡ<><D1A1> (BUF_SEL1 ~ BUF_SEL3)
u32 calcGap; // <20><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> (MIN_GAP ~ MAX_GAP)
u32 startPPS; // <20><><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5> (MIN_PPS ~ MAX_PPS)
u32 runPPS; // Ŀ<><C4BF>Ƶ<EFBFBD><C6B5> (MIN_PPS ~ MAX_PPS)
u32 outNum; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> (MIN_OUTNUM ~ MAX_OUTNUM)
u32 jumpNum; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> (0 ~ MAX_OUTNUM)
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч
} VAxisCmdStr;
// ע<>⣺
// 1. Ƶ<>ʷ<EFBFBD>Χ 1Hz ~ 4Mhz
// 2. <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5>Ϊ<EFBFBD>޷<EFBFBD><DEB7><EFBFBD><EFBFBD><EFBFBD>
// 3. <20><>СƵ<D0A1>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڼ<EFBFBD><DABC>ٶ<EFBFBD>Ƶ<EFBFBD><C6B5>
// 4.<2E><>3<EFBFBD><33><EFBFBD>ȼ<EFBFBD><C8BC><EFBFBD><EFBFBD>ڱ<EFBFBD>1<EFBFBD>ͱ<EFBFBD>2<EFBFBD><32><EFBFBD><EFBFBD>3<EFBFBD><33>Чʱ<D0A7><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ٶ<EFBFBD><D9B6>Ա<EFBFBD>3Ϊ׼
// <20>ṹ<EFBFBD>õ<EFBFBD><C3B5>ĺ궨<C4BA><EAB6A8>
// <20><><EFBFBD><EFBFBD>ѡ<EFBFBD><D1A1>
#define VAXIS_ID1 0x0001
#define VAXIS_ECD 0x0004
#define VAXIS_ID_ALL 0x0005
#define IS_VAXIS_ID(VAXIS) (((VAXIS) == VAXIS_ID1) || \
((VAXIS) == VAXIS_ECD) || \
((VAXIS) == VAXIS_ID_ALL))
// <20><>ѡ<EFBFBD><D1A1>
#define BUF_SEL1 0x0001
#define BUF_SEL2 0x0002
#define BUF_SEL3 0x0003
#define IS_BUF_SEL(BUFF) (((BUFF) == BUF_SEL1) || \
((BUFF) == BUF_SEL2) || \
((BUFF) == BUF_SEL3))
#define MIN_GAP 36
#define MAX_GAP 72000
#define MIN_PPS 1
#define MAX_PPS 4000000 // 4MHz
#define MIN_OUTNUM 1
#define MAX_OUTNUM 67108863 // 2^26-1
#define VOK_FLAG 0x4F4B // OK
#define OP_OUT_DIVISION (VAXIS+0x08) // OP<4F><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5><EFBFBD>ö˿<C3B6>
#define OP_OUT_DIRECT 0x0001 // ֱ<><D6B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
// <20><><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5>֧<EFBFBD>ִ<EFBFBD> 0x0002--0xFFFE ֮<><D6AE><EFBFBD><EFBFBD>ż<EFBFBD><C5BC>
#define OP_COUNTER_SET_L (VAXIS+0x0A) // <20><><EFBFBD><EFBFBD>OP<4F><50><EFBFBD><EFBFBD>ֵ
#define OP_COUNTER_SET_H (VAXIS+0x0C)
#define ZP_COUNTER_SET_L (VAXIS+0x0E) // <20><><EFBFBD><EFBFBD>ZP<5A><50><EFBFBD><EFBFBD>ֵ
#define ZP_COUNTER_SET_H (VAXIS+0x10)
#define ECD1_COUNTER_SET_L (VAXIS+0x12) // <20><><EFBFBD>ñ<EFBFBD><C3B1><EFBFBD><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD>ֵ
#define ECD1_COUNTER_SET_H (VAXIS+0x14)
#define ECD2_COUNTER_SET_L (VAXIS+0x16) // <20><><EFBFBD>ñ<EFBFBD><C3B1><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><32><EFBFBD><EFBFBD>ֵ
#define ECD2_COUNTER_SET_H (VAXIS+0x18)
#define INPUT_INT_SET (VAXIS+0x20) // <20><><EFBFBD><EFBFBD><EFBFBD>˿<EFBFBD><CBBF>½<EFBFBD><C2BD><EFBFBD><EFBFBD>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD>
#define INPUT_ALL_FINT_DIS 0x0000 // <20><><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>ȫ<EFBFBD><C8AB><EFBFBD><EFBFBD><EFBFBD>á<EFBFBD>
#define INPUT1_INT_EN 0x0001 // <20><><EFBFBD><EFBFBD>1<EFBFBD>ж<EFBFBD>ʹ<EFBFBD><CAB9>
#define INPUT2_INT_EN 0x0002 // <20><><EFBFBD><EFBFBD>2<EFBFBD>ж<EFBFBD>ʹ<EFBFBD><CAB9>
#define INPUT3_INT_EN 0x0004 // <20><><EFBFBD><EFBFBD>3<EFBFBD>ж<EFBFBD>ʹ<EFBFBD><CAB9>
#define INPUT4_INT_EN 0x0008 // <20><><EFBFBD><EFBFBD>4<EFBFBD>ж<EFBFBD>ʹ<EFBFBD><CAB9>
#define INPUT5_INT_EN 0x0010 // <20><><EFBFBD><EFBFBD>5<EFBFBD>ж<EFBFBD>ʹ<EFBFBD><CAB9>
#define INPUT6_INT_EN 0x0020 // <20><><EFBFBD><EFBFBD>6<EFBFBD>ж<EFBFBD>ʹ<EFBFBD><CAB9>
#define INPUT7_INT_EN 0x0040 // <20><><EFBFBD><EFBFBD>7<EFBFBD>ж<EFBFBD>ʹ<EFBFBD><CAB9>
#define INPUT8_INT_EN 0x0080 // <20><><EFBFBD><EFBFBD>8<EFBFBD>ж<EFBFBD>ʹ<EFBFBD><CAB9>
#define INPUT9_INT_EN 0x0100 // <20><><EFBFBD><EFBFBD>9<EFBFBD>ж<EFBFBD>ʹ<EFBFBD><CAB9>
#define INPUT10_INT_EN 0x0200 // <20><><EFBFBD><EFBFBD>10<31>ж<EFBFBD>ʹ<EFBFBD><CAB9>
#define INPUT11_INT_EN 0x0400 // <20><><EFBFBD><EFBFBD>11<31>ж<EFBFBD>ʹ<EFBFBD><CAB9>
#define INPUT12_INT_EN 0x0800 // <20><><EFBFBD><EFBFBD>12<31>ж<EFBFBD>ʹ<EFBFBD><CAB9>
#define INPUT13_INT_EN 0x1000 // <20><><EFBFBD><EFBFBD>13<31>ж<EFBFBD>ʹ<EFBFBD><CAB9>
#define INPUT14_INT_EN 0x2000 // <20><><EFBFBD><EFBFBD>14<31>ж<EFBFBD>ʹ<EFBFBD><CAB9>
#define INPUT15_INT_EN 0x4000 // <20><><EFBFBD><EFBFBD>15<31>ж<EFBFBD>ʹ<EFBFBD><CAB9>
#define INPUT16_INT_EN 0x8000 // <20><><EFBFBD><EFBFBD>16<31>ж<EFBFBD>ʹ<EFBFBD><CAB9>
// <20><><EFBFBD><EFBFBD><EFBFBD>˿ڿ<CBBF><DABF><EFBFBD>
#define OUTPUT_SET (VAXIS+0x22)
#define OUTPUT1_BIT 0x0001 // <20><><EFBFBD><EFBFBD>1
#define OUTPUT2_BIT 0x0002 // <20><><EFBFBD><EFBFBD>2
#define OUTPUT3_BIT 0x0004 // <20><><EFBFBD><EFBFBD>3
#define OUTPUT4_BIT 0x0008 // <20><><EFBFBD><EFBFBD>4
#define OUTPUT5_BIT 0x0010 // <20><><EFBFBD><EFBFBD>5
#define OUTPUT6_BIT 0x0020 // <20><><EFBFBD><EFBFBD>6
#define OUTPUT7_BIT 0x0040 // <20><><EFBFBD><EFBFBD>7
#define OUTPUT8_BIT 0x0080 // <20><><EFBFBD><EFBFBD>8
// <20>ⲿIOˢ<4F><CBA2>Ƶ<EFBFBD><C6B5>
#define EXIO_REFRE_FREQ (VAXIS+0x24) // <20>ⲿIOˢ<4F><CBA2>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define REF_FREQ_35K 0x0001
#define REF_FREQ_22K 0x0002
#define REF_FREQ_16K 0x0003
#define REF_FREQ_14K 0x0004
#define REF_FREQ_12K 0x0005
#define REF_FREQ_10K 0x0006 // <20><>
#define REF_FREQ_9K 0x0007
#define REF_FREQ_8K 0x0008
#define REF_FREQ_7K 0x0009
#define REF_FREQ_6K 0x000A
#define REF_FREQ_5K 0x000B
#define REF_FREQ_4K 0x000C
#define REF_FREQ_3K 0x000D
#define REF_FREQ_2K 0x000E
#define REF_FREQ_1K 0x000F
#define REF_FREQ_500 0x001F
// <20><><EFBFBD><EFBFBD>IO<49><4F>չ<EFBFBD>忨<EFBFBD><E5BFA8>д
#define EXIO_PORT_BASE (VAXIS+0x60) // <20><><EFBFBD><EFBFBD>IO<49><4F>չ<EFBFBD>忨<EFBFBD><E5BFA8><EFBFBD><EFBFBD>ַ
#define EXIO_PORT_ADDR(addr) (EXIO_PORT_BASE+((addr)>>4)*2)
#define EXIO_ADDR_MOD(addr) (0x0001 << ((addr)&0x0F))
#define MAX_EXIO_ADDR 256
#define EXIO_PER_PORT 16
#define EXIO_PORT_NUM (MAX_EXIO_ADDR/EXIO_PER_PORT)
//------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
// ʵ<><CAB5>ƫ<EFBFBD>Ƶ<EFBFBD>ַ
//------------------------------------------------------
// д<>˿ڵ<CBBF>ַ
// ʵ<><CAB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ö˿<C3B6>
#define AXIS_CONFIG(axisAddr) (axisAddr+0x00)
#define POUT_CWCCW 0x0000 // ˫<><CBAB><EFBFBD>巽ʽ<E5B7BD><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define POUT_PLSDIR 0x0001 // <20><><EFBFBD><EFBFBD>+<2B><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʽ<EFBFBD><CABD><EFBFBD><EFBFBD>
#define POUT_NORMAL 0x0002 // <20><><EFBFBD><EFBFBD><EFBFBD>ź<EFBFBD><C5BA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ<C4A3><CABD>
#define POUT_XCHANGE 0x0003 // <20><><EFBFBD><EFBFBD><EFBFBD>źŶԵ<C5B6><D4B5><EFBFBD><EFBFBD><EFBFBD>ģʽ
#define POUT_DISABLE 0x0100 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֹ<EFBFBD><D6B9>
#define POUT_ENABLE_VAXIS1 0x0101 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:<3A><><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>1
#define POUT_ENABLE_ECD 0x0102 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:<3A><><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ӿ<EFBFBD>
#define POUT_ENABLE_PWM 0x0102 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:<3A><><EFBFBD><EFBFBD>ΪPWMģʽ
#define POUT_ENABLE_BUSIO 0x0102 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>:<3A><><EFBFBD><EFBFBD>Ϊ<EFBFBD>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD>ֱ<EFBFBD>ӿ<EFBFBD><D3BF><EFBFBD>ģʽ
#define MAKE_POUT_CMD(vaxis) (POUT_DISABLE|((vaxis)&0x0F))
#define DATI_INTERPOLATION 0x0200 // Ӳ<><D3B2>ֱ<EFBFBD><D6B1>(<28><><EFBFBD><EFBFBD>)<29>岹<EFBFBD><E5B2B9>
#define DATI_ECD1_FLOW 0x0201 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1<EFBFBD>涯<EFBFBD><E6B6AF>ʽ<EFBFBD><CABD><EFBFBD><EFBFBD>(CW/CCW<43><57>P/S<>ź<EFBFBD>)
#define DATI_ECD2_FLOW 0x0202 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD>涯<EFBFBD><E6B6AF>ʽ<EFBFBD><CABD><EFBFBD><EFBFBD>(CW/CCW<43><57>P/S<>ź<EFBFBD>)
#define DATI_ECD1_MAPPING 0x0203 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1<EFBFBD>ź<EFBFBD>ӳ<EFBFBD><D3B3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(<28>ź<EFBFBD>ֱ<EFBFBD><D6B1>, <20><><EFBFBD><EFBFBD><EFBFBD>źŻ<C5BA>CW/CCW<43><57>P/S<>ź<EFBFBD>)
#define DATI_ECD2_MAPPING 0x0204 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD>ź<EFBFBD>ӳ<EFBFBD><D3B3><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(<28>ź<EFBFBD>ֱ<EFBFBD><D6B1>, <20><><EFBFBD><EFBFBD><EFBFBD>źŻ<C5BA>CW/CCW<43><57>P/S<>ź<EFBFBD>)
#define DATI_PWM 0x0205 // PWMģʽ
#define DATI_BUS_IO 0x0206 // <20>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD>ֱ<EFBFBD>ӿ<EFBFBD><D3BF><EFBFBD>ģʽ
#define MOUT_EN_LOW 0x0300 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>EN<45>ź<EFBFBD><C5BA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define MOUT_EN_HIGH 0x0301 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>EN<45>ź<EFBFBD><C5BA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ߡ<EFBFBD>
#define MOUT_SON_LOW 0x0310 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SON<4F>ź<EFBFBD><C5BA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define MOUT_SON_HIGH 0x0311 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SON<4F>ź<EFBFBD><C5BA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ߡ<EFBFBD>
#define MOUT_SEL_LOW 0x0320 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SEL<45>ź<EFBFBD><C5BA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define MOUT_SEL_HIGH 0x0321 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SEL<45>ź<EFBFBD><C5BA><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ߡ<EFBFBD>
#define COUNTER_DIR_POS 0x0400 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA><EFBFBD><EFBFBD>
#define COUNTER_DIR_NEG 0x0401 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><CEAA>
#define DIS_INTER_BUF1 0x0500 // <20><>1ʧЧ,<2C><>1<EFBFBD><31><EFBFBD><EFBFBD>,<2C><><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define DIS_INTER_BUF2 0x0501 // <20><>2ʧЧ,<2C><>2<EFBFBD><32><EFBFBD><EFBFBD>,<2C><><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define MOUT_PLUS_OFF 0x0600 // <20>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ź<EFBFBD>:<3A>ޡ<EFBFBD>
#define MOUT_PLUS_ON 0x0601 // <20>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ź<EFBFBD>:<3A><>
#define MOUT_SIGN_CW 0x0610 // <20>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ź<EFBFBD>:<3A><>ת<EFBFBD><D7AA>
#define MOUT_SIGN_CCW 0x0611 // <20>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ź<EFBFBD>:<3A><>ת
#define IS_AXIS_CMD(cmd) ( ((cmd) == POUT_CWCCW ) ||\
((cmd) == POUT_PLSDIR ) ||\
((cmd) == POUT_NORMAL ) ||\
((cmd) == POUT_XCHANGE ) ||\
((cmd) == POUT_DISABLE ) ||\
((cmd) == POUT_ENABLE_VAXIS1 ) ||\
((cmd) == POUT_ENABLE_ECD ) ||\
((cmd) == POUT_ENABLE_PWM ) ||\
((cmd) == POUT_ENABLE_BUSIO ) ||\
((cmd) == DATI_INTERPOLATION ) ||\
((cmd) == DATI_ECD1_FLOW ) ||\
((cmd) == DATI_ECD2_FLOW ) ||\
((cmd) == DATI_ECD1_MAPPING ) ||\
((cmd) == DATI_ECD2_MAPPING ) ||\
((cmd) == DATI_PWM ) ||\
((cmd) == DATI_BUS_IO ) ||\
((cmd) == MOUT_EN_LOW ) ||\
((cmd) == MOUT_EN_HIGH ) ||\
((cmd) == MOUT_SON_LOW ) ||\
((cmd) == MOUT_SON_HIGH ) ||\
((cmd) == MOUT_SEL_LOW ) ||\
((cmd) == MOUT_SEL_HIGH ) ||\
((cmd) == COUNTER_DIR_POS ) ||\
((cmd) == COUNTER_DIR_NEG ) ||\
((cmd) == DIS_INTER_BUF1 ) ||\
((cmd) == DIS_INTER_BUF2 ) ||\
((cmd) == MOUT_PLUS_OFF ) ||\
((cmd) == MOUT_PLUS_ON ) ||\
((cmd) == MOUT_SIGN_CW ) ||\
((cmd) == MOUT_SIGN_CCW ) ||\
0 )
// <20>岹1<E5B2B9><31><EFBFBD><EFBFBD>
#define INTER_BUF1_PARA(axisAddr) (axisAddr+0x02)
// <20>岹2<E5B2B9><32><EFBFBD><EFBFBD>
#define INTER_BUF2_PARA(axisAddr) (axisAddr+0x04)
// <20>岹<EFBFBD><E5B2B9><EFBFBD>ݻ<EFBFBD><DDBB><EFBFBD><EFBFBD><EFBFBD>1
#define INTER_BUF1_DATA(axisAddr) (axisAddr+0x06)
// <20>岹<EFBFBD><E5B2B9><EFBFBD>ݻ<EFBFBD><DDBB><EFBFBD><EFBFBD><EFBFBD>2
#define INTER_BUF2_DATA(axisAddr) (axisAddr+0x08)
#define MAX_SEGMENT_PER_BUF 16 // ÿ<><C3BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define MAX_PULSE_PER_SEGMENT 32767 // ÿ<><C3BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
// 0x00000000(Ĭ<><C4AC>ֵ): һֱ<D2BB><D6B1>ת
// R.31 R.30 00(<28><><EFBFBD><EFBFBD>|<7C><><EFBFBD><EFBFBD>)<29><>01(<28><><EFBFBD><EFBFBD>|<7C><><EFBFBD><EFBFBD>)<29><>10(<28><><EFBFBD><EFBFBD>|<7C><><EFBFBD><EFBFBD>)<29><>11(<28><><EFBFBD><EFBFBD>|<7C><><EFBFBD><EFBFBD>)
// R.25--R.0: <20><><EFBFBD><EFBFBD><EFBFBD>仯<EFBFBD><E4BBAF>λͼ<CEBB><CDBC>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD><CEBB><EFBFBD><EFBFBD>ַ
// <20><>Ϊ0xffffffff ʱ,<2C><><EFBFBD>ֶ<EFBFBD><D6B6>ڷ<EFBFBD><DAB7><EFBFBD><EFBFBD><EFBFBD>ʶִ<CAB6><D6B4>
#define DIR_POSPOS 0x00000000
#define DIR_POSNEG 0x40000000
#define DIR_NEGPOS 0x80000000
#define DIR_NEGNEG 0xC0000000
#define AXIS_DIR_CHG_VAL(n) ((n)&0x3FFFFFFF)
#define AXIS_DIR_USEBUF 0xFFFFFFFF // ʹ<><CAB9>ÿ<EFBFBD><C3BF><EFBFBD>ڷ<EFBFBD><DAB7><EFBFBD><EFBFBD><EFBFBD>־
// ÿ<>η<EFBFBD><CEB7><EFBFBD>&<26><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
// R.15 0(<28><><EFBFBD><EFBFBD>)<29><>1(<28><><EFBFBD><EFBFBD>)
// R.14--R.0: <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0--32767<36><37>
#define DATA_DIR_POS 0x0000
#define DATA_DIR_NEG 0x8000
#define DATA_DIR_CHG_VAL(n) ((n)&0x7FFF)
typedef struct
{
u16 axisId; // ʵ<><CAB5>ѡ<EFBFBD><D1A1> (AXIS_ID1 ~ AXIS_ID6)
u16 vaxisId; // <20><><EFBFBD><EFBFBD>ѡ<EFBFBD><D1A1> (VAXIS_ID1 ~ VAXIS_ECD)
u16 bufSel; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><D1A1> (BUF_SEL1 ~ BUF_SEL3)
u32 startEscNum; // <20><>ʼ<EFBFBD><CABC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> (0 ~ MAX_OUTNUM)
u32 partVxNum; // ÿ<>ζ<EFBFBD>Ӧ<EFBFBD><D3A6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> (MIN_OUTNUM ~ MAX_OUTNUM)
u32 dirAttr; // ʵ<><CAB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͷ<EFBFBD><CDB7><EFBFBD><EFBFBD>仯
u16 datBufLen; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч<EFBFBD><D0A7><EFBFBD>ݸ<EFBFBD><DDB8><EFBFBD> (1 ~ MAX_PULSE_PER_SEGMENT)
u16 datBuff[MAX_SEGMENT_PER_BUF]; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD> (15.<2E><>ִ<EFBFBD>з<EFBFBD><D0B7><EFBFBD>; .14~0<><30><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)
u16 sineOut; // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־. 0, <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>, 1, <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
} InterData;
#define SINE_MUTI (1.42f) // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>任ϵ<E4BBBB><CFB5>
// ʵ<><CAB5>ѡ<EFBFBD><D1A1>
#define AXIS_ID1 0x0001
#define AXIS_ID2 0x0002
#define AXIS_ID3 0x0003
#define AXIS_ID4 0x0004
#define AXIS_ID5 0x0005
#define AXIS_ID6 0x0006
#define IS_AXIS_ID(AXIS) (((AXIS) == AXIS_ID1) || \
((AXIS) == AXIS_ID2) || \
((AXIS) == AXIS_ID3) || \
((AXIS) == AXIS_ID4) || \
((AXIS) == AXIS_ID5) || \
((AXIS) == AXIS_ID6))
// <20><><EFBFBD>ü<EFBFBD><C3BC><EFBFBD><EFBFBD><EFBFBD>(L)
#define AXIS_COUNTER_L(axisAddr) (axisAddr+0x0A)
// <20><><EFBFBD>ü<EFBFBD><C3BC><EFBFBD><EFBFBD><EFBFBD>(H)
#define AXIS_COUNTER_H(axisAddr) (axisAddr+0x0C)
#define FPGA_PWM_MAX_VAL (0x3FF)
#define IS_AXIS_PWM_ID(AXIS) (((AXIS) == AXIS_ID3) || \
((AXIS) == AXIS_ID4))
#define IS_AXIS_PWM_FREQ(FREQ) (((FREQ) >= 0x01) && \
((FREQ) <= 0xFF))
#define IS_AXIS_PWM_VAL(VAL) (((VAL) >= 0x0000)&& \
((VAL) <= 0x03FF))
#define AXIS_PWM_FREQ(axisAddr) (axisAddr+0x0E) // PWM<57><4D>Ƶϵ<C6B5><CFB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>62.5K<EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD>(0x01~0xFF)
#define AXIS_PULSE_PWM(axisAddr) (axisAddr+0x10) // pulse PWM ֵ 10bit(0~0x3FF)
#define AXIS_SIGN_PWM(axisAddr) (axisAddr+0x12) // sign PWM ֵ 10bit(0~0x3FF)
/* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ
0,<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ0ʱ<EFBFBD><EFBFBD>ʾ<EFBFBD>˹<EFBFBD><EFBFBD>ܲ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
1,<EFBFBD><EFBFBD>ʹ<EFBFBD>ø<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ,<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֱ<EFBFBD>߲岹<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
2,ʵ<EFBFBD><EFBFBD>ֱ<EFBFBD>߲岹<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>費С<EFBFBD><EFBFBD> <EFBFBD><EFBFBD>ֵ x <EFBFBD><EFBFBD><EFBFBD><EFBFBD>2
*/
#define IS_AXIS_SINE_ID(AXIS) (((AXIS) == AXIS_ID1) || \
((AXIS) == AXIS_ID2) || \
((AXIS) == AXIS_ID3) || \
((AXIS) == AXIS_ID4) || \
((AXIS) == AXIS_ID5) || \
((AXIS) == AXIS_ID6))
#define AXIS_BUF1_SINE_OUT(axisAddr) (axisAddr+0x14) // BUF1<46><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define AXIS_BUF2_SINE_OUT(axisAddr) (axisAddr+0x16) // BUF2<46><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define AXIS_BUF1_SINE_OUT_H(axisAddr) (axisAddr+0x1A)
#define AXIS_BUF2_SINE_OUT_H(axisAddr) (axisAddr+0x1C)
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ѡ<EFBFBD><D1A1>
#define ECD_SEL1 0x0001
#define ECD_SEL2 0x0002
#define IS_ECD_SEL(ECD) (((ECD) == ECD_SEL1) || \
((ECD) == ECD_SEL2))
//------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
// <20><><EFBFBD>˿ڵ<CBBF>ַ
// FPGAӲ<41><D3B2><EFBFBD>汾(<28><>Ϊ<EFBFBD><CEAA>8λ<38><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,<2C><>8λ<38>汾)
#define FPGA_HARD_VERSION (VAXIS+0x00)
#define FPGA_PLOTTER_VER 0x01 // <20><>ī<EFBFBD><C4AB>ͼ<EFBFBD><CDBC>
#define FPGA_EMB_VER 0x02 // <20>廨<EFBFBD><E5BBA8>/<2F><><EFBFBD>߻<EFBFBD>
// FPGA<47><41><EFBFBD><EFBFBD><EFBFBD>汾(<28><>Ϊ<EFBFBD><CEAA>8λ,<2C><>8λ)
#define FPGA_SOFT_VERSION (VAXIS+0x02)
// <20><><EFBFBD><EFBFBD>״̬<D7B4>˿<EFBFBD>
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬<D7B4>˿<EFBFBD><CBBF>ж<EFBFBD>ȡ<EFBFBD><C8A1><EFBFBD>ݣ<EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ<EFBFBD>ж<EFBFBD><D0B6><EFBFBD>Ӧ<EFBFBD><D3A6>״̬<D7B4><CCAC>״̬λ .15 .14 .13 .12 .11 .10 .7 .6 .3 .2 Ϊ1ʱ<31><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϣ<D0B6><CFA3><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
// *<2A>ж<EFBFBD>Դ
#define VAXIS_STATUS (VAXIS+0x04)
#define VAXIS1_BUF1_RUNNING 0x0001 // <20><><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD>ִ<EFBFBD>б<EFBFBD>־
#define VAXIS1_BUF2_RUNNING 0x0002 // <20><><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><32><EFBFBD><EFBFBD>ִ<EFBFBD>б<EFBFBD>־
#define VAXIS1_BUF1_FINISH 0x0004 // <20><><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD>ɱ<EFBFBD>־*
#define VAXIS1_BUF2_FINISH 0x0008 // <20><><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><32><EFBFBD>ɱ<EFBFBD>־*
#define AXIS_ALARM_FLAG 0x2000 // ʵ<><CAB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͣ<EFBFBD><CDA3><EFBFBD><EFBFBD>־* (AXIS_ALM_STATUS)
#define ENCODER_ALARM_FLAG 0x4000 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϱ<D0B6>־* (ECD_INT_FLAGS)
#define INPUT_ALARM_FLAG 0x8000 // Input<75>½<EFBFBD><C2BD><EFBFBD><EFBFBD>жϱ<D0B6>־* (INPUT_INT_FLAGS)
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬
#define VAXIS_STATUS1 (VAXIS+0x0006)
#define VAXIS1_BUF1_ENABLE 0x0001 // <20><><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1<EFBFBD><31>Ч<EFBFBD><D0A7>־
#define VAXIS1_BUF2_ENABLE 0x0002 // <20><><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><32>Ч<EFBFBD><D0A7>־
#define VAXIS1_BUF3_ENABLE 0x0004 // <20><><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD>3<EFBFBD><33>Ч<EFBFBD><D0A7>־
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>жϱ<D0B6>־
#define ECD_INT_FLAGS (VAXIS+0x0008)
#define ECD1ZP_INT_FLAG 0x0001 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1 ZP<5A><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
#define ECD2ZP_INT_FLAG 0x0002 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2 ZP<5A><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
#define ECD_INT_MASK 0x0003
// <20><><EFBFBD><EFBFBD><EFBFBD>ź<EFBFBD><C5BA>жϱ<D0B6>־
#define INPUT_INT_FLAGS (VAXIS+0x0A)
#define INPUT01_INT_FLAG 0x0001 // <20><><EFBFBD><EFBFBD>1<EFBFBD>½<EFBFBD><C2BD><EFBFBD><EFBFBD>ж<EFBFBD>
#define INPUT02_INT_FLAG 0x0002 // <20><><EFBFBD><EFBFBD>2<EFBFBD>½<EFBFBD><C2BD><EFBFBD><EFBFBD>ж<EFBFBD>
#define INPUT03_INT_FLAG 0x0004 // <20><><EFBFBD><EFBFBD>3<EFBFBD>½<EFBFBD><C2BD><EFBFBD><EFBFBD>ж<EFBFBD>
#define INPUT04_INT_FLAG 0x0008 // <20><><EFBFBD><EFBFBD>4<EFBFBD>½<EFBFBD><C2BD><EFBFBD><EFBFBD>ж<EFBFBD>
#define INPUT05_INT_FLAG 0x0010 // <20><><EFBFBD><EFBFBD>5<EFBFBD>½<EFBFBD><C2BD><EFBFBD><EFBFBD>ж<EFBFBD>
#define INPUT06_INT_FLAG 0x0020 // <20><><EFBFBD><EFBFBD>6<EFBFBD>½<EFBFBD><C2BD><EFBFBD><EFBFBD>ж<EFBFBD>
#define INPUT07_INT_FLAG 0x0040 // <20><><EFBFBD><EFBFBD>7<EFBFBD>½<EFBFBD><C2BD><EFBFBD><EFBFBD>ж<EFBFBD>
#define INPUT08_INT_FLAG 0x0080 // <20><><EFBFBD><EFBFBD>8<EFBFBD>½<EFBFBD><C2BD><EFBFBD><EFBFBD>ж<EFBFBD>
#define INPUT09_INT_FLAG 0x0100 // <20><><EFBFBD><EFBFBD>9<EFBFBD>½<EFBFBD><C2BD><EFBFBD><EFBFBD>ж<EFBFBD>
#define INPUT10_INT_FLAG 0x0200 // <20><><EFBFBD><EFBFBD>10<31>½<EFBFBD><C2BD><EFBFBD><EFBFBD>ж<EFBFBD>
#define INPUT11_INT_FLAG 0x0400 // <20><><EFBFBD><EFBFBD>11<31>½<EFBFBD><C2BD><EFBFBD><EFBFBD>ж<EFBFBD>
#define INPUT12_INT_FLAG 0x0800 // <20><><EFBFBD><EFBFBD>12<31>½<EFBFBD><C2BD><EFBFBD><EFBFBD>ж<EFBFBD>
#define INPUT13_INT_FLAG 0x1000 // <20><><EFBFBD><EFBFBD>13<31>½<EFBFBD><C2BD><EFBFBD><EFBFBD>ж<EFBFBD>
#define INPUT14_INT_FLAG 0x2000 // <20><><EFBFBD><EFBFBD>14<31>½<EFBFBD><C2BD><EFBFBD><EFBFBD>ж<EFBFBD>
#define INPUT15_INT_FLAG 0x4000 // <20><><EFBFBD><EFBFBD>15<31>½<EFBFBD><C2BD><EFBFBD><EFBFBD>ж<EFBFBD>
#define INPUT16_INT_FLAG 0x8000 // <20><><EFBFBD><EFBFBD>16<31>½<EFBFBD><C2BD><EFBFBD><EFBFBD>ж<EFBFBD>
#define INPUT_INT_MASK 0xFFFF
// <20><><EFBFBD><EFBFBD>1<EFBFBD><31>ǰƵ<C7B0>ʣ<EFBFBD><CAA3><EFBFBD>λPPS<50><53><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡ (0<><30>4M)
#define CUR_VAXIS1_PPS_L (VAXIS+0x0C)
#define CUR_VAXIS1_PPS_H (VAXIS+0x0E)
// <20><>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5>
#define VAXIS1_END_FREQUENCY_L (VAXIS+0x10)
#define VAXIS1_END_FREQUENCY_H (VAXIS+0x12)
// <20><><EFBFBD><EFBFBD>1<EFBFBD><31>ǰ<EFBFBD><C7B0><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡ (0 <20><> 2^26-1)
#define CUR_VAXIS1_COUNTER_L (VAXIS+0x14)
#define CUR_VAXIS1_COUNTER_H (VAXIS+0x16)
// ʵ<><CAB5>1<EFBFBD><31><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD>з<EFBFBD><D0B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡ (-2^31-1 <20><> 2^31-1)
#define CUR_AXIS1_COUNTER_L (VAXIS+0x20)
#define CUR_AXIS1_COUNTER_H (VAXIS+0x22)
// ʵ<><CAB5>2<EFBFBD><32><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD>з<EFBFBD><D0B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡ (-2^31-1 <20><> 2^31-1)
#define CUR_AXIS2_COUNTER_L (VAXIS+0x24)
#define CUR_AXIS2_COUNTER_H (VAXIS+0x26)
// ʵ<><CAB5>3<EFBFBD><33><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD>з<EFBFBD><D0B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡ (-2^31-1 <20><> 2^31-1)
#define CUR_AXIS3_COUNTER_L (VAXIS+0x28)
#define CUR_AXIS3_COUNTER_H (VAXIS+0x2A)
// ʵ<><CAB5>4<EFBFBD><34><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD>з<EFBFBD><D0B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡ (-2^31-1 <20><> 2^31-1)
#define CUR_AXIS4_COUNTER_L (VAXIS+0x2C)
#define CUR_AXIS4_COUNTER_H (VAXIS+0x2E)
// ʵ<><CAB5>5<EFBFBD><35><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD>з<EFBFBD><D0B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡ (-2^31-1 <20><> 2^31-1)
#define CUR_AXIS5_COUNTER_L (VAXIS+0x30)
#define CUR_AXIS5_COUNTER_H (VAXIS+0x32)
// ʵ<><CAB5>6<EFBFBD><36><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD>з<EFBFBD><D0B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡ (-2^31-1 <20><> 2^31-1)
#define CUR_AXIS6_COUNTER_L (VAXIS+0x34)
#define CUR_AXIS6_COUNTER_H (VAXIS+0x36)
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1<EFBFBD><31><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD>з<EFBFBD><D0B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡ (-2^31-1 <20><> 2^31-1)
#define CUR_ECD1_COUNTER_L (VAXIS+0x40)
#define CUR_ECD1_COUNTER_H (VAXIS+0x42)
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><32><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD>з<EFBFBD><D0B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>λ:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡ (-2^31-1 <20><> 2^31-1)
#define CUR_ECD2_COUNTER_L (VAXIS+0x44)
#define CUR_ECD2_COUNTER_H (VAXIS+0x46)
// OP<4F><50><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD>λ:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡ (0 <20><> 2^32-1)
#define CUR_OP_COUNTER_L (VAXIS+0x48)
#define CUR_OP_COUNTER_H (VAXIS+0x4A)
// ZP<5A><50><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD>λ:<3A><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡ (0 <20><> 2^32-1)
#define CUR_ZP_COUNTER_L (VAXIS+0x4C)
#define CUR_ZP_COUNTER_H (VAXIS+0x4E)
// ʵ<>ᱨ<EFBFBD><E1B1A8>״̬<D7B4>˿<EFBFBD>
#define AXIS_ALM_STATUS (VAXIS+0x50)
#define AXIS1_ALM 0x0001 // <20><>1<EFBFBD><31><EFBFBD><EFBFBD>
#define AXIS2_ALM 0x0002 // <20><>2<EFBFBD><32><EFBFBD><EFBFBD>
#define AXIS3_ALM 0x0004 // <20><>3<EFBFBD><33><EFBFBD><EFBFBD>
#define AXIS4_ALM 0x0008 // <20><>4<EFBFBD><34><EFBFBD><EFBFBD>
#define AXIS5_ALM 0x0010 // <20><>5<EFBFBD><35><EFBFBD><EFBFBD>
#define AXIS6_ALM 0x0020 // <20><>6<EFBFBD><36><EFBFBD><EFBFBD>
#define AXIS_ALM_MASK 0x003F
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬<D7B4>˿<EFBFBD>
#define ECD_SIGNAL_STATUS (VAXIS+0x52)
#define BP1_STA 0x0001 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1BP
#define AP1_STA 0x0802 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1AP
#define ZP1_STA 0x0004 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>1ZP
#define BP2_STA 0x0008 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2BP
#define AP2_STA 0x0010 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2AP
#define ZP2_STA 0x0020 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2ZP
#define ECD_STA_MASK 0x003F
// <20><>׼<EFBFBD><D7BC><EFBFBD><EFBFBD>״̬<D7B4>˿<EFBFBD>
#define INPUT_STATUS (VAXIS+0x54)
#define INPUT1_STA 0x0001 // <20><><EFBFBD><EFBFBD>1
#define INPUT2_STA 0x0002 // <20><><EFBFBD><EFBFBD>2
#define INPUT3_STA 0x0004 // <20><><EFBFBD><EFBFBD>3
#define INPUT4_STA 0x0008 // <20><><EFBFBD><EFBFBD>4
#define INPUT5_STA 0x0010 // <20><><EFBFBD><EFBFBD>5
#define INPUT6_STA 0x0020 // <20><><EFBFBD><EFBFBD>6
#define INPUT7_STA 0x0040 // <20><><EFBFBD><EFBFBD>7
#define INPUT8_STA 0x0080 // <20><><EFBFBD><EFBFBD>8
#define INPUT9_STA 0x0100 // <20><><EFBFBD><EFBFBD>9
#define INPUT10_STA 0x0200 // <20><><EFBFBD><EFBFBD>10
#define INPUT11_STA 0x0400 // <20><><EFBFBD><EFBFBD>11
#define INPUT12_STA 0x0800 // <20><><EFBFBD><EFBFBD>12
#define INPUT13_STA 0x1000 // <20><><EFBFBD><EFBFBD>13
#define INPUT14_STA 0x2000 // <20><><EFBFBD><EFBFBD>14
#define INPUT15_STA 0x4000 // <20><><EFBFBD><EFBFBD>15
#define INPUT16_STA 0x8000 // <20><><EFBFBD><EFBFBD>16
//--------------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------------
// <20><>ʼ<EFBFBD><CABC>FPGA
void InitEmbFpga(void);
//--------------------------------------------------------------------------------------------------------------
// <20><><EFBFBD>˿<EFBFBD>
// <20><>ȡ<EFBFBD>汾
u16 GetFpgaHardVersion(void);
u16 GetFpgaSoftVersion(void);
// <20>õ<EFBFBD><C3B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬
u16 GetRunStatus(void);
// <20><>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬
u16 GetRunStatus1(void);
// <20>õ<EFBFBD><C3B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˿<EFBFBD><CBBF>ж<EFBFBD><D0B6><EFBFBD>Ϣ
u16 GetInputIntFlags(void);
// <20>õ<EFBFBD><C3B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD><D0B6><EFBFBD>Ϣ
u16 GetEcdIntFlags(void);
// <20>õ<EFBFBD><C3B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5>
u32 GetVAxisPPS(u16 vaxisId);
// <20><>ȡ<EFBFBD><C8A1>һ<EFBFBD><D2BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ٶ<EFBFBD>
u32 GetLastVAxisFrequency(u16 vaxisId);
// <20>õ<EFBFBD><C3B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC><EFBFBD>ֵ
u32 GetVAxisCounter(u16 vaxisId);
// <20><>ȡʵ<C8A1><CAB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
s32 GetAxisCounter(u16 axisId);
// <20>õ<EFBFBD><C3B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
s32 GetEcdCounter(u16 ecdId);
// <20><>ȡOP<4F><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
u32 GetOPCounter(void);
// <20><>ȡZP<5A><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
u32 GetZPCounter(void);
// <20>õ<EFBFBD>ʵ<EFBFBD>ᱨ<EFBFBD><E1B1A8><EFBFBD><EFBFBD>Ϣ
u16 GetAlarmValue(void);
// <20>õ<EFBFBD><C3B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ź<EFBFBD>״̬
u16 GetEcdStatus(void);
// <20>õ<EFBFBD><C3B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ź<EFBFBD>״̬
u16 GetInputStatus(void);
//--------------------------------------------------------------------------------------------------------------
// д<>˿<EFBFBD>
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
void SetVAxisConfig(u16 cfg);
// <20><><EFBFBD><EFBFBD>ȫ<EFBFBD><C8AB><EFBFBD>жϱ<D0B6>־
void CleanAllIntFlag(void);
// <20><><EFBFBD><EFBFBD><EFBFBD>˶<EFBFBD>
int StartVAxisRun(VAxisCmdStr * pCmd);
// ֹͣ<CDA3><D6B9>ǰ<EFBFBD>˶<EFBFBD>
int StopVAxisRun(u16 vaxisId);
// <20>ٶȽ<D9B6><C8BD><EFBFBD><EFBFBD>ٶ<EFBFBD><D9B6><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD>
void StopSpdCtrl(u16 vaxisId);
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD>
void ClearEcdCounter(u16 ecdId);
void ReetEcdABZLevel(u16 ecdId); // ABZ<42><5A>ƽ<EFBFBD>źŸ<C5BA>λ
void SetEcdAPLevelNegative(u16 ecdId); // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>APȡ<50><C8A1>
void SetEcdAZLevelNegative(u16 ecdId); // AP ZP ȡ<><C8A1>
void SetEcdZPLevelNegative(u16 ecdId); // ZPȡ<50><C8A1>
void SetOpOutOn(void); // OP<4F><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
void SetOpOutOff(void);
void SetZpOutOn(void); // ZP<5A><50><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
void SetZpOutOff(void);
// <20><><EFBFBD>ñ<EFBFBD><C3B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
void SetAxisAlarmConfig(u16 axisId, u16 alm);
//--------------------------------------------------------------------------------------------------------------
// <20><><EFBFBD><EFBFBD>OP<4F><50><EFBFBD><EFBFBD><EFBFBD>ķ<EFBFBD>Ƶϵ<C6B5><CFB5>
void SetOpDivision(u16 div);
// <20><><EFBFBD><EFBFBD>OP<4F><50><EFBFBD><EFBFBD>ֵ
void SetOpCounter(s32 cnt);
// <20><><EFBFBD><EFBFBD>ZP<5A><50><EFBFBD><EFBFBD>ֵ
void SetZpCounter(s32 cnt);
// <20><><EFBFBD>ñ<EFBFBD><C3B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
void SetEcdCounter(u16 ecdId, s32 cnt);
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>˿<EFBFBD><CBBF>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD>
void SetInputInt(u16 cfg);
// <20><><EFBFBD><EFBFBD><EFBFBD>źſ<C5BA><C5BF><EFBFBD>
void Output1On(void);
void Output1Off(void);
void Output2On(void);
void Output2Off(void);
void Output3On(void);
void Output3Off(void);
void Output4On(void);
void Output4Off(void);
void Output5On(void);
void Output5Off(void);
void Output6On(void);
void Output6Off(void);
void Output7On(void);
void Output7Off(void);
void Output8On(void);
void Output8Off(void);
u8 GetOutputVal(int num);
//--------------------------------------------------------------------------------------------------------------
// <20><><EFBFBD><EFBFBD>ʵ<EFBFBD><CAB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
void SetAxisConfig(u16 axisId, u16 cfg);
// д<>岹<EFBFBD><E5B2B9><EFBFBD><EFBFBD>
int WriteInterData(InterData * pCmd);
// <20><><EFBFBD>ձ<EFBFBD>
void CleanAxisBuff(u16 axisId, u16 bufSel);
// <20><><EFBFBD><EFBFBD>ʵ<EFBFBD><CAB5><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ
void SetAxisCounter(u16 axisId, s32 cnt);
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>PWM<57><4D>Ƶϵ<C6B5><CFB5>
void SetAxisPwmFreq(u16 axisId, u16 freq);
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>PULSE<53><45>PWMֵ
void SetAxisPulsePwm(u16 axisId, u16 val);
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SIGN<47><4E>PWMֵ
void SetAxisSignPwm(u16 axisId, u16 val);
//--------------------------------------------------------------------------------------------------------------
void RegInputIntProc(u16 intcfg, void(*inputProc)(void));
void RegEcdInputProc(u16 ecdId, void(*ecdProc)(void));
// <20>ⲿ<EFBFBD>ж<EFBFBD><D0B6><EFBFBD>Ӧ<EFBFBD><D3A6><EFBFBD><EFBFBD>
void FpgaIntProc(void);
//--------------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------------
void SetExoutEnOn(void);
void SetExoutEnOff(void);
void SetExOutValue(u16 addr, u8 value);
u8 GetExOutValue(u16 addr);
void FlushExOutputs(void);
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>չIO<49><4F><EFBFBD><EFBFBD>״̬
// addr: 1--MAX_EXIO_ADDR
// value: SENSOR_ON<4F><4E>Bit_RESET<45><54> <20><> SENSOR_OFF<46><46>Bit_SET<45><54>
void SetExOutput(u16 addr, u8 value);
// <20><>ȡIO<49><4F>չ<EFBFBD><D5B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬
// addr: 1--MAX_EXIO_ADDR
// <20><><EFBFBD><EFBFBD>: SENSOR_ON<4F><4E>Bit_RESET<45><54> <20><> SENSOR_OFF<46><46>Bit_SET<45><54>
u8 GetExInput(u16 addr);
void GetExInputs(u16 * pBuf);
//--------------------------------------------------------------------------------------------------------------
#endif
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