53 lines
1.4 KiB
C
53 lines
1.4 KiB
C
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#ifndef __COREFMC_H__
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#define __COREFMC_H__
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//---------------------------------------------------------------------------------
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#include "config.h"
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//---------------------------------------------------------------------------------
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//---------------------------------------------------------------------------------
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// FMC <20><><EFBFBD><EFBFBD><EFBFBD>Ϲҽ<CFB9> SDAM, FPGA, <20><><EFBFBD>Լ<EFBFBD><D4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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// BANK1 <20><>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>
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#define Bank1_SRAM1_ADDR ((u32)0x60000000) // NE1 <20><><EFBFBD><EFBFBD>FPGA
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#define Bank1_SRAM2_ADDR ((u32)0x64000000) // NE2
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#define Bank1_SRAM3_ADDR ((u32)0x68000000) // NE3
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#define Bank1_SRAM4_ADDR ((u32)0x6C000000) // NE4
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#define CORE_FPGA_ADDR_BEG Bank1_SRAM1_ADDR
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#define CORE_FPGA_BANK FSMC_Bank1_NORSRAM1
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// SDRAM BANK
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#define SDRAM_BANK1_ADDR ((u32)0xC0000000UL)
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#define SDRAM_BANK2_ADDR ((u32)0xD0000000UL)
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#define CORE_SDRAM1_ADDR_BEG SDRAM_BANK1_ADDR
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#define CORE_SDRAM2_ADDR_BEG SDRAM_BANK2_ADDR
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#define CORE_SDRAM1_SIZE (4*1024*1024*4*16/8) // <20>ֽ<EFBFBD><D6BD><EFBFBD> 32M <20>ֽ<EFBFBD>
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#define CORE_SDRAM2_SIZE (4*1024*1024*4*16/8) // <20>ֽ<EFBFBD><D6BD><EFBFBD> 32M <20>ֽ<EFBFBD>
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//---------------------------------------------------------------------------------
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// <20><>ʼ<EFBFBD><CABC>FMC
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void InitCoreFmc(void);
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// д<><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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void FmcWriteReg(u32 wAddr, u16 data);
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// <20><>ȡ<EFBFBD><C8A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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u16 FmcReadReg(u32 rAddr);
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// д<><D0B4><EFBFBD>ݵ<EFBFBD><DDB5>̶<EFBFBD><CCB6><EFBFBD>ַ
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void FmcWriteConstBuf(u32 wAddr, u16* pBuffer, u32 num);
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// <20>ӹ̶<D3B9><CCB6><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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void FmcReadConstBuf(u32 rAddr, u16* pBuffer, u32 num);
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#endif
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