140 lines
5.2 KiB
C
140 lines
5.2 KiB
C
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#ifndef __STFLASH_H__
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#define __STFLASH_H__
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#include "config.h"
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#ifndef STM32_FLASH_BASE
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#define STM32_FLASH_BASE FLASH_BASE // STM32 FLASH <20><><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַ
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#endif
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#ifdef FLASH_END
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#define STM32_FLASH_SIZE (FLASH_END - FLASH_BASE + 1) // <20><>ѡSTM32<33><32>FLASH<53><48><EFBFBD><EFBFBD><EFBFBD><EFBFBD>С(<28><>λΪ<CEBB>ֽ<EFBFBD>)
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#else
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#ifdef FLASH_BANK1_END
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#define STM32_FLASH_SIZE (FLASH_BANK1_END - FLASH_BASE + 1) // <20><>ѡSTM32<33><32>FLASH<53><48><EFBFBD><EFBFBD><EFBFBD><EFBFBD>С(<28><>λΪ<CEBB>ֽ<EFBFBD>)
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#endif
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#endif
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#if (__CORTEX_M == 0)
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/*
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С<EFBFBD><EFBFBD>64K<EFBFBD><EFBFBD>ÿ<EFBFBD><EFBFBD><EFBFBD>洢<EFBFBD>黮<EFBFBD><EFBFBD>Ϊ1K<EFBFBD>ֽڵ<EFBFBD>ҳ<EFBFBD><EFBFBD>(F03x, F04x, F05x)
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<EFBFBD><EFBFBD><EFBFBD>ڵ<EFBFBD><EFBFBD><EFBFBD>128K<EFBFBD><EFBFBD>ÿ<EFBFBD><EFBFBD><EFBFBD>洢<EFBFBD>黮<EFBFBD><EFBFBD>Ϊ2K<EFBFBD>ֽڵ<EFBFBD>ҳ<EFBFBD><EFBFBD>(F07x, F09x)
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*/
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#if (STM32_FLASH_SIZE <= (64*1024))
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#define STM32_FLASH_SEC_SIZE (1*1024) //
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#else
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#define STM32_FLASH_SEC_SIZE (2*1024) //
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#endif
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#define STM32_FLASH_SEC_NUM (STM32_FLASH_SIZE/STM32_FLASH_SEC_SIZE) // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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#define STM32_FLASH_RW_SIZE (STM32_FLASH_SEC_SIZE) // ÿ<>ζ<EFBFBD>д<EFBFBD><D0B4><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD>
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#elif (__CORTEX_M == 3)
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/*
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С<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ʒ<EFBFBD><EFBFBD><EFBFBD>洢<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ4K<EFBFBD><EFBFBD>64λ<EFBFBD><EFBFBD>ÿ<EFBFBD><EFBFBD><EFBFBD>洢<EFBFBD>黮<EFBFBD><EFBFBD>Ϊ32<EFBFBD><EFBFBD>1K<EFBFBD>ֽڵ<EFBFBD>ҳ<EFBFBD><EFBFBD>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ʒ<EFBFBD><EFBFBD><EFBFBD>洢<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ16K<EFBFBD><EFBFBD>64λ<EFBFBD><EFBFBD>ÿ<EFBFBD><EFBFBD><EFBFBD>洢<EFBFBD>黮<EFBFBD><EFBFBD>Ϊ128<EFBFBD><EFBFBD>1K<EFBFBD>ֽڵ<EFBFBD>ҳ<EFBFBD><EFBFBD>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ʒ<EFBFBD><EFBFBD><EFBFBD>洢<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ64K<EFBFBD><EFBFBD>64λ<EFBFBD><EFBFBD>ÿ<EFBFBD><EFBFBD><EFBFBD>洢<EFBFBD>黮<EFBFBD><EFBFBD>Ϊ256<EFBFBD><EFBFBD>2K<EFBFBD>ֽڵ<EFBFBD>ҳ<EFBFBD><EFBFBD>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ͳ<EFBFBD>Ʒ<EFBFBD><EFBFBD><EFBFBD>洢<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ32K<EFBFBD><EFBFBD>64λ<EFBFBD><EFBFBD>ÿ<EFBFBD><EFBFBD><EFBFBD>洢<EFBFBD>黮<EFBFBD><EFBFBD>Ϊ128<EFBFBD><EFBFBD>2K<EFBFBD>ֽڵ<EFBFBD>ҳ<EFBFBD><EFBFBD>
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*/
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#if (STM32_FLASH_SIZE <= (128*1024))
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#define STM32_FLASH_SEC_SIZE (1*1024) // ÿ<><C3BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD> 1K<31>ֽ<EFBFBD>
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#else
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#define STM32_FLASH_SEC_SIZE (2*1024) // ÿ<><C3BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD> 2K<32>ֽ<EFBFBD>
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#endif
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#define STM32_FLASH_SEC_NUM (STM32_FLASH_SIZE/STM32_FLASH_SEC_SIZE) // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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#define STM32_FLASH_RW_SIZE (STM32_FLASH_SEC_SIZE) // ÿ<>ζ<EFBFBD>д<EFBFBD><D0B4><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD>
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#elif (__CORTEX_M == 4)
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// STM32 FLASH <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַ
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#define STM32_FLASH_ADDR_SECTOR_0 ((u32)(STM32_FLASH_BASE + 0x000000)) //<2F><><EFBFBD><EFBFBD> 0 <20><>ʼ<EFBFBD><CABC>ַ, 16 Kbytes
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#define STM32_FLASH_ADDR_SECTOR_1 ((u32)(STM32_FLASH_BASE + 0x004000)) //<2F><><EFBFBD><EFBFBD> 1 <20><>ʼ<EFBFBD><CABC>ַ, 16 Kbytes
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#define STM32_FLASH_ADDR_SECTOR_2 ((u32)(STM32_FLASH_BASE + 0x008000)) //<2F><><EFBFBD><EFBFBD> 2 <20><>ʼ<EFBFBD><CABC>ַ, 16 Kbytes
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#define STM32_FLASH_ADDR_SECTOR_3 ((u32)(STM32_FLASH_BASE + 0x00C000)) //<2F><><EFBFBD><EFBFBD> 3 <20><>ʼ<EFBFBD><CABC>ַ, 16 Kbytes
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#define STM32_FLASH_ADDR_SECTOR_4 ((u32)(STM32_FLASH_BASE + 0x010000)) //<2F><><EFBFBD><EFBFBD> 4 <20><>ʼ<EFBFBD><CABC>ַ, 64 Kbytes
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#define STM32_FLASH_ADDR_SECTOR_5 ((u32)(STM32_FLASH_BASE + 0x020000)) //<2F><><EFBFBD><EFBFBD> 5 <20><>ʼ<EFBFBD><CABC>ַ, 128 Kbytes
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#define STM32_FLASH_ADDR_SECTOR_6 ((u32)(STM32_FLASH_BASE + 0x040000)) //<2F><><EFBFBD><EFBFBD> 6 <20><>ʼ<EFBFBD><CABC>ַ, 128 Kbytes
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#define STM32_FLASH_ADDR_SECTOR_7 ((u32)(STM32_FLASH_BASE + 0x060000)) //<2F><><EFBFBD><EFBFBD> 7 <20><>ʼ<EFBFBD><CABC>ַ, 128 Kbytes
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#if (STM32_FLASH_SIZE > (512*1024))
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#define STM32_FLASH_ADDR_SECTOR_8 ((u32)(STM32_FLASH_BASE + 0x080000)) //<2F><><EFBFBD><EFBFBD> 8 <20><>ʼ<EFBFBD><CABC>ַ, 128 Kbytes
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#define STM32_FLASH_ADDR_SECTOR_9 ((u32)(STM32_FLASH_BASE + 0x0A0000)) //<2F><><EFBFBD><EFBFBD> 9 <20><>ʼ<EFBFBD><CABC>ַ, 128 Kbytes
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#define STM32_FLASH_ADDR_SECTOR_10 ((u32)(STM32_FLASH_BASE + 0x0C0000)) //<2F><><EFBFBD><EFBFBD> 10 <20><>ʼ<EFBFBD><CABC>ַ, 128 Kbytes
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#define STM32_FLASH_ADDR_SECTOR_11 ((u32)(STM32_FLASH_BASE + 0x0E0000)) //<2F><><EFBFBD><EFBFBD> 11 <20><>ʼ<EFBFBD><CABC>ַ, 128 Kbytes
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#define STM32_FLASH_SEC_NUM 12
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#else
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#define STM32_FLASH_SEC_NUM 8 // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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#endif
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#define STM32_FLASH_SIZE_SECTOR_0 ((u32)(16*1024)) //<2F><><EFBFBD><EFBFBD> 0 <20><>С, 16 Kbytes
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#define STM32_FLASH_SIZE_SECTOR_1 ((u32)(16*1024)) //<2F><><EFBFBD><EFBFBD> 1 <20><>С, 16 Kbytes
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#define STM32_FLASH_SIZE_SECTOR_2 ((u32)(16*1024)) //<2F><><EFBFBD><EFBFBD> 2 <20><>С, 16 Kbytes
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#define STM32_FLASH_SIZE_SECTOR_3 ((u32)(16*1024)) //<2F><><EFBFBD><EFBFBD> 3 <20><>С, 16 Kbytes
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#define STM32_FLASH_SIZE_SECTOR_4 ((u32)(64*1024)) //<2F><><EFBFBD><EFBFBD> 4 <20><>С, 64 Kbytes
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#define STM32_FLASH_SIZE_SECTOR_5 ((u32)(128*1024)) //<2F><><EFBFBD><EFBFBD> 5 <20><>С, 128 Kbytes
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#define STM32_FLASH_SIZE_SECTOR_6 ((u32)(128*1024)) //<2F><><EFBFBD><EFBFBD> 6 <20><>С, 128 Kbytes
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#define STM32_FLASH_SIZE_SECTOR_7 ((u32)(128*1024)) //<2F><><EFBFBD><EFBFBD> 7 <20><>С, 128 Kbytes
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#if (STM32_FLASH_SIZE > (512*1024))
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#define STM32_FLASH_SIZE_SECTOR_8 ((u32)(128*1024)) //<2F><><EFBFBD><EFBFBD> 8 <20><>С, 128 Kbytes
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#define STM32_FLASH_SIZE_SECTOR_9 ((u32)(128*1024)) //<2F><><EFBFBD><EFBFBD> 9 <20><>С, 128 Kbytes
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#define STM32_FLASH_SIZE_SECTOR_10 ((u32)(128*1024)) //<2F><><EFBFBD><EFBFBD> 10 <20><>С, 128 Kbytes
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#define STM32_FLASH_SIZE_SECTOR_11 ((u32)(128*1024)) //<2F><><EFBFBD><EFBFBD> 11 <20><>С, 128 Kbytes
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#endif
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#define STM32_FLASH_RW_SIZE (2*1024) // ÿ<>ζ<EFBFBD>д<EFBFBD><D0B4><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD>
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#endif
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#define STM32_APP_ADDR (STM32_FLASH_BASE+STM32_BOOT_SIZE) // Ӧ<>ó<EFBFBD><C3B3><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַ(<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>FLASH)
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#ifndef STF_UPDATE_SIZE
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#define STF_UPDATE_SIZE (0) // <20><><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC>洢<EFBFBD><E6B4A2><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD>С
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#endif
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#ifndef STM32_PARA_SIZE
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#define STM32_PARA_SIZE (0) // <20><><EFBFBD><EFBFBD><EFBFBD>洢<EFBFBD><E6B4A2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>С
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#endif
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#ifdef STM32_FLASH_SEC_SIZE
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#define MARK_SIZE (STM32_FLASH_RW_SIZE) // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>־<EFBFBD>洢<EFBFBD><E6B4A2><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD>С
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#define STF_UPDATE_BEGIN (STM32_FLASH_BASE+STM32_FLASH_SIZE-STM32_PARA_SIZE-STF_UPDATE_SIZE-MARK_SIZE)
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#define STM32_PARA_ADDR (STM32_FLASH_BASE+STM32_FLASH_SIZE-STM32_PARA_SIZE)
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#endif
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//-------------------------------------------------------------------------
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// Cortex-M4<4D><34><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,FLASH<53><48><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>С<EFBFBD><D0A1>һ<EFBFBD><D2BB>,<2C><><EFBFBD><EFBFBD>д<EFBFBD><D0B4>
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#ifndef NO_BUFF_WHEN_WT
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#define NO_BUFF_WHEN_WT 0
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#endif
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//-------------------------------------------------------------------------
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int GetFlashSectorIdx(u32 faddr);
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int STMFlashErase(u32 secIdx, int secnums);
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int STMFlashRead(u32 rdAddr, u16 * pBuffer, u16 hwNumToWrite);
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int STMFlashCheck(u32 ckAddr, u16 * pBuffer, u16 hwNumOfChekc);
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int STMFlashWrite(u32 wrAddr, u16 * pBuffer, u16 hwNumToWrite, int svwhenera);
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//-------------------------------------------------------------------------
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#endif
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