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.cproject
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.cproject
Normal file
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|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
|
||||
<storageModule moduleId="org.eclipse.cdt.core.settings">
|
||||
<cconfiguration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094">
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094" moduleId="org.eclipse.cdt.core.settings" name="Debug">
|
||||
<externalSettings />
|
||||
<extensions>
|
||||
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser" />
|
||||
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser" />
|
||||
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser" />
|
||||
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser" />
|
||||
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser" />
|
||||
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser" />
|
||||
</extensions>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<configuration artifactName="rtthread" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094" name="Debug" parent="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug">
|
||||
<folderInfo id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094." name="/" resourcePath="">
|
||||
<toolChain id="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug.1201710416" name="ARM Cross GCC" superClass="ilg.gnuarmeclipse.managedbuild.cross.toolchain.elf.debug">
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash.251260409" name="Create flash image" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createflash" useByScannerDiscovery="false" value="true" valueType="boolean" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createlisting.1365878149" name="Create extended listing" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.createlisting" useByScannerDiscovery="false" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize.709136944" name="Print size" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.addtools.printsize" useByScannerDiscovery="false" value="true" valueType="boolean" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.1986446770" name="Optimization Level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.level.none" valueType="enumerated" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength.1312975261" name="Message length (-fmessage-length=0)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.messagelength" useByScannerDiscovery="true" value="false" valueType="boolean" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar.1538128212" name="'char' is signed (-fsigned-char)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.signedchar" useByScannerDiscovery="true" value="false" valueType="boolean" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections.2136804218" name="Function sections (-ffunction-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.functionsections" useByScannerDiscovery="true" value="true" valueType="boolean" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections.244767666" name="Data sections (-fdata-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.optimization.datasections" useByScannerDiscovery="true" value="true" valueType="boolean" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.1055848773" name="Debug level" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.level.default" valueType="enumerated" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.501941135" name="Debug format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.debugging.format.dwarf2" valueType="enumerated" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name.1696308067" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.name" useByScannerDiscovery="false" value="GNU Tools for ARM Embedded Processors" valueType="string" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.architecture.1558403188" name="Architecture" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.architecture" useByScannerDiscovery="false" value="ilg.gnuarmeclipse.managedbuild.cross.option.architecture.arm" valueType="enumerated" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family.749415257" name="ARM family" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.family" useByScannerDiscovery="false" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.mcpu.cortex-m3" valueType="enumerated" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset.2114153533" name="Instruction set" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset" useByScannerDiscovery="false" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.instructionset.thumb" valueType="enumerated" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix.1600865811" name="Prefix" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.prefix" useByScannerDiscovery="false" value="arm-none-eabi-" valueType="string" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.c.1109963929" name="C compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.c" useByScannerDiscovery="false" value="gcc" valueType="string" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp.1040883831" name="C++ compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.cpp" useByScannerDiscovery="false" value="g++" valueType="string" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.ar.1678200391" name="Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.ar" useByScannerDiscovery="false" value="ar" valueType="string" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy.1171840296" name="Hex/Bin converter" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objcopy" useByScannerDiscovery="false" value="objcopy" valueType="string" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump.342604837" name="Listing generator" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.objdump" useByScannerDiscovery="false" value="objdump" valueType="string" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.size.898269225" name="Size command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.size" useByScannerDiscovery="false" value="size" valueType="string" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.make.2016398076" name="Build command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.make" useByScannerDiscovery="false" value="make" valueType="string" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm.1606171496" name="Remove command" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.command.rm" useByScannerDiscovery="false" value="rm" valueType="string" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.id.540792084" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.toolchain.id" useByScannerDiscovery="false" value="1287942917" valueType="string" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.architecture.430121817" name="Architecture" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.architecture" useByScannerDiscovery="false" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.arch.none" valueType="enumerated" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.966735324" name="Float ABI" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.abi.default" valueType="enumerated" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn.1381561249" name="Enable all common warnings (-Wall)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.warnings.allwarn" useByScannerDiscovery="true" value="true" valueType="boolean" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.target.other.2041717463" name="Other target flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.target.other" useByScannerDiscovery="true" value="" valueType="string" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.1463655269" name="FPU Type" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit" useByScannerDiscovery="true" value="ilg.gnuarmeclipse.managedbuild.cross.option.arm.target.fpu.unit.default" valueType="enumerated" />
|
||||
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform.1798638225" isAbstract="false" osList="all" superClass="ilg.gnuarmeclipse.managedbuild.cross.targetPlatform" />
|
||||
<builder buildPath="${workspace_loc:/qemu-vexpress-a9}/Debug" cleanBuildTarget="clean2" id="ilg.gnuarmeclipse.managedbuild.cross.builder.1736709688" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="GNU Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="ilg.gnuarmeclipse.managedbuild.cross.builder" />
|
||||
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.1810966071" name="GNU ARM Cross Assembler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler">
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor.1072524326" name="Use preprocessor" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.usepreprocessor" useByScannerDiscovery="false" value="true" valueType="boolean" />
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths.161242639" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.include.paths" useByScannerDiscovery="true" valueType="includePath">
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}}"" />
|
||||
</option>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs.1521934876" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.defs" useByScannerDiscovery="true" />
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.flags.1325367962" name="Assembler flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.assembler.flags" useByScannerDiscovery="false" valueType="stringList">
|
||||
<listOptionValue builtIn="false" value="-mimplicit-it=thumb" />
|
||||
</option>
|
||||
<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input.1843333483" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.assembler.input" />
|
||||
</tool>
|
||||
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1570350559" name="GNU ARM Cross C Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler">
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths.634882052" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.paths" useByScannerDiscovery="true" valueType="includePath">
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}/drivers}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}/applications/fram}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}/applications/ADC}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}/applications/RS232}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}/applications/config}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}/applications/thread}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}/applications/IO}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}/applications/AIR820}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}/applications/Modbus}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}/applications/OLED}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}/drivers//include}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}/drivers//include//config}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}/libraries//CMSIS//Device//ST//STM32F1xx//Include}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}/libraries//CMSIS//Include}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}/libraries//CMSIS//RTOS//Template}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}/libraries//STM32F1xx_HAL_Driver//Inc}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}/libraries//STM32F1xx_HAL_Driver//Inc//Legacy}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}/.}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}/applications}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//.}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//packages/agile_modbus-v1.1.2/inc}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//packages/agile_modbus-v1.1.2/util}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//packages/rs485-latest/inc}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//packages/ssd1306-latest/inc}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/drivers/include}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/drivers/spi}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/finsh}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/libc/compilers/common/include}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/libc/compilers/newlib}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/libc/posix/io/epoll}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/libc/posix/io/eventfd}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/libc/posix/io/poll}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/libc/posix/ipc}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/include}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/libcpu/arm/common}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/libcpu/arm/cortex-m3}"" />
|
||||
</option>
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs.100549972" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.defs" useByScannerDiscovery="true" valueType="definedSymbols">
|
||||
<listOptionValue builtIn="false" value="SOC_FAMILY_STM32" />
|
||||
<listOptionValue builtIn="false" value="SOC_SERIES_STM32F1" />
|
||||
<listOptionValue builtIn="false" value="USE_HAL_DRIVER" />
|
||||
<listOptionValue builtIn="false" value="STM32F103xE" />
|
||||
</option>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.other.2133065240" name="Other compiler flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.other" useByScannerDiscovery="true" value="" valueType="string" />
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.files.714348818" name="Include files (-include)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.compiler.include.files" useByScannerDiscovery="true" valueType="includeFiles">
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/rtconfig_preinc.h}"" />
|
||||
</option>
|
||||
<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.992053063" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input" />
|
||||
</tool>
|
||||
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.869072473" name="Cross ARM C Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker">
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.gcsections.1167322178" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.gcsections" useByScannerDiscovery="false" value="true" valueType="boolean" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.nostart.351692886" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.nostart" useByScannerDiscovery="false" value="false" valueType="boolean" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.nostdlibs.1009243715" name="No startup or default libs (-nostdlib)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.nostdlibs" useByScannerDiscovery="false" value="false" valueType="boolean" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.nodeflibs.2016026082" name="Do not use default libraries (-nodefaultlibs)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.nodeflibs" useByScannerDiscovery="false" value="false" valueType="boolean" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.usenewlibnano.923990336" name="Use newlib-nano (--specs=nano.specs)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.usenewlibnano" useByScannerDiscovery="false" value="false" valueType="boolean" />
|
||||
<option defaultValue="true" id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.shared.548869459" name="Shared (-shared)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.shared" useByScannerDiscovery="false" valueType="boolean" />
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.scriptfile.1818777301" name="Script files (-T)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.scriptfile" useByScannerDiscovery="false" valueType="stringList">
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//linkscripts//STM32F103RC//link.lds}"" />
|
||||
</option>
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.libs.1135656995" name="Libraries (-l)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.libs" useByScannerDiscovery="false" valueType="libs">
|
||||
<listOptionValue builtIn="false" value="c " />
|
||||
<listOptionValue builtIn="false" value="m " />
|
||||
</option>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.paths.36884122" name="Library search path (-L)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.paths" useByScannerDiscovery="false" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.other.396049466" name="Other linker flags" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.other" useByScannerDiscovery="false" value="" valueType="string" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.cref.1645737861" name="Cross reference (-Xlinker --cref)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.c.linker.cref" useByScannerDiscovery="false" value="true" valueType="boolean" />
|
||||
<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.input.334732222" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.c.linker.input">
|
||||
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)" />
|
||||
<additionalInput kind="additionalinput" paths="$(LIBS)" />
|
||||
</inputType>
|
||||
</tool>
|
||||
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.1601059928" name="GNU ARM Cross C++ Linker" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker">
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections.437759352" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.gcsections" value="true" valueType="boolean" />
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile.1101974459" name="Script files (-T)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.scriptfile" useByScannerDiscovery="false" valueType="stringList">
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//linkscripts//STM32F103RC//link.lds}"" />
|
||||
</option>
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.cref.2007675975" name="Cross reference (-Xlinker --cref)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.cref" useByScannerDiscovery="false" value="true" valueType="boolean" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.usenewlibnano.2105838438" name="Use newlib-nano (--specs=nano.specs)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.usenewlibnano" useByScannerDiscovery="false" value="true" valueType="boolean" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.libs.934137837" name="Libraries (-l)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.libs" useByScannerDiscovery="false" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nostart.2118356996" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nostart" useByScannerDiscovery="false" value="false" valueType="boolean" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nodeflibs.1427884346" name="Do not use default libraries (-nodefaultlibs)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nodeflibs" useByScannerDiscovery="false" value="false" valueType="boolean" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nostdlibs.1433863653" name="No startup or default libs (-nostdlib)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.nostdlibs" useByScannerDiscovery="false" value="false" valueType="boolean" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.printgcsections.1387745410" name="Print removed sections (-Xlinker --print-gc-sections)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.printgcsections" useByScannerDiscovery="false" value="false" valueType="boolean" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.strip.1230158061" name="Omit all symbol information (-s)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.strip" useByScannerDiscovery="false" value="false" valueType="boolean" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.printmap.1307581821" name="Print link map (-Xlinker --print-map)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.printmap" useByScannerDiscovery="false" value="false" valueType="boolean" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.useprintffloat.960778920" name="Use float with nano printf (-u _printf_float)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.useprintffloat" useByScannerDiscovery="false" value="false" valueType="boolean" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.usescanffloat.637205035" name="Use float with nano scanf (-u _scanf_float)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.usescanffloat" useByScannerDiscovery="false" value="false" valueType="boolean" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.usenewlibnosys.1948314201" name="Do not use syscalls (--specs=nosys.specs)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.usenewlibnosys" useByScannerDiscovery="false" value="false" valueType="boolean" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.verbose.273162112" name="Verbose (-v)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.verbose" useByScannerDiscovery="false" value="false" valueType="boolean" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths.1399535143" name="Library search path (-L)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.linker.paths" useByScannerDiscovery="false" />
|
||||
<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input.262373798" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.linker.input">
|
||||
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)" />
|
||||
<additionalInput kind="additionalinput" paths="$(LIBS)" />
|
||||
</inputType>
|
||||
</tool>
|
||||
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver.506412204" name="GNU ARM Cross Archiver" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.archiver" />
|
||||
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash.1461589245" name="GNU ARM Cross Create Flash Image" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createflash">
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.1937707052" name="Output file format (-O)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice" useByScannerDiscovery="false" value="ilg.gnuarmeclipse.managedbuild.cross.option.createflash.choice.binary" valueType="enumerated" />
|
||||
</tool>
|
||||
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting.82359725" name="GNU ARM Cross Create Listing" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.createlisting">
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source.601724476" name="Display source (--source|-S)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.source" value="true" valueType="boolean" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders.692505279" name="Display all headers (--all-headers|-x)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.allheaders" value="true" valueType="boolean" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle.97345172" name="Demangle names (--demangle|-C)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.demangle" value="true" valueType="boolean" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers.1342893377" name="Display line numbers (--line-numbers|-l)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.linenumbers" value="true" valueType="boolean" />
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide.1533725981" name="Wide lines (--wide|-w)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.createlisting.wide" value="true" valueType="boolean" />
|
||||
</tool>
|
||||
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize.1073550295" name="GNU ARM Cross Print Size" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.printsize">
|
||||
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format.946451386" name="Size format" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.printsize.format" useByScannerDiscovery="false" />
|
||||
</tool>
|
||||
<tool id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.1302177015" name="GNU ARM Cross C++ Compiler" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler">
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs.704468062" name="Defined symbols (-D)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.defs" useByScannerDiscovery="true" valueType="definedSymbols">
|
||||
<listOptionValue builtIn="false" value="SOC_FAMILY_STM32" />
|
||||
<listOptionValue builtIn="false" value="SOC_SERIES_STM32F1" />
|
||||
<listOptionValue builtIn="false" value="USE_HAL_DRIVER" />
|
||||
<listOptionValue builtIn="false" value="STM32F103xE" />
|
||||
</option>
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths.302877723" name="Include paths (-I)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.paths" useByScannerDiscovery="true" valueType="includePath">
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}/drivers}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}/drivers//include}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}/drivers//include//config}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}/libraries//CMSIS//Device//ST//STM32F1xx//Include}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}/libraries//CMSIS//Include}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}/libraries//CMSIS//RTOS//Template}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}/libraries//STM32F1xx_HAL_Driver//Inc}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}/libraries//STM32F1xx_HAL_Driver//Inc//Legacy}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}/.}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}/applications}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//.}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//packages/agile_modbus-v1.1.2/inc}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//packages/agile_modbus-v1.1.2/util}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//packages/rs485-latest/inc}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//packages/ssd1306-latest/inc}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/drivers/include}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/drivers/spi}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/finsh}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/libc/compilers/common/include}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/libc/compilers/newlib}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/libc/posix/io/epoll}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/libc/posix/io/eventfd}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/libc/posix/io/poll}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/components/libc/posix/ipc}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/include}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/libcpu/arm/common}"" />
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc://${ProjName}//rt-thread/libcpu/arm/cortex-m3}"" />
|
||||
</option>
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.files.343249373" name="Include files (-include)" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.cpp.compiler.include.files" useByScannerDiscovery="true" valueType="includeFiles">
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/rtconfig_preinc.h}"" />
|
||||
</option>
|
||||
<inputType id="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input.45918001" superClass="ilg.gnuarmeclipse.managedbuild.cross.tool.cpp.compiler.input" />
|
||||
</tool>
|
||||
</toolChain>
|
||||
</folderInfo>
|
||||
<sourceEntries>
|
||||
<entry excluding="//packages/agile_modbus-v1.1.2/examples|//rt-thread/components/dfs|//rt-thread/components/drivers/audio|//rt-thread/components/drivers/can|//rt-thread/components/drivers/core/bus.c|//rt-thread/components/drivers/core/dm.c|//rt-thread/components/drivers/core/driver.c|//rt-thread/components/drivers/core/platform.c|//rt-thread/components/drivers/core/platform_ofw.c|//rt-thread/components/drivers/cputime|//rt-thread/components/drivers/fdt|//rt-thread/components/drivers/hwcrypto|//rt-thread/components/drivers/hwtimer|//rt-thread/components/drivers/ktime|//rt-thread/components/drivers/misc/dac.c|//rt-thread/components/drivers/misc/pulse_encoder.c|//rt-thread/components/drivers/misc/rt_drv_pwm.c|//rt-thread/components/drivers/misc/rt_inputcapture.c|//rt-thread/components/drivers/misc/rt_null.c|//rt-thread/components/drivers/misc/rt_random.c|//rt-thread/components/drivers/misc/rt_zero.c|//rt-thread/components/drivers/mtd|//rt-thread/components/drivers/ofw|//rt-thread/components/drivers/phy|//rt-thread/components/drivers/pic|//rt-thread/components/drivers/pm|//rt-thread/components/drivers/rtc|//rt-thread/components/drivers/sdio|//rt-thread/components/drivers/sensor|//rt-thread/components/drivers/serial/serial_v2.c|//rt-thread/components/drivers/spi/enc28j60.c|//rt-thread/components/drivers/spi/qspi_core.c|//rt-thread/components/drivers/spi/sfud|//rt-thread/components/drivers/spi/spi-bit-ops.c|//rt-thread/components/drivers/spi/spi_flash_sfud.c|//rt-thread/components/drivers/spi/spi_msd.c|//rt-thread/components/drivers/spi/spi_wifi_rw009.c|//rt-thread/components/drivers/touch|//rt-thread/components/drivers/tty|//rt-thread/components/drivers/usb|//rt-thread/components/drivers/virtio|//rt-thread/components/drivers/watchdog|//rt-thread/components/drivers/wlan|//rt-thread/components/fal|//rt-thread/components/finsh/msh_file.c|//rt-thread/components/legacy|//rt-thread/components/libc/compilers/armlibc|//rt-thread/components/libc/compilers/dlib|//rt-thread/components/libc/compilers/musl|//rt-thread/components/libc/compilers/picolibc|//rt-thread/components/libc/cplusplus|//rt-thread/components/libc/posix|//rt-thread/components/lwp|//rt-thread/components/mm|//rt-thread/components/net|//rt-thread/components/utilities|//rt-thread/components/vbus|//rt-thread/components/vmm|//rt-thread/libcpu/aarch64|//rt-thread/libcpu/arc|//rt-thread/libcpu/arm/AT91SAM7S|//rt-thread/libcpu/arm/AT91SAM7X|//rt-thread/libcpu/arm/am335x|//rt-thread/libcpu/arm/arm926|//rt-thread/libcpu/arm/armv6|//rt-thread/libcpu/arm/common/divsi3.S|//rt-thread/libcpu/arm/cortex-a|//rt-thread/libcpu/arm/cortex-m0|//rt-thread/libcpu/arm/cortex-m23|//rt-thread/libcpu/arm/cortex-m3/context_iar.S|//rt-thread/libcpu/arm/cortex-m3/context_rvds.S|//rt-thread/libcpu/arm/cortex-m33|//rt-thread/libcpu/arm/cortex-m4|//rt-thread/libcpu/arm/cortex-m7|//rt-thread/libcpu/arm/cortex-r4|//rt-thread/libcpu/arm/dm36x|//rt-thread/libcpu/arm/lpc214x|//rt-thread/libcpu/arm/lpc24xx|//rt-thread/libcpu/arm/realview-a8-vmm|//rt-thread/libcpu/arm/s3c24x0|//rt-thread/libcpu/arm/s3c44b0|//rt-thread/libcpu/arm/sep4020|//rt-thread/libcpu/arm/zynqmp-r5|//rt-thread/libcpu/avr32|//rt-thread/libcpu/blackfin|//rt-thread/libcpu/c-sky|//rt-thread/libcpu/ia32|//rt-thread/libcpu/m16c|//rt-thread/libcpu/mips|//rt-thread/libcpu/nios|//rt-thread/libcpu/ppc|//rt-thread/libcpu/risc-v|//rt-thread/libcpu/rx|//rt-thread/libcpu/sim|//rt-thread/libcpu/sparc-v8|//rt-thread/libcpu/ti-dsp|//rt-thread/libcpu/unicore32|//rt-thread/libcpu/v850|//rt-thread/libcpu/xilinx|//rt-thread/src/cpu.c|//rt-thread/src/memheap.c|//rt-thread/src/scheduler_mp.c|//rt-thread/src/signal.c|//rt-thread/src/slab.c|//rt-thread/tools" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="" />
|
||||
</sourceEntries>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings" />
|
||||
</cconfiguration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<project id="qemu-vexpress-a9.ilg.gnuarmeclipse.managedbuild.cross.target.elf.860020518" name="Executable" projectType="ilg.gnuarmeclipse.managedbuild.cross.target.elf" />
|
||||
</storageModule>
|
||||
<storageModule moduleId="scannerConfiguration">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="" />
|
||||
<scannerConfigBuildInfo instanceId="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094;ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094.;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.1570350559;ilg.gnuarmeclipse.managedbuild.cross.tool.c.compiler.input.992053063">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="" />
|
||||
</scannerConfigBuildInfo>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders" />
|
||||
<storageModule moduleId="refreshScope" versionNumber="2">
|
||||
<configuration configurationName="Debug">
|
||||
<resource resourceType="PROJECT" workspacePath="/project" />
|
||||
</configuration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets" />
|
||||
<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings">
|
||||
<doc-comment-owner id="org.eclipse.cdt.ui.doxygen">
|
||||
<path value="" />
|
||||
</doc-comment-owner>
|
||||
</storageModule>
|
||||
</cproject>
|
||||
36
.gitattributes
vendored
Normal file
36
.gitattributes
vendored
Normal file
@ -0,0 +1,36 @@
|
||||
# Sources
|
||||
*.c text diff=c
|
||||
*.cc text diff=cpp
|
||||
*.cxx text diff=cpp
|
||||
*.cpp text diff=cpp
|
||||
*.c++ text diff=cpp
|
||||
*.hpp text diff=cpp
|
||||
*.h text diff=c
|
||||
*.h++ text diff=cpp
|
||||
*.hh text diff=cpp
|
||||
|
||||
# Compiled Object files
|
||||
*.slo binary
|
||||
*.lo binary
|
||||
*.o binary
|
||||
*.obj binary
|
||||
|
||||
# Precompiled Headers
|
||||
*.gch binary
|
||||
*.pch binary
|
||||
|
||||
# Compiled Dynamic libraries
|
||||
*.so binary
|
||||
*.dylib binary
|
||||
*.dll binary
|
||||
|
||||
# Compiled Static libraries
|
||||
*.lai binary
|
||||
*.la binary
|
||||
*.a binary
|
||||
*.lib binary
|
||||
|
||||
# Executables
|
||||
*.exe binary
|
||||
*.out binary
|
||||
*.app binary
|
||||
37
.gitignore
vendored
Normal file
37
.gitignore
vendored
Normal file
@ -0,0 +1,37 @@
|
||||
*.pyc
|
||||
*.map
|
||||
*.dblite
|
||||
*.elf
|
||||
*.bin
|
||||
*.hex
|
||||
*.axf
|
||||
*.pdb
|
||||
*.idb
|
||||
*.ilk
|
||||
*.old
|
||||
build
|
||||
Debug
|
||||
*~
|
||||
*.o
|
||||
*.obj
|
||||
*.out
|
||||
*.bak
|
||||
*.dep
|
||||
*.lib
|
||||
*.i
|
||||
*.d
|
||||
.DS_Stor*
|
||||
.config 3
|
||||
.config 4
|
||||
.config 5
|
||||
*.uimg
|
||||
GPATH
|
||||
GRTAGS
|
||||
GTAGS
|
||||
.vscode
|
||||
JLinkLog.txt
|
||||
JLinkSettings.ini
|
||||
DebugConfig/
|
||||
RTE/
|
||||
settings/
|
||||
*.uvguix*
|
||||
29
.project
Normal file
29
.project
Normal file
@ -0,0 +1,29 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>project</name>
|
||||
<comment />
|
||||
<projects>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<triggers>clean,full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.rt-thread.studio.rttnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
<name>G_CAMS_DATU</name>
|
||||
<linkedResources />
|
||||
</projectDescription>
|
||||
BIN
.settings/.rtmenus
Normal file
BIN
.settings/.rtmenus
Normal file
Binary file not shown.
63
.settings/G_CAMS_DATU.DAPLink.Debug.rttlaunch
Normal file
63
.settings/G_CAMS_DATU.DAPLink.Debug.rttlaunch
Normal file
@ -0,0 +1,63 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.pyocd.launchConfigurationType">
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.adapterName" value="DAP-LINK"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.binFlashStartAddress" value=""/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doContinue" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doDebugInRam" value="false"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doFirstReset" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doGdbServerAllocateConsole" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doSecondReset" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doStartGdbServer" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.enableSemihosting" value="true"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.firstResetType" value="init"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbClientOtherOptions" value=""/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerBusSpeed" value="1000000"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerConnectionAddress" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerDeviceName" value="STM32F103RC"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerEnableSemihosting" value="false"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerExecutable" value="${debugger_install_path}/${daplink_debugger_relative_path}\pyocd.exe"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerFlashMode" value="0"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerGdbPortNumber" value="3333"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerOther" value=""/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerTelnetPortNumber" value="4444"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.otherInitCommands" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.otherRunCommands" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.programMode" value="BIN"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.secondResetType" value="halt"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${studio_install_path}repo\Extract\Chip_Support_Packages\RealThread\STM32F1\0.1.9\debug\svd\STM32F103xx.svd"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU PyOCD"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="false"/>
|
||||
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${rtt_gnu_gcc}/arm-none-eabi-gdb.exe"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
|
||||
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/rtthread.elf"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="G_CAMS_DATU"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
|
||||
<listEntry value="/G_CAMS_DATU"/>
|
||||
</listAttribute>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
|
||||
<listEntry value="4"/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="org.eclipse.debug.core.source_locator_id" value="org.eclipse.cdt.debug.core.sourceLocator"/>
|
||||
<stringAttribute key="org.eclipse.debug.core.source_locator_memento" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <sourceLookupDirector> <sourceContainers duplicates="false"> <container memento="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;default/&gt;&#13;&#10;" typeId="org.eclipse.debug.core.containerType.default"/> </sourceContainers> </sourceLookupDirector> "/>
|
||||
<stringAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_ENCODING" value="GBK"/>
|
||||
<booleanAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_OUTPUT_ON" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="true"/>
|
||||
</launchConfiguration>
|
||||
89
.settings/G_CAMS_DATU.JLink.Debug.rttlaunch
Normal file
89
.settings/G_CAMS_DATU.JLink.Debug.rttlaunch
Normal file
@ -0,0 +1,89 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.jlink.launchConfigurationType">
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.adapterName" value="J-Link"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.binFileStartAddress" value=""/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doConnectToRunning" value="false"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doContinue" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doDebugInRam" value="false"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doFirstReset" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerAllocateConsole" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerAllocateSemihostingConsole" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerInitRegs" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerLocalOnly" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerSilent" value="false"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerVerifyDownload" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doSecondReset" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doStartGdbServer" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableFlashBreakpoints" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihosting" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihostingIoclientGdbClient" value="false"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihostingIoclientTelnet" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSwo" value="true"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.eraseEndAddress" value=""/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.eraseMode" value="0"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.eraseStartAddress" value=""/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.firstResetSpeed" value="1000"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.firstResetType" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.flashDeviceName" value="STM32F103RC"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.flashDownloadHex" value="false"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherOptions" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnection" value="usb"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnectionAddress" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDebugInterface" value="swd"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceEndianness" value="little"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceName" value="STM32F103RC"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceSpeed" value="1000"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerExecutable" value="${debugger_install_path}/${jlink_debugger_relative_path}\JLinkGDBServerCL.exe"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerGdbPortNumber" value="2331"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerLog" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerOther" value="-singlerun"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerRunAfterStopDebug" value="true"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerSwoPortNumber" value="2332"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerTelnetPortNumber" value="2333"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.interfaceSpeed" value="auto"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.jlinkExecutable" value="${debugger_install_path}/${jlink_debugger_relative_path}\JLink.exe"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.otherInitCommands" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.otherRunCommands" value=""/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.runAfterDownload" value="true"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.secondResetType" value=""/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetCpuFreq" value="0"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetPortMask" value="0x1"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetSwoFreq" value="0"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${studio_install_path}\repo\Extract\Chip_Support_Packages\RealThread\STM32F1\0.1.9\debug\svd\STM32F103xx.svd"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU J-Link"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
|
||||
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="2331"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${rtt_gnu_gcc}/arm-none-eabi-gdb.exe"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
|
||||
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/rtthread.elf"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="G_CAMS_DATU"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
|
||||
<listEntry value="/G_CAMS_DATU"/>
|
||||
</listAttribute>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
|
||||
<listEntry value="4"/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="org.eclipse.debug.core.source_locator_id" value="org.eclipse.cdt.debug.core.sourceLocator"/>
|
||||
<stringAttribute key="org.eclipse.debug.core.source_locator_memento" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <sourceLookupDirector> <sourceContainers duplicates="false"> <container memento="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;default/&gt;&#13;&#10;" typeId="org.eclipse.debug.core.containerType.default"/> </sourceContainers> </sourceLookupDirector> "/>
|
||||
<stringAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_ENCODING" value="GBK"/>
|
||||
<booleanAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_OUTPUT_ON" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="true"/>
|
||||
</launchConfiguration>
|
||||
58
.settings/G_CAMS_DATU.Qemu.Debug.rttlaunch
Normal file
58
.settings/G_CAMS_DATU.Qemu.Debug.rttlaunch
Normal file
@ -0,0 +1,58 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.qemu.launchConfigurationType">
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.qemu.doContinue" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.qemu.doDebugInRam" value="false"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.qemu.doFirstReset" value="false"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.qemu.doSecondReset" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.qemu.doStartGdbServer" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.qemu.enableSemihosting" value="true"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.qemu.gdbClientOtherCommands" value="set mem inaccessible-by-default off "/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.qemu.gdbClientOtherOptions" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.qemu.gdbServerBoardModel" value="?"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.qemu.gdbServerCpuQuantity" value="1"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.qemu.gdbServerEnableNetwork" value="false"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.qemu.gdbServerExecutable" value="${debugger_install_path}/${qemu_debugger_relative_path}\qemu-system-arm.exe"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.qemu.gdbServerExtraQemuCmd" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.qemu.gdbServerSdcardMemory" value="64.0"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.qemu.gdbServerSerialPort" value="COM1"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.qemu.gdbServerStartup" value="${studio_install_path}/repo/Extract/Debugger_Support_Packages/RealThread/QEMU/4.2.0.4/qemu-system-arm.exe -M ? -sd sd.bin -nographic -S -s"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.qemu.gdbServerTapName" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.qemu.otherInitCommands" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.qemu.otherRunCommands" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${studio_install_path}\repo\Extract\Chip_Support_Packages\RealThread\STM32F1\0.1.9\debug\svd\STM32F103xx.svd"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU QEMU"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
|
||||
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="1234"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
|
||||
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/rtthread.elf"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="G_CAMS_DATU"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
|
||||
<listEntry value="/G_CAMS_DATU"/>
|
||||
</listAttribute>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
|
||||
<listEntry value="4"/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="org.eclipse.debug.core.source_locator_id" value="org.eclipse.cdt.debug.core.sourceLocator"/>
|
||||
<stringAttribute key="org.eclipse.debug.core.source_locator_memento" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <sourceLookupDirector> <sourceContainers duplicates="false"> <container memento="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;default/&gt;&#13;&#10;" typeId="org.eclipse.debug.core.containerType.default"/> </sourceContainers> </sourceLookupDirector> "/>
|
||||
<stringAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_ENCODING" value="GBK"/>
|
||||
<booleanAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_OUTPUT_ON" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="true"/>
|
||||
</launchConfiguration>
|
||||
57
.settings/G_CAMS_DATU.STLink.Debug.rttlaunch
Normal file
57
.settings/G_CAMS_DATU.STLink.Debug.rttlaunch
Normal file
@ -0,0 +1,57 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<launchConfiguration type="org.rtthread.studio.debug.gdbjtag.stlink.launchConfigurationType">
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${studio_install_path}\repo\Extract\Chip_Support_Packages\RealThread\STM32F1\0.1.9\debug\svd\STM32F103xx.svd"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.connectMode" value="NORMAL"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.debugInterface" value="SWD"/>
|
||||
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="3"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.flashVerify" value="false"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDeviceId" value="org.eclipse.cdt.debug.gdbjtag.core.jtagdevice.genericDevice"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.otherDownloadOption" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.otherGdbserverOption" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
|
||||
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="61235"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.resetMode" value=" -hardRst"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.resetRun" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${rtt_gnu_gcc}/arm-none-eabi-gdb.exe"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
|
||||
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/rtthread.elf"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="G_CAMS_DATU"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
|
||||
<listEntry value="/G_CAMS_DATU"/>
|
||||
</listAttribute>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
|
||||
<listEntry value="4"/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="org.eclipse.debug.core.source_locator_id" value="org.eclipse.cdt.debug.core.sourceLocator"/>
|
||||
<stringAttribute key="org.eclipse.debug.core.source_locator_memento" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <sourceLookupDirector> <sourceContainers duplicates="false"> <container memento="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;default/&gt;&#13;&#10;" typeId="org.eclipse.debug.core.containerType.default"/> </sourceContainers> </sourceLookupDirector> "/>
|
||||
<stringAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_ENCODING" value="GBK"/>
|
||||
<booleanAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_OUTPUT_ON" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.debug.ui.ATTR_LAUNCH_IN_BACKGROUND" value="true"/>
|
||||
<stringAttribute key="org.rtthread.studio.debug.gdbjtag.stlink.adapterName" value="ST-LINK"/>
|
||||
<booleanAttribute key="org.rtthread.studio.debug.gdbjtag.stlink.doContinue" value="true"/>
|
||||
<stringAttribute key="org.rtthread.studio.debug.gdbjtag.stlink.gdbServerDeviceName" value="STM32F103RC"/>
|
||||
<stringAttribute key="org.rtthread.studio.debug.gdbjtag.stlink.gdbServerExecutable" value="${debugger_install_path}/${stlink_debugger_relative_path}/ST-LINK_gdbserver.exe"/>
|
||||
<stringAttribute key="org.rtthread.studio.debug.gdbjtag.stlink.stlinkGdbServer" value="${debugger_install_path}/${stlink_debugger_relative_path}/tools/bin/STM32_Programmer_CLI.exe"/>
|
||||
<booleanAttribute key="org.rtthread.studio.debug.gdbjtag.stlink.useRemoteTarget" value="true"/>
|
||||
</launchConfiguration>
|
||||
2
.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs
Normal file
2
.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs
Normal file
@ -0,0 +1,2 @@
|
||||
eclipse.preferences.version=1
|
||||
toolchain.path.1287942917=${toolchain_install_path}/ARM/GNU_Tools_for_ARM_Embedded_Processors/5.4.1/bin
|
||||
14
.settings/language.settings.xml
Normal file
14
.settings/language.settings.xml
Normal file
@ -0,0 +1,14 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<project>
|
||||
<configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094" name="Debug">
|
||||
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
|
||||
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
|
||||
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-1574790197502911086" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||
</provider>
|
||||
</extension>
|
||||
</configuration>
|
||||
</project>
|
||||
2
.settings/org.eclipse.core.resources.prefs
Normal file
2
.settings/org.eclipse.core.resources.prefs
Normal file
@ -0,0 +1,2 @@
|
||||
eclipse.preferences.version=1
|
||||
encoding/<project>=UTF-8
|
||||
3
.settings/org.eclipse.core.runtime.prefs
Normal file
3
.settings/org.eclipse.core.runtime.prefs
Normal file
@ -0,0 +1,3 @@
|
||||
content-types/enabled=true
|
||||
content-types/org.eclipse.cdt.core.asmSource/file-extensions=s
|
||||
eclipse.preferences.version=1
|
||||
22
.settings/projcfg.ini
Normal file
22
.settings/projcfg.ini
Normal file
@ -0,0 +1,22 @@
|
||||
#RT-Thread Studio Project Configuration
|
||||
#Tue May 07 19:17:35 CST 2024
|
||||
project_type=rtt
|
||||
chip_name=STM32F103RC
|
||||
cpu_name=None
|
||||
target_freq=72
|
||||
clock_source=hsi
|
||||
dvendor_name=STMicroelectronics
|
||||
rx_pin_name=PA10
|
||||
rtt_path=repo/Extract/RT-Thread_Source_Code/RT-Thread/5.0.2
|
||||
source_freq=0
|
||||
csp_path=repo/Extract/Chip_Support_Packages/RealThread/STM32F1/0.1.9
|
||||
sub_series_name=STM32F103
|
||||
selected_rtt_version=5.0.2
|
||||
cfg_version=v3.0
|
||||
tool_chain=gcc
|
||||
uart_name=uart1
|
||||
tx_pin_name=PA9
|
||||
rtt_nano_path=
|
||||
output_project_path=C\:\\UserL\\work\\rttworkspace
|
||||
hardware_adapter=ST-LINK
|
||||
project_name=G_CAMS_DATU
|
||||
27
Kconfig
Normal file
27
Kconfig
Normal file
@ -0,0 +1,27 @@
|
||||
mainmenu "RT-Thread Configuration"
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
option env="BSP_ROOT"
|
||||
default "."
|
||||
|
||||
config RTT_DIR
|
||||
string
|
||||
option env="RTT_ROOT"
|
||||
default "rt-thread"
|
||||
|
||||
config PKGS_DIR
|
||||
string
|
||||
option env="PKGS_ROOT"
|
||||
default "packages"
|
||||
|
||||
source "$RTT_DIR/Kconfig"
|
||||
source "$PKGS_DIR/Kconfig"
|
||||
source "$PKGS_DIR/packages/misc/samples/Kconfig"
|
||||
|
||||
config RT_STUDIO_BUILT_IN
|
||||
bool
|
||||
select ARCH_ARM_CORTEX_M3
|
||||
select RT_USING_COMPONENTS_INIT
|
||||
select RT_USING_USER_MAIN
|
||||
default y
|
||||
125
README.md
Normal file
125
README.md
Normal file
@ -0,0 +1,125 @@
|
||||
## CAMS DATU ：CAMS计算机辅助缝纫管理系统采集模块
|
||||
|
||||
#### 说明
|
||||
|
||||
- 待完成
|
||||
|
||||
RS232协议（未指定）
|
||||
|
||||
发送数据信息（未指定格式）
|
||||
|
||||
- 已完成
|
||||
|
||||
1.IO输入输出
|
||||
|
||||
2.flash读写，保存数据
|
||||
|
||||
3.USB串口动态配置信息（MQTT、Modbus等）
|
||||
|
||||
4.屏幕多级菜单显示IO数据、配置信息等
|
||||
|
||||
5.Modbus/485读写
|
||||
|
||||
7.ADC采集0-10V、3.3V、4-20ma（可配合硬件修改）
|
||||
|
||||
8.4G联网、MQTT连接
|
||||
|
||||
9.命令输出指定log用于调试
|
||||
|
||||
#### 开发环境
|
||||
|
||||
RT-Thread 软件打开 [点击下载](https://www.rt-thread.org/download.html#download-rt-thread-studio "点击下载")，版本: 2.2.7、C 语言
|
||||
|
||||
安装完成，**SDK下载RT-Thread 5.0.2与STM32F1固件库**，导入工程即可
|
||||
|
||||
---
|
||||
|
||||
#### 使用说明
|
||||
|
||||
| 目录 | 说明 |
|
||||
| ----------- | ---------------- |
|
||||
| driver | RT-Thread 的驱动 |
|
||||
| libraries | rtt 内核 |
|
||||
| linkscripts | 空间链接脚本 |
|
||||
| packages | 第三方功能包 |
|
||||
| rt-thread | rtt 内核 |
|
||||
|
||||
主要关心 application 目录下文件夹功能：
|
||||
|
||||
| 目录名 | 作用 |
|
||||
| ------ | -------------------------------- |
|
||||
| config | 用户配置功能 |
|
||||
| fram | 读写flash，用以保存读取配置 |
|
||||
| IO | 端口电平等 |
|
||||
| OLED | 屏幕 |
|
||||
| modbus | modbus 功能 |
|
||||
| thread | 线程管理 |
|
||||
| LTE | 网络配置 |
|
||||
| ADC | ADC读值转换0-10V、3.3V、4-20ma等 |
|
||||
| AIR820 | 4G模组与MQTT代码 |
|
||||
| RS232 | 暂未定协议 |
|
||||
|
||||
由main函数为起始阅读点，读取配置后做初始化启动线程开始工作
|
||||
|
||||
main.c-> 读配置 ->thread.c -> IO
|
||||
-> fram
|
||||
-> modbus
|
||||
-> .......
|
||||
|
||||
|
||||
---
|
||||
|
||||
|
||||
|
||||
#### 空间与引脚分配
|
||||
|
||||
- MB85RS64储存分布说明，8192 字节
|
||||
|
||||
| 字符 | 占用 |
|
||||
| ------------ | ---- |
|
||||
| 预留标志位 | 8 |
|
||||
| MQTT | 80 |
|
||||
| modbus | 9 |
|
||||
| ADC | 4 |
|
||||
| 下一写入位置 | 101 |
|
||||
| 运行数据 | ... |
|
||||
|
||||
-
|
||||
- 引脚分配表
|
||||
- 输入输出
|
||||
|
||||
| 引脚名称 | 功能 | | 引脚名称 | 功能 |
|
||||
| -------- | ------ | ---- | -------- | ------- |
|
||||
| PC2 | INPUT1 | | PB12 | OUTPUT1 |
|
||||
| PC3 | INPUT2 | | PB13 | OUTPUT2 |
|
||||
| PC4 | INPUT3 | | PB14 | OUTPUT3 |
|
||||
| PA5 | INPUT4 | | PB15 | OUTPUT4 |
|
||||
| PA6 | INPUT5 | | PC6 | OUTPUT5 |
|
||||
| PA7 | INPUT6 | | PC7 | OUTPUT6 |
|
||||
| PA8 | INPUT7 | | PC8 | OUTPUT7 |
|
||||
| PC9 | INPUT8 | | PA11 | OUTPUT8 |
|
||||
|
||||
- 通信接口
|
||||
|
||||
| 引脚 | 功能 | | 引脚 | 功能 |
|
||||
| ---- | ------------- | ---- | ---- | -------------- |
|
||||
| PA9 | UART1_console | | PB3 | SPI_SCK_flash |
|
||||
| PA10 | UART1_console | | PB4 | SPI_MISO_flash |
|
||||
| | | | PB5 | SPI_MOSI_flash |
|
||||
| PC10 | UART4_232_TX | | PA15 | NSS_CS |
|
||||
| PC11 | UART4_232_RX | | | |
|
||||
| PC12 | UART5_232_TX | | PB6 | oled_SCL |
|
||||
| PD2 | UART5_232_RX | | PB7 | oled_SDA |
|
||||
| | | | PB8 | Key_4 |
|
||||
| PA1 | EN_485 | | PB9 | Key_3 |
|
||||
| PA2 | UART2_485_TX | | PC13 | key_2 |
|
||||
| PA3 | UART2_485_RX | | PC14 | key_1 |
|
||||
| | | | | |
|
||||
| PB10 | UART3_TX_4G | | PA0 | ADC1_0 |
|
||||
| PB11 | UART3_RX_4G | | PA4 | ADC2_4 |
|
||||
| PB1 | WAK | | PC0 | ADC3_10 |
|
||||
| PB0 | GPS | | PC1 | ADC3_11 |
|
||||
| PC5 | RST | | | |
|
||||
|
||||
-
|
||||
|
||||
15
SConscript
Normal file
15
SConscript
Normal file
@ -0,0 +1,15 @@
|
||||
# for module compiling
|
||||
import os
|
||||
Import('RTT_ROOT')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
objs = []
|
||||
list = os.listdir(cwd)
|
||||
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(d, 'SConscript'))
|
||||
|
||||
Return('objs')
|
||||
36
SConstruct
Normal file
36
SConstruct
Normal file
@ -0,0 +1,36 @@
|
||||
import os
|
||||
import sys
|
||||
import rtconfig
|
||||
|
||||
RTT_ROOT = os.path.normpath(os.getcwd() + '/rt-thread')
|
||||
|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||
try:
|
||||
from building import *
|
||||
except Exception as e:
|
||||
print("Error message:", e.message)
|
||||
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
|
||||
print(RTT_ROOT)
|
||||
sys.exit(-1)
|
||||
|
||||
TARGET = 'rt-thread.elf'
|
||||
|
||||
DefaultEnvironment(tools=[])
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
|
||||
env.AppendUnique(CPPDEFINES = [])
|
||||
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
213
applications/ADC/adc.c
Normal file
213
applications/ADC/adc.c
Normal file
@ -0,0 +1,213 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-05-11 LJ the first version
|
||||
*/
|
||||
#include <adc.h>
|
||||
|
||||
rt_adc_device_t adc1_dev;
|
||||
rt_adc_device_t adc2_dev;
|
||||
rt_adc_device_t adc3_dev;
|
||||
ADC_Data ADC;
|
||||
|
||||
/**
|
||||
* ADC初始化函数
|
||||
* @return
|
||||
*/
|
||||
rt_uint8_t adc_init()
|
||||
{
|
||||
//查找设备
|
||||
adc1_dev = (rt_adc_device_t) rt_device_find("adc1");
|
||||
if (adc1_dev == RT_NULL)
|
||||
{
|
||||
rt_kprintf("adc sample run failed! can't find %s device!\n", "adc1");
|
||||
return RT_ERROR;
|
||||
}
|
||||
|
||||
adc2_dev = (rt_adc_device_t) rt_device_find("adc2");
|
||||
if (adc2_dev == RT_NULL)
|
||||
{
|
||||
rt_kprintf("adc sample run failed! can't find %s device!\n", "adc3");
|
||||
return RT_ERROR;
|
||||
}
|
||||
|
||||
adc3_dev = (rt_adc_device_t) rt_device_find("adc3");
|
||||
if (adc3_dev == RT_NULL)
|
||||
{
|
||||
rt_kprintf("adc sample run failed! can't find %s device!\n", "adc3");
|
||||
return RT_ERROR;
|
||||
}
|
||||
|
||||
//使能设备
|
||||
rt_adc_enable(adc1_dev, ADC1_CHANNEL_0);
|
||||
rt_adc_enable(adc2_dev, ADC2_CHANNEL_4);
|
||||
rt_adc_enable(adc3_dev, ADC3_CHANNEL_10);
|
||||
rt_adc_enable(adc3_dev, ADC3_CHANNEL_11);
|
||||
|
||||
return RT_EOK;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* ADC读取数据
|
||||
*/
|
||||
void adc_read()
|
||||
{
|
||||
/**
|
||||
* 根据电路推导下面公式
|
||||
* 0-10v vout = vin*2/6.8 + 0.2v
|
||||
* 外部电压 = （vout - 0.2）* 6.8 / 2
|
||||
*
|
||||
* 4-20ma vin = i * 150
|
||||
* 外部电流 = （vout - 0.2）* 6.8 / 2 / 150
|
||||
*/
|
||||
|
||||
ADC.ADC1_0_value = rt_adc_read(adc1_dev, ADC1_CHANNEL_0); //读取采样值
|
||||
ADC.ADC1_0_vol = ADC.ADC1_0_value * REFER_VOLTAGE / CONVERT_BITS; //转换为对应电压值
|
||||
// h_vol = (((float)vol - 0.2) * 6.8 ) / 2 ;
|
||||
ADC.ADC1_0_h_vol = (rt_uint16_t) (((float) ADC.ADC1_0_vol / 100 - 0.2) * 340);
|
||||
|
||||
if (ADC.ADC1_mode == 1) //1:0-10V 2:4-20ma
|
||||
{
|
||||
|
||||
}
|
||||
else if (ADC.ADC1_mode == 2)
|
||||
{
|
||||
ADC.ADC1_0_Current = (rt_uint16_t) (((float) ADC.ADC1_0_vol / 100 - 0.2) / 150 * 340);
|
||||
}
|
||||
|
||||
if (ADC.log)
|
||||
{
|
||||
rt_kprintf("ADC1_CHANNEL_0 value is :%d voltage is :%d.%02d \n", ADC.ADC1_0_value, ADC.ADC1_0_vol / 100, ADC.ADC1_0_vol % 100);
|
||||
rt_kprintf("ADC1_CHANNEL_0 0-10V voltage is :%d.%02d , Current is :%d.%02d\n", ADC.ADC1_0_h_vol / 100, ADC.ADC1_0_h_vol % 100,
|
||||
ADC.ADC1_0_Current / 100, ADC.ADC1_0_Current % 100);
|
||||
}
|
||||
|
||||
ADC.ADC2_4_value = rt_adc_read(adc2_dev, ADC2_CHANNEL_4);
|
||||
ADC.ADC2_4_vol = ADC.ADC2_4_value * REFER_VOLTAGE / CONVERT_BITS;
|
||||
ADC.ADC2_4_h_vol = (rt_uint16_t) (((float) ADC.ADC2_4_vol / 100 - 0.2) * 340);
|
||||
if (ADC.ADC2_mode == 1)
|
||||
{
|
||||
|
||||
}
|
||||
else if (ADC.ADC2_mode == 2)
|
||||
{
|
||||
ADC.ADC2_4_Current = (rt_uint16_t) (((float) ADC.ADC2_4_vol / 100 - 0.2) / 150 * 340);
|
||||
}
|
||||
|
||||
if (ADC.log)
|
||||
{
|
||||
rt_kprintf("ADC2_CHANNEL_4 value is :%d voltage is :%d.%02d \n", ADC.ADC2_4_value, ADC.ADC2_4_vol / 100, ADC.ADC2_4_vol % 100);
|
||||
rt_kprintf("ADC2_CHANNEL_4 0-10V voltage is :%d.%02d , Current is :%d.%02d\n", ADC.ADC2_4_h_vol / 100, ADC.ADC2_4_h_vol % 100,
|
||||
ADC.ADC2_4_Current / 100, ADC.ADC2_4_Current % 100);
|
||||
}
|
||||
|
||||
ADC.ADC3_10_value = rt_adc_read(adc3_dev, ADC3_CHANNEL_10);
|
||||
ADC.ADC3_10_vol = ADC.ADC3_10_value * REFER_VOLTAGE / CONVERT_BITS;
|
||||
if (ADC.log)
|
||||
{
|
||||
rt_kprintf("ADC3_CHANNEL_10 value is :%d voltage is :%d.%02d \n", ADC.ADC3_10_value, ADC.ADC3_10_vol / 100, ADC.ADC3_10_vol % 100);
|
||||
|
||||
}
|
||||
ADC.ADC3_11_value = rt_adc_read(adc3_dev, ADC3_CHANNEL_11);
|
||||
ADC.ADC3_11_vol = ADC.ADC3_11_value * REFER_VOLTAGE / CONVERT_BITS;
|
||||
if (ADC.log)
|
||||
{
|
||||
rt_kprintf("ADC3_CHANNEL_11 value is :%d voltage is :%d.%02d \n", ADC.ADC3_11_value, ADC.ADC3_11_vol / 100, ADC.ADC3_11_vol % 100);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* 获取3V3的值ADC
|
||||
* @return
|
||||
*/
|
||||
rt_uint16_t get_ADC3_10_vol()
|
||||
{
|
||||
return ADC.ADC3_10_vol;
|
||||
}
|
||||
|
||||
rt_uint16_t get_ADC3_11_vol()
|
||||
{
|
||||
return ADC.ADC3_11_vol;
|
||||
}
|
||||
/**
|
||||
* 获取0-10vADC值
|
||||
* @return
|
||||
*/
|
||||
rt_uint16_t get_ADC1_0_h_vol()
|
||||
{
|
||||
return ADC.ADC1_0_h_vol;
|
||||
}
|
||||
|
||||
/**
|
||||
* 获取4-10ma电流值
|
||||
* @return
|
||||
*/
|
||||
rt_uint16_t get_ADC1_0_Current()
|
||||
{
|
||||
return ADC.ADC1_0_Current;
|
||||
}
|
||||
|
||||
/**
|
||||
* 获取0-10vADC值
|
||||
* @return
|
||||
*/
|
||||
rt_uint16_t get_ADC2_4_h_vol()
|
||||
{
|
||||
return ADC.ADC2_4_h_vol;
|
||||
}
|
||||
|
||||
/**
|
||||
* 获取4-10ma电流值
|
||||
* @return
|
||||
*/
|
||||
rt_uint16_t get_ADC2_4_Current()
|
||||
{
|
||||
return ADC.ADC2_4_Current;
|
||||
}
|
||||
|
||||
void set_ADC_log(rt_uint8_t log)
|
||||
{
|
||||
ADC.log = log;
|
||||
}
|
||||
|
||||
/**
|
||||
* 设置ADC1的模式1:0-10V 2:4-20ma
|
||||
* @param mode
|
||||
*/
|
||||
void set_ADC1_mode(rt_uint8_t mode)
|
||||
{
|
||||
ADC.ADC1_mode = mode;
|
||||
}
|
||||
|
||||
/**
|
||||
* 设置ADC2的模式1:0-10V 2:4-20ma
|
||||
* @param mode
|
||||
*/
|
||||
void set_ADC2_mode(rt_uint8_t mode)
|
||||
{
|
||||
ADC.ADC2_mode = mode;
|
||||
}
|
||||
|
||||
/**
|
||||
* 获取ADC1的模式1:0-10V 2:4-20ma
|
||||
* @param mode
|
||||
*/
|
||||
rt_uint8_t get_ADC1_mode()
|
||||
{
|
||||
return ADC.ADC1_mode;
|
||||
}
|
||||
|
||||
/**
|
||||
* 获取ADC2的模式1:0-10V 2:4-20ma
|
||||
* @param mode
|
||||
*/
|
||||
rt_uint8_t get_ADC2_mode()
|
||||
{
|
||||
return ADC.ADC2_mode;
|
||||
}
|
||||
94
applications/ADC/adc.h
Normal file
94
applications/ADC/adc.h
Normal file
@ -0,0 +1,94 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-05-11 LJ the first version
|
||||
*/
|
||||
#ifndef APPLICATIONS_ADC_ADC_H_
|
||||
#define APPLICATIONS_ADC_ADC_H_
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
|
||||
#define ADC1_CHANNEL_0 0 /* ADC 通道 */
|
||||
#define ADC2_CHANNEL_4 4 /* ADC 通道 */
|
||||
#define ADC3_CHANNEL_10 10 /* ADC 通道 */
|
||||
#define ADC3_CHANNEL_11 11 /* ADC 通道 */
|
||||
|
||||
#define REFER_VOLTAGE 330 /* 参考电压 3.3V,数据精度乘以100保留2位小数 */
|
||||
#define CONVERT_BITS (1 << 12) /* 转换位数为12位 */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
rt_uint16_t ADC1_0_vol; // 读取电压值
|
||||
rt_uint16_t ADC2_4_vol; // 读取电压值
|
||||
rt_uint16_t ADC3_10_vol; // 读取电压值
|
||||
rt_uint16_t ADC3_11_vol; // 读取电压值
|
||||
|
||||
rt_uint16_t ADC1_0_value; // 读取电压值
|
||||
rt_uint16_t ADC2_4_value; // 读取电压值
|
||||
rt_uint16_t ADC3_10_value; // 读取电压值
|
||||
rt_uint16_t ADC3_11_value; // 读取电压值
|
||||
|
||||
rt_uint16_t ADC1_0_h_vol; // 0-10V
|
||||
rt_uint16_t ADC2_4_h_vol; //
|
||||
|
||||
rt_uint16_t ADC1_0_Current; // 4-20ma
|
||||
rt_uint16_t ADC2_4_Current; //
|
||||
|
||||
rt_uint8_t log;
|
||||
rt_uint8_t ADC1_mode; //ADC1模式 1:0-10V 2:4-20ma 3:3.3v
|
||||
rt_uint8_t ADC2_mode;//ADC2模式
|
||||
} ADC_Data; // ADC状态
|
||||
|
||||
//ADC初始化函数
|
||||
rt_uint8_t adc_init();
|
||||
|
||||
//ADC读取数据
|
||||
void adc_read();
|
||||
|
||||
//获取3V3的值ADC
|
||||
rt_uint16_t get_ADC3_10_vol();
|
||||
|
||||
//获取3V3的值ADC
|
||||
rt_uint16_t get_ADC3_11_vol();
|
||||
|
||||
/**
|
||||
* 获取0-10vADC值
|
||||
* @return
|
||||
*/
|
||||
rt_uint16_t get_ADC1_0_h_vol();
|
||||
/**
|
||||
* 获取4-10ma电流值
|
||||
* @return
|
||||
*/
|
||||
rt_uint16_t get_ADC1_0_Current();
|
||||
/**
|
||||
* 获取0-10vADC值
|
||||
* @return
|
||||
*/
|
||||
rt_uint16_t get_ADC2_4_h_vol();
|
||||
/**
|
||||
* 获取4-10ma电流值
|
||||
* @return
|
||||
*/
|
||||
rt_uint16_t get_ADC2_4_Current();
|
||||
|
||||
//ADC log 功能开启
|
||||
void set_ADC_log(rt_uint8_t log);
|
||||
|
||||
//设置ADC1的模式1:0-10V 2:4-20ma
|
||||
void set_ADC1_mode(rt_uint8_t mode);
|
||||
|
||||
//设置ADC2的模式1:0-10V 2:4-20ma
|
||||
void set_ADC2_mode(rt_uint8_t mode);
|
||||
|
||||
//获取ADC1的模式1:0-10V 2:4-20ma
|
||||
rt_uint8_t get_ADC1_mode();
|
||||
//获取ADC2的模式1:0-10V 2:4-20ma
|
||||
rt_uint8_t get_ADC2_mode();
|
||||
|
||||
#endif /* APPLICATIONS_ADC_ADC_H_ */
|
||||
397
applications/AIR820/LTE.c
Normal file
397
applications/AIR820/LTE.c
Normal file
@ -0,0 +1,397 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-05-06 lijian the first version
|
||||
*/
|
||||
#include <LTE.h>
|
||||
|
||||
#define AT_UART_NAME "uart3"
|
||||
|
||||
LTE_t LTE;
|
||||
|
||||
static rt_device_t AT_serial; /* 串口设备句柄 */
|
||||
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; /* 初始化配置参数 */
|
||||
|
||||
/* 串口接收消息结构*/
|
||||
struct rx_msg
|
||||
{
|
||||
rt_device_t dev;
|
||||
rt_size_t size;
|
||||
};
|
||||
|
||||
/* 消息队列控制块 */
|
||||
static struct rt_messagequeue rx_mq;
|
||||
|
||||
rt_uint8_t rx_length;
|
||||
rt_uint8_t check_flag;
|
||||
rt_err_t result;
|
||||
static char line_buffer[60];
|
||||
|
||||
void set_check_flag(rt_uint8_t flag){
|
||||
check_flag = flag;
|
||||
}
|
||||
|
||||
//AT指令发送
|
||||
void AT_send(const char * cmd)
|
||||
{
|
||||
rt_device_write(AT_serial, 0, cmd, rt_strlen(cmd));
|
||||
}
|
||||
|
||||
/* 接收数据回调函数 */
|
||||
static rt_err_t uart_callback(rt_device_t dev, rt_size_t size)
|
||||
{
|
||||
struct rx_msg msg;
|
||||
rt_err_t result;
|
||||
msg.dev = dev;
|
||||
msg.size = size;
|
||||
|
||||
//rt_kprintf("in uart_callback\n");
|
||||
|
||||
result = rt_mq_send(&rx_mq, &msg, sizeof(msg));
|
||||
if (result == -RT_EFULL)
|
||||
{
|
||||
/* 消息队列满 */
|
||||
rt_kprintf("message queue full！\n");
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
|
||||
//接收数据线程
|
||||
static void rx_serial_thread_entry(void *parameter)
|
||||
{
|
||||
struct rx_msg msg;
|
||||
static char rx_buffer[RT_SERIAL_RB_BUFSZ + 1];
|
||||
rt_uint8_t line_pos = 0;
|
||||
|
||||
while (1)
|
||||
{
|
||||
rt_memset(&msg, 0, sizeof(msg));
|
||||
/* 从消息队列中读取消息*/
|
||||
result = rt_mq_recv(&rx_mq, &msg, sizeof(msg), RT_WAITING_FOREVER);
|
||||
if (result > 0)
|
||||
{
|
||||
|
||||
// rx_length = rt_device_read(msg.dev, 0, rx_buffer, msg.size);
|
||||
// rx_buffer[rx_length] = '\0';
|
||||
// /* 打印数据 */
|
||||
// rt_kprintf("%s\n", rx_buffer);
|
||||
|
||||
rx_length = rt_device_read(msg.dev, 0, rx_buffer, msg.size);
|
||||
|
||||
for (int i = 0; i < rx_length; i++)
|
||||
{
|
||||
// 如果收到了换行符或回车符，就认为是一行的结束
|
||||
if (rx_buffer[i] == '\n' || rx_buffer[i] == '\r')
|
||||
{
|
||||
line_buffer[line_pos] = '\0'; // 添加字符串结束符
|
||||
if (line_pos > 0) // 如果这一行至少有一个字符
|
||||
{
|
||||
|
||||
if (check_flag == 1) //1检测MQTT
|
||||
{
|
||||
//+MQTTSTATU :0 离线 1 已经登陆认证过 2 还没认证，需要发送 MCONNECT
|
||||
char * ch_pos = rt_strstr(line_buffer, "+MQTTSTATU :");
|
||||
// rt_kprintf("ch_pos c: %s\n", ch_pos);
|
||||
if (ch_pos != RT_NULL)
|
||||
{
|
||||
ch_pos = ch_pos + 12;
|
||||
set_MQTT_STATUS((rt_uint8_t) *ch_pos - '0');
|
||||
//break;
|
||||
}
|
||||
}
|
||||
|
||||
else if (check_flag == 2) //2检测LTE
|
||||
{
|
||||
|
||||
//判断两个.为有IP，即联网成功
|
||||
char *ch_pos2 = strchr(line_buffer, '.');
|
||||
|
||||
if (ch_pos2 != NULL) {
|
||||
// 计算点字符的位置
|
||||
rt_uint8_t position = ch_pos2 - line_buffer; // 指针减法得到索引
|
||||
|
||||
if (line_buffer[position+2] == '.' || line_buffer[position+3] == '.' || line_buffer[position+4] == '.') {
|
||||
set_LTE_Status(1);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
//+CME ERROR:联网失败
|
||||
ch_pos2 = rt_strstr(line_buffer, "+CME ERROR:");
|
||||
if (ch_pos2 != RT_NULL)
|
||||
{
|
||||
set_LTE_Status(0);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (LTE.log) {
|
||||
rt_kprintf("Received line: %s\n", line_buffer);
|
||||
}
|
||||
|
||||
// rt_kprintf("Received line: %s , %d\n", line_buffer, line_pos);
|
||||
}
|
||||
line_pos = 0; // 重置行缓冲区位置
|
||||
}
|
||||
else if (line_pos < sizeof(line_buffer) - 1)
|
||||
{
|
||||
// 否则，将字符添加到行缓冲区
|
||||
line_buffer[line_pos++] = rx_buffer[i];
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//AT串口初始化
|
||||
rt_uint8_t AT_device_init()
|
||||
{
|
||||
|
||||
// rt_pin_mode(WAK, PIN_MODE_OUTPUT);
|
||||
// // 默认为高电平
|
||||
// rt_pin_write(WAK, PIN_HIGH);
|
||||
// rt_pin_mode(GPS, PIN_MODE_OUTPUT);
|
||||
// // 默认为高电平
|
||||
// rt_pin_write(GPS, PIN_LOW);
|
||||
rt_pin_mode(RST, PIN_MODE_OUTPUT);
|
||||
// 默认为高电平
|
||||
rt_pin_write(RST, PIN_HIGH);
|
||||
rt_thread_mdelay(200);
|
||||
rt_pin_write(RST, PIN_LOW);
|
||||
|
||||
rt_err_t ret = RT_EOK;
|
||||
|
||||
static char msg_pool[256];
|
||||
|
||||
// char str[] = "AT\r\n";
|
||||
|
||||
AT_serial = rt_device_find(AT_UART_NAME);
|
||||
if (!AT_serial)
|
||||
{
|
||||
rt_kprintf("find %s failed!\n", AT_UART_NAME);
|
||||
return RT_ERROR;
|
||||
}
|
||||
|
||||
config.baud_rate = BAUD_RATE_115200; //修改波特率为 115200
|
||||
config.data_bits = DATA_BITS_8; //数据位 8
|
||||
config.stop_bits = STOP_BITS_1; //停止位 1
|
||||
config.bufsz = 128; //修改缓冲区 buff size 为 128
|
||||
config.parity = PARITY_NONE; //无奇偶校验位
|
||||
|
||||
/* 初始化消息队列 */
|
||||
rt_mq_init(&rx_mq, "rx_mq", msg_pool, /* 存放消息的缓冲区 */
|
||||
sizeof(struct rx_msg), /* 一条消息的最大长度 */
|
||||
sizeof(msg_pool), /* 存放消息的缓冲区大小 */
|
||||
RT_IPC_FLAG_FIFO); /* 如果有多个线程等待，按照先来先得到的方法分配消息 */
|
||||
|
||||
/* 串口设备控制参数 */
|
||||
rt_device_control(AT_serial, RT_DEVICE_CTRL_CONFIG, &config);
|
||||
|
||||
/* 打开串口设备。 DMA 接收及轮询发送模式打开串口设备 RT_DEVICE_FLAG_DMA_RX */
|
||||
ret = rt_device_open(AT_serial, RT_DEVICE_FLAG_DMA_RX);
|
||||
if (ret != RT_EOK)
|
||||
{
|
||||
rt_kprintf("open AT_serial fail!\n");
|
||||
return RT_ERROR;
|
||||
}
|
||||
|
||||
// AT_send("ATE0\r\n");
|
||||
|
||||
/* 设置接收回调函数 */
|
||||
rt_device_set_rx_indicate(AT_serial, uart_callback);
|
||||
/* 发送字符串 */
|
||||
|
||||
/* 创建 serial 线程 */
|
||||
rt_thread_t rx_thread = rt_thread_create("rx_serial", rx_serial_thread_entry, RT_NULL, 1024, 25, 10);
|
||||
/* 创建成功则启动线程 */
|
||||
if (rx_thread != RT_NULL)
|
||||
{
|
||||
rt_thread_startup(rx_thread);
|
||||
}
|
||||
else
|
||||
{
|
||||
ret = RT_ERROR;
|
||||
}
|
||||
|
||||
rt_kprintf("open AT_serial ok!\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
//LTE初始化
|
||||
rt_uint8_t LTE_init()
|
||||
{
|
||||
AT_send("AT\r\n");
|
||||
AT_send("ATE0\r\n");
|
||||
rt_thread_mdelay(1000);
|
||||
// AT_send("AT+CGMI\r\n"); //模块厂商信息
|
||||
// rt_thread_mdelay(500);
|
||||
//
|
||||
// AT_send("AT+CPIN?\r\n"); //查询卡是否插好
|
||||
// rt_thread_mdelay(500);
|
||||
//
|
||||
// AT_send("AT+CSQ\r\n"); //信号质量
|
||||
// rt_thread_mdelay(500);
|
||||
//
|
||||
// AT_send("AT+CREG?\r\n"); //网络注册状态
|
||||
// rt_thread_mdelay(500);
|
||||
//
|
||||
// AT_send("AT+CGATT?\r\n"); //附着GPRS
|
||||
// rt_thread_mdelay(500);
|
||||
|
||||
AT_send("AT+CSTT=\"\",\"\",\"\"\r\n"); //自动APN
|
||||
rt_thread_mdelay(500);
|
||||
|
||||
// AT_send("AT+CSTT?\r\n");
|
||||
// rt_thread_mdelay(500);
|
||||
|
||||
AT_send("AT+CIICR\r\n"); //激活移动场景
|
||||
rt_thread_mdelay(500);
|
||||
|
||||
AT_send("AT+CIFSR\r\n"); //查询IP
|
||||
rt_thread_mdelay(500);
|
||||
|
||||
// AT_send("ATI\r\n");
|
||||
// rt_thread_mdelay(500);
|
||||
|
||||
//AT_send("ATD15612696324;\r\n");
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
//获取LTE状态
|
||||
rt_uint8_t get_LTE_status_flag()
|
||||
{
|
||||
set_check_flag(2);
|
||||
rt_uint8_t i = 0;
|
||||
AT_send("AT+CIFSR\r\n");
|
||||
while (!get_LTE_Status())
|
||||
{
|
||||
rt_thread_mdelay(200);
|
||||
if (i > 3)
|
||||
{
|
||||
break;
|
||||
}
|
||||
i++;
|
||||
}
|
||||
|
||||
if (LTE.log) {
|
||||
rt_kprintf("LTE status:%d\n" , get_LTE_Status());
|
||||
}
|
||||
|
||||
|
||||
return get_LTE_Status();
|
||||
}
|
||||
|
||||
void set_LTE_log(rt_uint8_t log){
|
||||
LTE.log = log;
|
||||
}
|
||||
|
||||
//LTE重新初始化
|
||||
void LTE_Re_Init()
|
||||
{
|
||||
rt_pin_write(RST, PIN_HIGH);
|
||||
rt_thread_mdelay(500);
|
||||
rt_pin_write(RST, PIN_LOW);
|
||||
|
||||
AT_send("AT+CSTT=\"\",\"\",\"\"\r\n"); //自动APN
|
||||
rt_thread_mdelay(500);
|
||||
|
||||
// AT_send("AT+CSTT?\r\n");
|
||||
// rt_thread_mdelay(500);
|
||||
|
||||
AT_send("AT+CIICR\r\n"); //激活移动场景
|
||||
rt_thread_mdelay(500);
|
||||
|
||||
AT_send("AT+CIFSR\r\n"); //查询IP
|
||||
}
|
||||
|
||||
//检测MQTT与LTE联网状态
|
||||
void check_LTE_MQTT(){
|
||||
if (LTE.toggle)
|
||||
{
|
||||
if (get_LTE_status_flag() != 1)
|
||||
{
|
||||
LTE.LTE_re++;
|
||||
}
|
||||
else
|
||||
{
|
||||
LTE.LTE_re = 0;
|
||||
}
|
||||
|
||||
if (LTE.LTE_re == 3)
|
||||
{
|
||||
|
||||
LTE_Re_Init();
|
||||
}
|
||||
|
||||
|
||||
LTE.toggle = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
||||
if (get_MQTT_Status_flag() != 1)
|
||||
{
|
||||
LTE.MQTT_re++;
|
||||
}
|
||||
else
|
||||
{
|
||||
LTE.MQTT_re = 0;
|
||||
}
|
||||
|
||||
if (LTE.LTE_re == 0 && LTE.MQTT_re == 3)
|
||||
{
|
||||
MQTT_RE_init();
|
||||
}
|
||||
|
||||
LTE.toggle = 1;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置/获取LTE使用键值
|
||||
* @param rt_uint8_t key 要设置的Key值
|
||||
* @return rt_uint8_t 返回当前的Key值
|
||||
*/
|
||||
void set_LTE_Key(rt_uint8_t key)
|
||||
{
|
||||
LTE.Key = key;
|
||||
}
|
||||
|
||||
rt_uint8_t get_LTE_Key()
|
||||
{
|
||||
return LTE.Key;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置/获取LTE状态键值
|
||||
* @param rt_uint8_t key 要设置的Key值
|
||||
* @return rt_uint8_t 返回当前的Key值
|
||||
*/
|
||||
void set_LTE_Status(rt_uint8_t Status_t)
|
||||
{
|
||||
LTE.Status = Status_t;
|
||||
}
|
||||
|
||||
rt_uint8_t get_LTE_Status()
|
||||
{
|
||||
return LTE.Status;
|
||||
}
|
||||
|
||||
rt_uint8_t get_LTE_re()
|
||||
{
|
||||
return LTE.LTE_re;
|
||||
}
|
||||
|
||||
rt_uint8_t get_L_MQTT_re()
|
||||
{
|
||||
return LTE.MQTT_re;
|
||||
}
|
||||
61
applications/AIR820/LTE.h
Normal file
61
applications/AIR820/LTE.h
Normal file
@ -0,0 +1,61 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-05-06 lijian the first version
|
||||
*/
|
||||
#ifndef APPLICATIONS_AIR820_LTE_H_
|
||||
#define APPLICATIONS_AIR820_LTE_H_
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <drv_common.h>
|
||||
#include <rtdevice.h>
|
||||
#include <mqtt.h>
|
||||
#include <gui.h>
|
||||
|
||||
#define GPS GET_PIN(B, 0)
|
||||
#define WAK GET_PIN(B, 1)
|
||||
#define RST GET_PIN(C, 5)
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
rt_uint8_t LTE; // 4G
|
||||
rt_uint8_t Status; //已连接1 未连接0 以有无IP为根据
|
||||
rt_uint8_t toggle;
|
||||
rt_uint8_t LTE_re;
|
||||
rt_uint8_t MQTT_re;
|
||||
rt_uint8_t Key; //使用状态键值 1使用LTE 0不使用LTE
|
||||
rt_uint8_t log;
|
||||
} LTE_t; // 4G配置与状态
|
||||
|
||||
//AT指令发送
|
||||
void AT_send(const char * cmd);
|
||||
|
||||
//AT串口初始化
|
||||
rt_uint8_t AT_device_init();
|
||||
|
||||
//LTE初始化
|
||||
rt_uint8_t LTE_init();
|
||||
|
||||
//log
|
||||
void set_LTE_log(rt_uint8_t log);
|
||||
|
||||
//设置/获取LTE状态键值
|
||||
void set_LTE_Status(rt_uint8_t Status_t);
|
||||
rt_uint8_t get_LTE_Status();
|
||||
|
||||
//检查标志位 1 MQTT 2 LTE
|
||||
void set_check_flag(rt_uint8_t flag);
|
||||
|
||||
//获取LTE状态
|
||||
rt_uint8_t get_LTE_status_flag();
|
||||
|
||||
//检测MQTT与LTE联网状态
|
||||
void check_LTE_MQTT();
|
||||
rt_uint8_t get_LTE_re();
|
||||
rt_uint8_t get_L_MQTT_re();
|
||||
#endif /* APPLICATIONS_AIR820_LTE_H_ */
|
||||
336
applications/AIR820/MQTT.c
Normal file
336
applications/AIR820/MQTT.c
Normal file
@ -0,0 +1,336 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-04-18 lijian the first version
|
||||
*/
|
||||
#include <MQTT.h>
|
||||
|
||||
MQTT_t MQTT;
|
||||
|
||||
char buffer_sn[40] ;
|
||||
char buffer_sn1[40] ;
|
||||
char buffer_sn2[40] ;
|
||||
|
||||
/**
|
||||
* mqtt初始化
|
||||
* @return
|
||||
*/
|
||||
rt_uint8_t MQTT_init()
|
||||
{
|
||||
char buf[64];
|
||||
|
||||
rt_sprintf(buf, "AT+MCONFIG=\"%s\",\"%s\",\"%s\"\r\n", MQTT.MQTT_CLI_ID, MQTT.MQTT_USERNAME, MQTT.MQTT_PWD);
|
||||
//AT_send("AT+MCONFIG=\"RP121380\",\"RP121380\",\"\"\r\n"); //MQTT <client ID> , <username> , <password>
|
||||
AT_send(buf);
|
||||
rt_thread_mdelay(300);
|
||||
|
||||
rt_sprintf(buf, "AT+MIPSTART=\"%s\",\"%s\"\r\n", MQTT.MQTT_ADDR, MQTT.MQTT_PORT);
|
||||
// AT_send("AT+MIPSTART=\"8.130.165.100\",8082\r\n");//MQTT <ip addr> , <port>
|
||||
AT_send(buf);
|
||||
rt_thread_mdelay(300);
|
||||
|
||||
AT_send("AT+MCONNECT=0,60000\r\n");//MQTT <clean_session> , <keepalive>
|
||||
|
||||
rt_thread_mdelay(3000);
|
||||
|
||||
|
||||
/*
|
||||
* 最大 4100 个字节。字符串类型，须用双引号括住。
|
||||
注:消息中内嵌的双引号请用\22 表达；控制字符回车
|
||||
\r(0x0D)请用\0D 表达；控制字符换行\n（0x0A）
|
||||
请用\0A 表达；控制字符反斜杠\（0x5C）请用\5C
|
||||
表达
|
||||
如果是 MCU 发消息，需要用\\22，\\0D，
|
||||
\\0A，\\5C 来表达，即\需要转义成\\
|
||||
*
|
||||
*/
|
||||
//AT_send("AT+MPUB=\"v1/devices/me/telemetry\",0,0,\"{\"IN0\":1}\"\r\n");
|
||||
// rt_thread_mdelay(1000);
|
||||
// AT_send("AT+MPUB=\"v1/devices/me/telemetry\",0,0,\"{\\22IN0\\22:1}\"\r\n");
|
||||
|
||||
// get_MQTT_flag();
|
||||
|
||||
return RT_EOK;
|
||||
|
||||
}
|
||||
|
||||
//MQTT发送函数
|
||||
void MQTT_PUB()
|
||||
{
|
||||
//char buffer[32];
|
||||
// rt_sprintf(buffer, "{\\\"IN0:1\\\":%d;\\\"ZQ_ON\\\":%d;\\\"YD_ON\\\":%d;\\\"SUM\\\":%ld}", MQTT.MQTT_ADDR);
|
||||
// AT_send("AT+MQTTPUB=%s,0,0,%s\r\n", MQTT_PUBTOPIC, "");
|
||||
AT_send("AT+MPUB=\"v1/devices/me/telemetry\",0,0,\"{\\22IN0\\22:1}\"\r\n");
|
||||
}
|
||||
|
||||
/**
|
||||
* 心跳函数
|
||||
*/
|
||||
void MQTT_Keep_Alive()
|
||||
{
|
||||
AT_send("AT+MPUB=\"v1/devices/me/telemetry\",0,0,\"{\\22IN0\\22:1}\"\r\n");
|
||||
}
|
||||
|
||||
/**
|
||||
* 获取MQTT连接状态
|
||||
* @return
|
||||
*/
|
||||
rt_uint8_t get_MQTT_Status_flag()
|
||||
{
|
||||
set_check_flag(1);
|
||||
rt_uint8_t i = 0;
|
||||
//MQTTSTATU :<state> 0 离线 1 已经登陆认证过 2 还没认证，需要发送 MCONNECT
|
||||
AT_send("AT+MQTTSTATU\r\n");
|
||||
while (!get_MQTT_STATUS())
|
||||
{
|
||||
rt_thread_mdelay(100);
|
||||
if (i > 3)
|
||||
{
|
||||
break;
|
||||
}
|
||||
i++;
|
||||
}
|
||||
|
||||
if (MQTT.log) {
|
||||
rt_kprintf("MQTT status:%d\n", get_MQTT_STATUS());
|
||||
}
|
||||
|
||||
return get_MQTT_STATUS();
|
||||
}
|
||||
|
||||
void set_mqtt_log(uint8_t log){
|
||||
MQTT.log = log;
|
||||
}
|
||||
|
||||
/**
|
||||
* MQTT重连
|
||||
* @return
|
||||
*/
|
||||
void MQTT_RE_init()
|
||||
{
|
||||
AT_send("AT+MDISCONNECT\r\n");
|
||||
rt_thread_mdelay(2000);
|
||||
AT_send("AT+MCONNECT=0,60000\r\n");
|
||||
}
|
||||
|
||||
/**
|
||||
* 发送电平
|
||||
* @param key
|
||||
*/
|
||||
void MQTT_Send_Key(rt_uint16_t key)
|
||||
{
|
||||
|
||||
rt_sprintf(buffer_sn1 , "AT+MQTTPUB=\"v1/devices/me/telemetry\",0,0,\"{\"IN\":%04x}\"\r\n" , key);
|
||||
|
||||
AT_send(buffer_sn1);
|
||||
}
|
||||
|
||||
/**
|
||||
* 发送modbus
|
||||
* @param key
|
||||
*/
|
||||
void MQTT_Send_Modbus(rt_uint16_t key)
|
||||
{
|
||||
|
||||
rt_sprintf(buffer_sn2 , "AT+MQTTPUB=\"v1/devices/me/telemetry\",0,0,\"{\"Modbus\":%d}\"\r\n" , key);
|
||||
|
||||
AT_send(buffer_sn2);
|
||||
}
|
||||
|
||||
/**
|
||||
* 发送转速针数
|
||||
*/
|
||||
//void MQTT_Send_SpeedNeedle()
|
||||
//{
|
||||
// rt_sprintf(buffer_sn , "AT+MQTTPUB=\"v1/devices/me/telemetry\",0,0,\"{\"Speed\":%d;\"NeedlCount\":%d}\"\r\n" , get_Data_Speed(get_Flag_Speed_IO()) , get_Data_NeedleCount(get_Flag_Needle_IO()));
|
||||
// AT_send(buffer_sn);
|
||||
//}
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief 设置MQTT服务器IP地址
|
||||
* @param rt_uint8_t addr MQTT服务器的IP地址值
|
||||
* @return none
|
||||
*/
|
||||
void set_MQTT_ADDR(char* addr)
|
||||
{
|
||||
for (rt_uint8_t var = 0; var < sizeof(MQTT.MQTT_ADDR); var++)
|
||||
{
|
||||
MQTT.MQTT_ADDR[var] = addr[var];
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 获取MQTT服务器IP地址
|
||||
* @return rt_uint8_t 返回MQTT服务器的IP地址值
|
||||
*/
|
||||
char* get_MQTT_ADDR()
|
||||
{
|
||||
return MQTT.MQTT_ADDR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置MQTT服务器端口
|
||||
* @param rt_uint8_t port MQTT服务器的端口号
|
||||
* @return none
|
||||
*/
|
||||
void set_MQTT_PORT(char* port)
|
||||
{
|
||||
for (rt_uint8_t var = 0; var < sizeof(MQTT.MQTT_PORT); var++)
|
||||
{
|
||||
MQTT.MQTT_PORT[var] = port[var];
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 获取MQTT服务器端口
|
||||
* @return rt_uint8_t 返回MQTT服务器的端口号
|
||||
*/
|
||||
char* get_MQTT_PORT()
|
||||
{
|
||||
return MQTT.MQTT_PORT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置MQTT客户端ID
|
||||
* @param rt_uint8_t cli_id MQTT客户端ID值
|
||||
* @return none
|
||||
*/
|
||||
void set_MQTT_CLI_ID(char* cli_id)
|
||||
{
|
||||
for (rt_uint8_t var = 0; var < sizeof(MQTT.MQTT_CLI_ID); var++)
|
||||
{
|
||||
MQTT.MQTT_CLI_ID[var] = cli_id[var];
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 获取MQTT客户端ID
|
||||
* @return rt_uint8_t 返回MQTT客户端ID值
|
||||
*/
|
||||
char* get_MQTT_CLI_ID()
|
||||
{
|
||||
return MQTT.MQTT_CLI_ID;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置MQTT用户名
|
||||
* @param rt_uint8_t username MQTT用户名值
|
||||
* @return none
|
||||
*/
|
||||
void set_MQTT_USERNAME(char* username)
|
||||
{
|
||||
for (rt_uint8_t var = 0; var < sizeof(MQTT.MQTT_USERNAME); var++)
|
||||
{
|
||||
MQTT.MQTT_USERNAME[var] = username[var];
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 获取MQTT用户名
|
||||
* @return rt_uint8_t 返回MQTT用户名值
|
||||
*/
|
||||
char* get_MQTT_USERNAME()
|
||||
{
|
||||
return MQTT.MQTT_USERNAME;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置MQTT密码
|
||||
* @param rt_uint8_t pwd MQTT密码值
|
||||
* @return none
|
||||
*/
|
||||
void set_MQTT_PWD(char* PWD)
|
||||
{
|
||||
for (rt_uint8_t var = 0; var < sizeof(MQTT.MQTT_PWD); var++)
|
||||
{
|
||||
MQTT.MQTT_PWD[var] = PWD[var];
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 获取MQTT密码
|
||||
* @return rt_uint8_t 返回MQTT密码值
|
||||
*/
|
||||
char* get_MQTT_PWD()
|
||||
{
|
||||
return MQTT.MQTT_PWD;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置MQTT订阅话题
|
||||
* @param rt_uint8_t topic MQTT订阅话题值
|
||||
* @return none
|
||||
*/
|
||||
void set_MQTT_TOPIC(rt_uint8_t topic)
|
||||
{
|
||||
MQTT.MQTT_TOPIC = topic;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 获取MQTT订阅话题
|
||||
* @return rt_uint8_t 返回MQTT订阅话题值
|
||||
*/
|
||||
rt_uint8_t get_MQTT_TOPIC()
|
||||
{
|
||||
return MQTT.MQTT_TOPIC;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置MQTT连接状态
|
||||
* @param rt_uint8_t status MQTT连接状态值（1已连接，0未连接）
|
||||
* @return none
|
||||
*/
|
||||
void set_MQTT_STATUS(rt_uint8_t status)
|
||||
{
|
||||
MQTT.MQTT_STATUS = status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 获取MQTT连接状态
|
||||
* @return rt_uint8_t 返回MQTT连接状态值（1已连接，0未连接）
|
||||
*/
|
||||
rt_uint8_t get_MQTT_STATUS()
|
||||
{
|
||||
return MQTT.MQTT_STATUS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置MQTT配置更新标志位
|
||||
* @param rt_uint8_t update_flag MQTT配置更新标志位值（1有更新，0无更新，2无改变）
|
||||
* @return none
|
||||
*/
|
||||
void set_MQTT_UPDATE_FLAG(rt_uint8_t update_flag)
|
||||
{
|
||||
MQTT.MQTT_UPDATE_FLAG = update_flag;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 获取MQTT配置更新标志位
|
||||
* @return rt_uint8_t 返回MQTT配置更新标志位值（1有更新，0无更新，2无改变）
|
||||
*/
|
||||
rt_uint8_t get_MQTT_UPDATE_FLAG()
|
||||
{
|
||||
return MQTT.MQTT_UPDATE_FLAG;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置/获取Key值
|
||||
* @param rt_uint8_t key 要设置的Key值
|
||||
* @return rt_uint8_t 返回当前的Key值
|
||||
*/
|
||||
void set_MQTT_Key(rt_uint8_t key)
|
||||
{
|
||||
MQTT.Key = key;
|
||||
}
|
||||
|
||||
rt_uint8_t get_MQTT_Key()
|
||||
{
|
||||
return MQTT.Key;
|
||||
}
|
||||
147
applications/AIR820/MQTT.h
Normal file
147
applications/AIR820/MQTT.h
Normal file
@ -0,0 +1,147 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-04-18 GOATS the first version
|
||||
*/
|
||||
#ifndef APPLICATIONS_WIRELESS_MQTT_H_
|
||||
#define APPLICATIONS_WIRELESS_MQTT_H_
|
||||
|
||||
#include <LTE.h>
|
||||
|
||||
typedef struct
|
||||
{
|
||||
char MQTT_ADDR[16]; // MQTT IP地址
|
||||
char MQTT_PORT[9]; // 端口
|
||||
char MQTT_CLI_ID[16]; // 客户端ID
|
||||
char MQTT_USERNAME[16]; // 用户名
|
||||
char MQTT_PWD[16]; // 密码
|
||||
rt_uint8_t MQTT_TOPIC; // 订阅话题
|
||||
rt_uint8_t MQTT_STATUS; // 连接状态：1已连接 0未连接
|
||||
rt_uint8_t MQTT_UPDATE_FLAG; // 配置更新标志位：1有更新 0无更新 2无改变
|
||||
rt_uint8_t log; // log
|
||||
|
||||
rt_uint8_t Key;
|
||||
|
||||
} MQTT_t; // MQTT配置与状态
|
||||
|
||||
|
||||
#define MQTT_PUBTOPIC "v1/devices/me/telemetry"
|
||||
#define MQTT_SUBTOPIC "v1/devices/me/attributes"
|
||||
|
||||
void set_mqtt_log(uint8_t log);
|
||||
|
||||
//MQTT初始化
|
||||
rt_uint8_t MQTT_init();
|
||||
|
||||
//获取MQTT连接状态
|
||||
rt_uint8_t get_MQTT_Status_flag();
|
||||
|
||||
//MQTT心跳
|
||||
void MQTT_Keep_Alive();
|
||||
|
||||
//MQTT重启
|
||||
void MQTT_RE_init();
|
||||
|
||||
//发送电平信息
|
||||
void MQTT_Send_Key(rt_uint16_t key);
|
||||
|
||||
//发送modbus数据
|
||||
void MQTT_Send_Modbus(rt_uint16_t key);
|
||||
|
||||
//发送转速针数
|
||||
void MQTT_Send_SpeedNeedle();
|
||||
|
||||
// 设置MQTT服务器IP地址
|
||||
// @param rt_uint8_t addr MQTT服务器IP地址值
|
||||
// @return void 无返回值
|
||||
void set_MQTT_ADDR(char* addr); // 将addr值赋给全局MQTT结构体的MQTT_ADDR成员
|
||||
|
||||
// 获取MQTT服务器IP地址
|
||||
// @return rt_uint8_t 返回MQTT服务器IP地址值
|
||||
char* get_MQTT_ADDR(); // 返回全局MQTT结构体的MQTT_ADDR成员的值
|
||||
|
||||
// 设置MQTT服务器端口
|
||||
// @param rt_uint8_t port MQTT服务器端口号
|
||||
// @return void 无返回值
|
||||
void set_MQTT_PORT(char* port); // 将port值赋给全局MQTT结构体的MQTT_PORT成员
|
||||
|
||||
// 获取MQTT服务器端口
|
||||
// @return rt_uint8_t 返回MQTT服务器端口号
|
||||
char* get_MQTT_PORT(); // 返回全局MQTT结构体的MQTT_PORT成员的值
|
||||
|
||||
// 设置MQTT客户端ID
|
||||
// @param rt_uint8_t cli_id MQTT客户端ID值
|
||||
// @return void 无返回值
|
||||
void set_MQTT_CLI_ID(char* cli_id); // 将cli_id值赋给全局MQTT结构体的MQTT_CLI_ID成员
|
||||
|
||||
// 获取MQTT客户端ID
|
||||
// @return rt_uint8_t 返回MQTT客户端ID值
|
||||
char* get_MQTT_CLI_ID(); // 返回全局MQTT结构体的MQTT_CLI_ID成员的值
|
||||
|
||||
// 设置MQTT用户名
|
||||
// @param rt_uint8_t username MQTT用户名值
|
||||
// @return void 无返回值
|
||||
void set_MQTT_USERNAME(char* username); // 将username值赋给全局MQTT结构体的MQTT_USERNAME成员
|
||||
|
||||
// 获取MQTT用户名
|
||||
// @return rt_uint8_t 返回MQTT用户名值
|
||||
char* get_MQTT_USERNAME(); // 返回全局MQTT结构体的MQTT_USERNAME成员的值
|
||||
|
||||
// 设置MQTT密码
|
||||
// @param rt_uint8_t pwd MQTT密码值
|
||||
// @return void 无返回值
|
||||
void set_MQTT_PWD(char* pwd); // 将pwd值赋给全局MQTT结构体的MQTT_PWD成员
|
||||
|
||||
// 获取MQTT密码
|
||||
// @return rt_uint8_t 返回MQTT密码值
|
||||
char* get_MQTT_PWD(); // 返回全局MQTT结构体的MQTT_PWD成员的值
|
||||
|
||||
// 设置MQTT订阅话题
|
||||
// @param rt_uint8_t topic MQTT订阅话题值
|
||||
// @return void 无返回值
|
||||
void set_MQTT_TOPIC(rt_uint8_t topic); // 将topic值赋给全局MQTT结构体的MQTT_TOPIC成员
|
||||
|
||||
// 获取MQTT订阅话题
|
||||
// @return rt_uint8_t 返回MQTT订阅话题值
|
||||
rt_uint8_t get_MQTT_TOPIC(); // 返回全局MQTT结构体的MQTT_TOPIC成员的值
|
||||
|
||||
// 设置MQTT连接状态
|
||||
// @param rt_uint8_t status MQTT连接状态值（1已连接，0未连接）
|
||||
// @return void 无返回值
|
||||
void set_MQTT_STATUS(rt_uint8_t status); // 将status值赋给全局MQTT结构体的MQTT_STATUS成员
|
||||
|
||||
// 获取MQTT连接状态
|
||||
// @return rt_uint8_t 返回MQTT连接状态值（1已连接，0未连接）
|
||||
rt_uint8_t get_MQTT_STATUS(); // 返回全局MQTT结构体的MQTT_STATUS成员的值
|
||||
|
||||
// 设置MQTT配置更新标志位
|
||||
// @param rt_uint8_t update_flag MQTT配置更新标志位值（1有更新，0无更新，2无改变）
|
||||
// @return void 无返回值
|
||||
void set_MQTT_UPDATE_FLAG(rt_uint8_t update_flag); // 将update_flag值赋给全局MQTT结构体的MQTT_UPDATE_FLAG成员
|
||||
|
||||
// 获取MQTT配置更新标志位
|
||||
// @return rt_uint8_t 返回MQTT配置更新标志位值（1有更新，0无更新，2无改变）
|
||||
rt_uint8_t get_MQTT_UPDATE_FLAG(); // 返回全局MQTT结构体的MQTT_UPDATE_FLAG成员的值
|
||||
|
||||
// 设置MQTT配置保存标志位
|
||||
// @param rt_uint8_t save_flag MQTT配置保存标志位值（1已保存，0未保存，2无改变）
|
||||
// @return void 无返回值
|
||||
void set_MQTT_SAVE_FLAG(rt_uint8_t save_flag); // 将save_flag值赋给全局MQTT结构体的MQTT_SAVE_FLAG成员
|
||||
|
||||
// 获取MQTT配置保存标志位
|
||||
// @return rt_uint8_t 返回MQTT配置保存标志位值（1已保存，0未保存，2无改变）
|
||||
rt_uint8_t get_MQTT_SAVE_FLAG(); // 返回全局MQTT结构体的MQTT_SAVE_FLAG成员的值
|
||||
|
||||
// 设置/获取Key值
|
||||
// @param rt_uint8_t key 要设置的Key值
|
||||
// @return rt_uint8_t 返回当前的Key值
|
||||
void set_MQTT_Key(rt_uint8_t key); // 将key值赋给全局MQTT结构体的Key成员
|
||||
|
||||
rt_uint8_t get_MQTT_Key(); // 返回全局MQTT结构体的Key成员的值
|
||||
|
||||
|
||||
#endif /* APPLICATIONS_WIRELESS_MQTT_H_ */
|
||||
151
applications/IO/inout.c
Normal file
151
applications/IO/inout.c
Normal file
@ -0,0 +1,151 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-05-06 lijian the first version
|
||||
*/
|
||||
#include <inout.h>
|
||||
|
||||
|
||||
IO_t IO;
|
||||
|
||||
//输入端口列表
|
||||
rt_base_t input_pins[] = {
|
||||
GET_PIN(C, 2),
|
||||
GET_PIN(C, 3),
|
||||
GET_PIN(C, 4),
|
||||
GET_PIN(A, 5),
|
||||
GET_PIN(A, 6),
|
||||
GET_PIN(A, 7),
|
||||
GET_PIN(A, 8),
|
||||
GET_PIN(C, 9),
|
||||
|
||||
};
|
||||
|
||||
//输出端口列表
|
||||
rt_base_t output_pins[] = {
|
||||
|
||||
GET_PIN(B, 12),
|
||||
GET_PIN(B, 13),
|
||||
GET_PIN(B, 14),
|
||||
GET_PIN(B, 15),
|
||||
GET_PIN(C, 6),
|
||||
GET_PIN(C, 7),
|
||||
GET_PIN(C, 8),
|
||||
GET_PIN(A, 11),
|
||||
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* 端口中断回调函数
|
||||
* @param args
|
||||
*/
|
||||
void gpio_irq_callback(void *args)
|
||||
{
|
||||
rt_base_t pin = (rt_base_t)(uintptr_t)args; // 获取触发中断的引脚号
|
||||
rt_kprintf("pin: %#x", pin);
|
||||
switch (pin)
|
||||
{
|
||||
case IN1:
|
||||
IO.IO_Data[0].Temp_Count++;
|
||||
//rt_kprintf("pin1:%d\n", IO.IO_Data[0].Temp_Count);
|
||||
break;
|
||||
case IN2:
|
||||
IO.IO_Data[1].Temp_Count++;
|
||||
//rt_kprintf("pin2:%d\n", IO.IO_Data[1].Temp_Count);
|
||||
break;
|
||||
case IN3:
|
||||
IO.IO_Data[2].Temp_Count++;
|
||||
//rt_kprintf("pin3:%d\n", IO.IO_Data[2].Temp_Count);
|
||||
break;
|
||||
case IN4:
|
||||
IO.IO_Data[3].Temp_Count++;
|
||||
//rt_kprintf("pin4:%d\n", IO.IO_Data[3].Temp_Count);
|
||||
break;
|
||||
case IN5:
|
||||
IO.IO_Data[4].Temp_Count++;
|
||||
//rt_kprintf("pin5:%d\n", IO.IO_Data[4].Temp_Count);
|
||||
break;
|
||||
case IN6:
|
||||
IO.IO_Data[5].Temp_Count++;
|
||||
//rt_kprintf("pin6:%d\n", IO.IO_Data[5].Temp_Count);
|
||||
break;
|
||||
case IN7:
|
||||
IO.IO_Data[6].Temp_Count++;
|
||||
//rt_kprintf("pin7:%d\n", IO.IO_Data[6].Temp_Count);
|
||||
break;
|
||||
case IN8:
|
||||
IO.IO_Data[7].Temp_Count++;
|
||||
//rt_kprintf("pin8:%d\n", IO.IO_Data[7].Temp_Count);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
//配置输入引脚
|
||||
void configure_inpin(rt_base_t pin)
|
||||
{
|
||||
// 设置引脚模式为上拉输入
|
||||
rt_pin_mode(pin, PIN_MODE_INPUT_PULLUP);
|
||||
|
||||
rt_kprintf(" pin: %d %#x\r\n", pin, pin);
|
||||
/* 绑定中断，下降沿模式，回调函数名为 */
|
||||
rt_pin_attach_irq(pin, PIN_IRQ_MODE_FALLING, gpio_irq_callback, (void *)(uintptr_t)pin);
|
||||
/* 使能中断 */
|
||||
rt_pin_irq_enable(pin, PIN_IRQ_ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* 输入引脚初始化
|
||||
*/
|
||||
void gpio_input_init(void)
|
||||
{
|
||||
rt_kprintf(" pin list:\r\n");
|
||||
|
||||
for (rt_uint8_t var = 0; var < INPUT_NUM; var++)
|
||||
{
|
||||
configure_inpin(input_pins[var]);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* 输出引脚默认为高电平
|
||||
* @param pin
|
||||
*/
|
||||
void configure_outpin(rt_base_t pin) {
|
||||
// 设置引脚模式为输出模式
|
||||
rt_pin_mode(pin, PIN_MODE_OUTPUT);
|
||||
// 默认为高电平
|
||||
rt_pin_write(pin, PIN_HIGH);
|
||||
}
|
||||
|
||||
//输出引脚初始化
|
||||
void gpio_output_init(void){
|
||||
for (rt_uint8_t var = 0; var < OUTPUT_NUM; var++) {
|
||||
configure_outpin(output_pins[var]);
|
||||
}
|
||||
}
|
||||
|
||||
//获取端口电平触发次数
|
||||
rt_uint32_t get_IO_count(rt_uint8_t io){
|
||||
return IO.IO_Data[io].Temp_Count;
|
||||
}
|
||||
|
||||
//控制台更改电平
|
||||
void IO_key(int argc, char**argv){
|
||||
|
||||
rt_uint8_t var = atoi(argv[1]);
|
||||
rt_uint8_t var2 = atoi(argv[2]);
|
||||
if (var2) {
|
||||
rt_pin_write(output_pins[var], PIN_HIGH);
|
||||
} else {
|
||||
rt_pin_write(output_pins[var], PIN_LOW);
|
||||
}
|
||||
}
|
||||
|
||||
MSH_CMD_EXPORT(IO_key, chage IO);
|
||||
87
applications/IO/inout.h
Normal file
87
applications/IO/inout.h
Normal file
@ -0,0 +1,87 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-05-06 lijian the first version
|
||||
*/
|
||||
#ifndef APPLICATIONS_IO_INOUT_H_
|
||||
#define APPLICATIONS_IO_INOUT_H_
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <drv_common.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
#define OUTPUT_NUM 8
|
||||
#define INPUT_NUM 8
|
||||
|
||||
#define IN1 0x22
|
||||
#define IN2 0x23
|
||||
#define IN3 0x24
|
||||
#define IN4 0x5
|
||||
#define IN5 0x6
|
||||
#define IN6 0x7
|
||||
#define IN7 0x8
|
||||
#define IN8 0x29
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
rt_uint8_t Key; // 电平键值
|
||||
rt_uint8_t Key_Flag; // 电平键值
|
||||
rt_uint8_t InputType; // 输入类型 0输入 1转速 2针数
|
||||
rt_uint32_t Temp_Count; //中断触发次数
|
||||
rt_uint32_t Count; // 高低电平交替后触发次数
|
||||
rt_uint32_t NeedleCount; // 当前针数
|
||||
rt_uint32_t NeedleCount_last; // 当前针数
|
||||
rt_uint32_t NeedleCount_Sum; // 总针数
|
||||
rt_uint32_t Speed; // 速度
|
||||
rt_uint32_t Month_Count; // 月电平触发次数
|
||||
rt_uint32_t Month_NeedleCount_Sum; // 月总针数
|
||||
rt_uint32_t Old_Count; // 总电平触发次数
|
||||
rt_uint32_t Old_NeedleCount_Sum; // 总总针数
|
||||
} Data; // IO数据
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
rt_uint32_t Ok_Num; // 产量
|
||||
rt_uint32_t Month_Num; // 月总产量
|
||||
rt_uint32_t Old_Num; // 历史产量
|
||||
rt_uint8_t Write_Flag; // 写入eeprom标志位：1已写入 0未写入
|
||||
rt_uint8_t Speed_io;//速度端口
|
||||
rt_uint8_t Needle_io;//针数端口
|
||||
rt_uint8_t SpeedUpdateFlag; // 速度更新标志位
|
||||
rt_uint8_t NeedleCountUpdateFlag; // 针数更新标志位
|
||||
} Flag; // IO状态
|
||||
|
||||
typedef struct
|
||||
{
|
||||
rt_uint8_t InputType; // 输入类型
|
||||
rt_uint8_t Key; // 键值
|
||||
} Out; // 输出IO状态
|
||||
|
||||
typedef struct
|
||||
{
|
||||
Out IO_Out[15]; // IO输出端口状态
|
||||
Data IO_Data[15]; // IO当前数据
|
||||
Flag IO_Flag; // IO状态
|
||||
|
||||
} IO_t; //IO结构体
|
||||
|
||||
/**
|
||||
* 输入引脚初始化
|
||||
*/
|
||||
void gpio_input_init(void);
|
||||
|
||||
//输出引脚初始化
|
||||
void gpio_output_init(void);
|
||||
|
||||
//获取端口电平触发次数
|
||||
rt_uint32_t get_IO_count(rt_uint8_t io);
|
||||
|
||||
//控制台更改电平
|
||||
void IO_key();
|
||||
#endif /* APPLICATIONS_IO_INOUT_H_ */
|
||||
370
applications/Modbus/modbus_rtu.c
Normal file
370
applications/Modbus/modbus_rtu.c
Normal file
@ -0,0 +1,370 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-04-23 lijian the first version
|
||||
*/
|
||||
#include "modbus_rtu.h"
|
||||
#include <board.h>
|
||||
|
||||
Modbus_RTU_t Modbus_RTU;
|
||||
|
||||
/**
|
||||
* 设置modbus从机地址
|
||||
* @param modbus_addr
|
||||
*/
|
||||
void set_Modbus_Addr(rt_uint16_t modbus_addr)
|
||||
{
|
||||
Modbus_RTU.modbus_addr = modbus_addr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 获取Modbus从机地址
|
||||
* @return rt_uint16
|
||||
*/
|
||||
rt_uint16_t get_Modbus_Addr()
|
||||
{
|
||||
return Modbus_RTU.modbus_addr;
|
||||
}
|
||||
|
||||
/**
|
||||
* 设置modbus寄存器地址
|
||||
* @param modbus_reg_addr
|
||||
*/
|
||||
void set_Modbus_Reg_Addr(rt_uint16_t modbus_reg_addr)
|
||||
{
|
||||
Modbus_RTU.modbus_reg_addr = modbus_reg_addr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 获取Modbus读取寄存器起始地址
|
||||
* @return rt_uint16
|
||||
*/
|
||||
rt_uint16_t get_Modbus_Reg_Addr()
|
||||
{
|
||||
return Modbus_RTU.modbus_reg_addr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 设置Modbus读寄存器数量
|
||||
* @return rt_uint16
|
||||
*/
|
||||
void set_Modbus_Reg_Num(rt_uint16_t modbus_reg_num)
|
||||
{
|
||||
Modbus_RTU.modbus_reg_num = modbus_reg_num;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 获取Modbus读寄存器数量
|
||||
* @return rt_uint16
|
||||
*/
|
||||
rt_uint16_t get_Modbus_Reg_Num()
|
||||
{
|
||||
return Modbus_RTU.modbus_reg_num;
|
||||
}
|
||||
|
||||
|
||||
|
||||
//功能码01（0x01）: 读线圈状态（Read Coils）
|
||||
//功能码02（0x02）: 读离散输入状态（Read Discrete Inputs）
|
||||
//功能码03（0x03）: 读保持寄存器（Read Holding Registers）
|
||||
//功能码04（0x04）: 读输入寄存器（Read Input Registers）
|
||||
//功能码05（0x05）: 写单个线圈（Write Single Coil）
|
||||
//功能码06（0x06）: 写单个保持寄存器（Write Single Holding Register）
|
||||
//功能码15（0x0F）: 写多个线圈（Write Multiple Coils）
|
||||
//功能码16（0x10）: 写多个保持寄存器（Write Multiple Holding Registers）
|
||||
|
||||
/**
|
||||
* modbus初始化
|
||||
*/
|
||||
void Modbus_init()
|
||||
{
|
||||
|
||||
// Modbus_RTU.modbus_addr = (rt_uint16_t)0x01;
|
||||
// Modbus_RTU.modbus_reg_addr = (rt_uint16_t)0x00;
|
||||
// Modbus_RTU.modbus_reg_num = (rt_uint16_t)0x02;
|
||||
|
||||
rs485_inst_t *hinst = rs485_create(RS485_SAMPLE_MASTER_SERIAL, RS485_SAMPLE_MASTER_BAUDRATE,
|
||||
RS485_SAMPLE_MASTER_PARITY, RS485_SAMPLE_MASTER_PIN, RS485_SAMPLE_MASTER_LVL);
|
||||
|
||||
if (hinst == RT_NULL)
|
||||
{
|
||||
rt_kprintf("create rs485 instance fail.\n");
|
||||
return;
|
||||
}
|
||||
|
||||
rs485_set_recv_tmo(hinst, 1000);
|
||||
if (rs485_connect(hinst) != RT_EOK)
|
||||
{
|
||||
rs485_destory(hinst);
|
||||
rt_kprintf("rs485 connect fail.\n");
|
||||
return;
|
||||
}
|
||||
|
||||
rt_uint8_t ctx_send_buf[AGILE_MODBUS_MAX_ADU_LENGTH];
|
||||
rt_uint8_t ctx_read_buf[AGILE_MODBUS_MAX_ADU_LENGTH];
|
||||
|
||||
|
||||
agile_modbus_rtu_t ctx_rtu;
|
||||
agile_modbus_t *ctx = &ctx_rtu._ctx;
|
||||
agile_modbus_rtu_init(&ctx_rtu, ctx_send_buf, sizeof(ctx_send_buf), ctx_read_buf, sizeof(ctx_read_buf));
|
||||
agile_modbus_set_slave(ctx, Modbus_RTU.modbus_addr); //地址
|
||||
rt_kprintf("Modbus Running.\n");
|
||||
|
||||
|
||||
rt_int8_t send_len;
|
||||
rt_int8_t read_len;
|
||||
rt_uint8_t i;
|
||||
rt_int8_t rc;
|
||||
|
||||
//
|
||||
|
||||
|
||||
while (1)
|
||||
{
|
||||
rt_thread_mdelay(1000);
|
||||
|
||||
|
||||
//if(Modbus_RTU.modbus_func == 3){
|
||||
send_len = agile_modbus_serialize_read_registers(ctx, Modbus_RTU.modbus_reg_addr, Modbus_RTU.modbus_reg_num);
|
||||
//
|
||||
// } else if(Modbus_RTU.modbus_func == 1){
|
||||
// send_len = agile_modbus_serialize_read_bits(ctx, Modbus_RTU.modbus_reg_addr, Modbus_RTU.modbus_reg_num);
|
||||
//
|
||||
// }
|
||||
|
||||
// rt_kprintf("rs485 send %d datas : ", send_len);
|
||||
// for (i = 0; i < send_len; i++) {
|
||||
// rt_kprintf("%02X ", ctx->send_buf[i]);
|
||||
// }
|
||||
|
||||
// rt_kprintf("\n");
|
||||
|
||||
read_len = rs485_send_then_recv(hinst, (void *) ctx->send_buf, send_len, ctx->read_buf, ctx->read_bufsz);
|
||||
if (read_len < 0)
|
||||
{
|
||||
// rt_kprintf("rs485 send datas error.\n");
|
||||
break;
|
||||
}
|
||||
|
||||
if (read_len == 0)
|
||||
{
|
||||
// rt_kprintf("rs485 recv timeout.\n");
|
||||
continue;
|
||||
}
|
||||
|
||||
ctx->read_buf[read_len] = 0;
|
||||
|
||||
// Bsp_Rs485_Tx(ctx->send_buf, send_len); //
|
||||
// int read_len = Bsp_Rs485_Rx(ctx->read_buf, ctx->read_bufsz); //
|
||||
|
||||
if (read_len == 0)
|
||||
{
|
||||
// rt_kprintf("Receive timeout.\n");
|
||||
continue;
|
||||
}
|
||||
rc = agile_modbus_deserialize_read_registers(ctx, read_len, Modbus_RTU.hold_register);
|
||||
if (rc < 0)
|
||||
{
|
||||
Modbus_RTU.modbus_rec = 0;
|
||||
|
||||
rt_kprintf("Receive failed.\n");
|
||||
if (rc != -1)
|
||||
rt_kprintf("Error code:%d\n", -128 - rc);
|
||||
continue;
|
||||
}
|
||||
|
||||
Modbus_RTU.modbus_rec = 1;
|
||||
|
||||
if (Modbus_RTU.log) {
|
||||
rt_kprintf("Hold Registers:");
|
||||
for (i = 0; i < 10; i++)
|
||||
rt_kprintf("Register [%d]: 0x%04X\n", i, Modbus_RTU.hold_register[i]);
|
||||
}
|
||||
|
||||
if (Modbus_RTU.modbus_rec) {
|
||||
//get_modbus_rec();
|
||||
// MQTT_Send_Modbus(get_modbus_rec());
|
||||
}
|
||||
rt_kprintf("\r\n\r\n\r\n");
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void set_modbus_log(rt_uint8_t log){
|
||||
Modbus_RTU.log = log;
|
||||
}
|
||||
|
||||
/**
|
||||
* 获取modbus读取数据的转换后返回值
|
||||
* @return
|
||||
*/
|
||||
rt_uint16_t get_modbus_rec(){
|
||||
if (Modbus_RTU.modbus_rec) {
|
||||
|
||||
rt_uint8_t high_d=0;
|
||||
rt_uint8_t low_d=0;
|
||||
|
||||
if (Modbus_RTU.modbus_reg_num == 2) {
|
||||
high_d = Modbus_RTU.hold_register[0];
|
||||
low_d = Modbus_RTU.hold_register[1];
|
||||
rt_uint16_t rec = (high_d << 8) | low_d;
|
||||
return rec;
|
||||
}
|
||||
Modbus_RTU.modbus_rec =0;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
//void Bsp_Rs485_Tx(){
|
||||
//
|
||||
//}
|
||||
//
|
||||
//void Bsp_Rs485_Rx(){
|
||||
//
|
||||
//}
|
||||
//
|
||||
//static void rs485_sample_master(void *args)
|
||||
//{
|
||||
// const char read_cmd[] = "read datas test\r\n";
|
||||
// static rt_uint8_t buf[256];
|
||||
// rs485_inst_t *hinst = rs485_create(RS485_SAMPLE_MASTER_SERIAL, RS485_SAMPLE_MASTER_BAUDRATE,
|
||||
// RS485_SAMPLE_MASTER_PARITY, RS485_SAMPLE_MASTER_PIN, RS485_SAMPLE_MASTER_LVL);
|
||||
//
|
||||
// if (hinst == RT_NULL)
|
||||
// {
|
||||
// LOG_E("create rs485 instance fail.");
|
||||
// return;
|
||||
// }
|
||||
//
|
||||
// rs485_set_recv_tmo(hinst, 1000);
|
||||
// if (rs485_connect(hinst) != RT_EOK)
|
||||
// {
|
||||
// rs485_destory(hinst);
|
||||
// LOG_E("rs485 connect fail.");
|
||||
// return;
|
||||
// }
|
||||
//
|
||||
// while (1)
|
||||
// {
|
||||
// int len = strlen(read_cmd);
|
||||
// len = rs485_send_then_recv(hinst, (void *) read_cmd, len, buf, sizeof(buf));
|
||||
// if (len < 0)
|
||||
// {
|
||||
// LOG_E("rs485 send datas error.");
|
||||
// break;
|
||||
// }
|
||||
//
|
||||
// if (len == 0)
|
||||
// {
|
||||
// LOG_D("rs485 recv timeout.");
|
||||
// continue;
|
||||
// }
|
||||
//
|
||||
// buf[len] = 0;
|
||||
// LOG_D("rs485 recv %d datas : %s", len, buf);
|
||||
// }
|
||||
//
|
||||
//}
|
||||
|
||||
//
|
||||
//#define PORT_NUM MB_MASTER_USING_PORT_NUM
|
||||
//#define PORT_BAUDRATE MB_MASTER_USING_PORT_BAUDRATE
|
||||
//
|
||||
//#define PORT_PARITY MB_PAR_EVEN
|
||||
//
|
||||
//#define MB_POLL_CYCLE_MS 500
|
||||
//
|
||||
//#define func_Coil 1
|
||||
//#define func_Holding 3
|
||||
//
|
||||
//#define MODBUS_REG_NUM 30
|
||||
|
||||
//rt_uint16_t buffer[MODBUS_REG_NUM];
|
||||
//
|
||||
///*
|
||||
// *
|
||||
|
||||
// *
|
||||
// */
|
||||
//
|
||||
//void Copy_Holding(rt_uint16_t * Holding, rt_uint16_t reg_num){
|
||||
// rt_uint16_t * a = get_modbus_03();
|
||||
// for (rt_uint8_t var = 0; var < reg_num; var++) {
|
||||
// Holding[var] = a[var];
|
||||
// }
|
||||
//}
|
||||
//
|
||||
//void Copy_Coil(rt_uint16_t * Coil, rt_uint16_t reg_num){
|
||||
// unsigned char * a = get_modbus_01();
|
||||
// for (rt_uint8_t var = 0; var < reg_num; var++) {
|
||||
// Coil[var] = a[var];
|
||||
// }
|
||||
//}
|
||||
//
|
||||
//
|
||||
//
|
||||
//void Modbus_Read_Holding_Registers(rt_uint16_t addr, rt_uint16_t reg_addr, rt_uint16_t reg_num, rt_uint16_t * Holding){
|
||||
//
|
||||
// while(1){
|
||||
// eMBMasterPoll();
|
||||
//
|
||||
// /*
|
||||
// * ucSndAddr 请求的从机地址，0代表广播。
|
||||
// usRegAddr 读寄存器的地址
|
||||
// usRegData 读寄存器的数量
|
||||
// lTimeOut 请求超时时间。支持永久等待，使用操作系统的永久等待参数即可。
|
||||
// */
|
||||
// eMBMasterReqReadHoldingRegister(addr, reg_addr, reg_num, 1000);
|
||||
//
|
||||
// rt_thread_mdelay(MB_POLL_CYCLE_MS);
|
||||
//
|
||||
// if (get_Holding_flag()) {
|
||||
// Copy_Holding(Holding, reg_num);
|
||||
// Modbus_RTU.modbus_rec =1;
|
||||
// get_modbus_rec();
|
||||
// }
|
||||
//
|
||||
// }
|
||||
//}
|
||||
//
|
||||
//void Modbus_Read_Coils(rt_uint16_t addr, rt_uint16_t reg_addr, rt_uint16_t reg_num, rt_uint16_t * Coil){
|
||||
//
|
||||
// while(1){
|
||||
// eMBMasterPoll();
|
||||
//
|
||||
// /*
|
||||
// * ucSndAddr 请求的从机地址，0代表广播。
|
||||
// usCoilAddr 读线圈的地址
|
||||
// usNCoils 读线圈的数量
|
||||
// lTimeOut 请求超时时间。支持永久等待，使用操作系统的永久等待参数即可
|
||||
// */
|
||||
// eMBMasterReqReadCoils(addr, reg_addr, reg_num, 1000);
|
||||
//
|
||||
// rt_thread_mdelay(MB_POLL_CYCLE_MS);
|
||||
// if (get_Coil_flag()) {
|
||||
// Copy_Coil(Coil , reg_num);
|
||||
// Modbus_RTU.modbus_rec =1;
|
||||
// }
|
||||
// }
|
||||
//}
|
||||
//
|
||||
//
|
||||
//void Modbus_config(void){
|
||||
//
|
||||
// eMBMasterInit(MB_RTU, PORT_NUM, PORT_BAUDRATE, PORT_PARITY);
|
||||
// eMBMasterEnable();
|
||||
//
|
||||
//// if(Modbus_RTU.modbus_func == func_Holding){
|
||||
// Modbus_Read_Holding_Registers(Modbus_RTU.modbus_addr, Modbus_RTU.modbus_reg_addr, Modbus_RTU.modbus_reg_num ,buffer);
|
||||
//// } else if(Modbus_RTU.modbus_func == func_Coil){
|
||||
//// Modbus_Read_Coils(Modbus_RTU.modbus_addr, Modbus_RTU.modbus_reg_addr, Modbus_RTU.modbus_reg_num , buffer);
|
||||
//// }
|
||||
//
|
||||
//}
|
||||
//
|
||||
|
||||
|
||||
77
applications/Modbus/modbus_rtu.h
Normal file
77
applications/Modbus/modbus_rtu.h
Normal file
@ -0,0 +1,77 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-04-23 lijian the first version
|
||||
*/
|
||||
#ifndef APPLICATIONS_MODBUS_MODBUS_RTU_H_
|
||||
#define APPLICATIONS_MODBUS_MODBUS_RTU_H_
|
||||
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <drv_common.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
#include "rs485.h"
|
||||
|
||||
//int rs485_init(void);
|
||||
//int rs485_send(uint8_t *buf, int len);
|
||||
//int rs485_receive(uint8_t *buf, int bufsz, int timeout, int bytes_timeout);
|
||||
|
||||
|
||||
#include "agile_modbus.h"
|
||||
#include "agile_modbus_rtu.h"
|
||||
#include <rs485.h>
|
||||
|
||||
typedef struct
|
||||
{
|
||||
rt_uint16_t modbus_addr;//从机地址
|
||||
rt_uint16_t modbus_reg_addr;//寄存器地址
|
||||
rt_uint16_t modbus_reg_num;//寄存器数量
|
||||
rt_uint8_t modbus_func;//功能码
|
||||
rt_uint8_t modbus_rec; //接收成功
|
||||
rt_uint8_t log; //log
|
||||
rt_uint16_t hold_register[10];
|
||||
} Modbus_RTU_t; //
|
||||
|
||||
//设置modbus从机地址
|
||||
void set_Modbus_Addr(rt_uint16_t modbus_addr);
|
||||
|
||||
//获取Modbus从机地址
|
||||
rt_uint16_t get_Modbus_Addr();
|
||||
|
||||
//设置modbus寄存器地址
|
||||
void set_Modbus_Reg_Addr(rt_uint16_t modbus_reg_addr);
|
||||
|
||||
//获取Modbus读取寄存器起始地址
|
||||
rt_uint16_t get_Modbus_Reg_Addr();
|
||||
|
||||
/**
|
||||
* @brief 设置Modbus读寄存器数量
|
||||
* @return rt_uint16
|
||||
*/
|
||||
void set_Modbus_Reg_Num(rt_uint16_t modbus_reg_num);
|
||||
|
||||
/**
|
||||
* @brief 获取Modbus读寄存器数量
|
||||
* @return rt_uint16
|
||||
*/
|
||||
rt_uint16_t get_Modbus_Reg_Num();
|
||||
|
||||
void set_modbus_log(rt_uint8_t log);
|
||||
|
||||
//modbus初始化
|
||||
void Modbus_init();
|
||||
|
||||
//获取modbus是否接收成功
|
||||
rt_uint16_t get_modbus_rec();
|
||||
|
||||
#endif /* APPLICATIONS_MODBUS_MODBUS_RTU_H_ */
|
||||
424
applications/OLED/gui.c
Normal file
424
applications/OLED/gui.c
Normal file
@ -0,0 +1,424 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-05-09 LJ the first version
|
||||
*/
|
||||
#include <gui.h>
|
||||
|
||||
rt_uint8_t key = 0;
|
||||
rt_uint8_t menu_index = 0;
|
||||
rt_uint8_t cnt = 0;
|
||||
void (*menu)();
|
||||
char buf[20];
|
||||
rt_base_t key_pins[] = { GET_PIN(C, 14), GET_PIN(C, 13), GET_PIN(B, 9), GET_PIN(B, 8), };
|
||||
|
||||
//开机界面
|
||||
void Menu_index()
|
||||
{
|
||||
//ssd1306_Fill(Black);
|
||||
ssd1306_SetCursor(9, 28);
|
||||
ssd1306_WriteString("GetonAgain", Font_11x18, White);
|
||||
ssd1306_UpdateScreenArea(9, 28, 110, 18);
|
||||
}
|
||||
|
||||
//Mqtt状态
|
||||
void Menu_MQTT()
|
||||
{
|
||||
ssd1306_FillArea(119, 2, 7, 10, Black);
|
||||
ssd1306_SetCursor(119, 2);
|
||||
ssd1306_WriteString("Y", Font_7x10, White);
|
||||
ssd1306_UpdateScreenArea(119, 2, 7, 10);
|
||||
}
|
||||
|
||||
//Mqtt状态
|
||||
void Menu_NO_MQTT()
|
||||
{
|
||||
ssd1306_FillArea(119, 2, 7, 10, Black);
|
||||
ssd1306_SetCursor(119, 2);
|
||||
ssd1306_WriteString("N", Font_7x10, White);
|
||||
ssd1306_UpdateScreenArea(119, 2, 7, 10);
|
||||
}
|
||||
|
||||
//LTE状态
|
||||
void Menu_LTE()
|
||||
{
|
||||
ssd1306_FillArea(93, 2, 7, 10, Black);
|
||||
ssd1306_SetCursor(93, 2);
|
||||
ssd1306_WriteString("Y", Font_7x10, White);
|
||||
ssd1306_UpdateScreenArea(93, 2, 7, 10);
|
||||
}
|
||||
|
||||
//LTE状态
|
||||
void Menu_NO_LTE()
|
||||
{
|
||||
ssd1306_FillArea(93, 2, 7, 10, Black);
|
||||
ssd1306_SetCursor(93, 2);
|
||||
ssd1306_WriteString("N", Font_7x10, White);
|
||||
ssd1306_UpdateScreenArea(93, 2, 7, 10);
|
||||
}
|
||||
|
||||
//状态栏显示
|
||||
void Menu_one()
|
||||
{
|
||||
// ssd1306_Fill(Black);
|
||||
ssd1306_FillArea(79, 2, 49, 10, Black);
|
||||
ssd1306_SetCursor(79, 2);
|
||||
ssd1306_WriteString("G:", Font_7x10, White);
|
||||
|
||||
ssd1306_SetCursor(105, 2);
|
||||
ssd1306_WriteString("M:", Font_7x10, White);
|
||||
ssd1306_UpdateScreenArea(79, 2, 49, 10);
|
||||
|
||||
// Menu_LTE();
|
||||
// Menu_NO_MQTT();
|
||||
|
||||
ssd1306_FillArea(0, 18, 128, 46, Black);
|
||||
|
||||
//ssd1306_Line(1, 12, SSD1306_WIDTH - 1, 12, White);
|
||||
ssd1306_SetCursor(2, 20);
|
||||
ssd1306_WriteString("index", Font_11x18, White);
|
||||
|
||||
// ssd1306_UpdateScreen();
|
||||
ssd1306_UpdateScreenArea(0, 18, 128, 46);
|
||||
}
|
||||
|
||||
//二极菜单
|
||||
void Menu2_IN()
|
||||
{
|
||||
ssd1306_FillArea(0, 18, 128, 46, Black);
|
||||
ssd1306_SetCursor(48, 25);
|
||||
ssd1306_WriteString("IN", Font_16x26, White);
|
||||
ssd1306_UpdateScreenArea(0, 18, 128, 46);
|
||||
}
|
||||
//二极菜单
|
||||
void Menu2_OUT()
|
||||
{
|
||||
ssd1306_FillArea(0, 18, 128, 46, Black);
|
||||
ssd1306_SetCursor(40, 25);
|
||||
ssd1306_WriteString("OUT", Font_16x26, White);
|
||||
ssd1306_UpdateScreenArea(0, 18, 128, 46);
|
||||
}
|
||||
//二极菜单
|
||||
void Menu2_485()
|
||||
{
|
||||
|
||||
ssd1306_FillArea(0, 18, 128, 46, Black);
|
||||
ssd1306_SetCursor(40, 25);
|
||||
ssd1306_WriteString("485", Font_16x26, White);
|
||||
|
||||
ssd1306_UpdateScreenArea(0, 18, 128, 46);
|
||||
}
|
||||
//二极菜单
|
||||
void Menu2_232()
|
||||
{
|
||||
|
||||
ssd1306_FillArea(0, 18, 128, 46, Black);
|
||||
ssd1306_SetCursor(40, 25);
|
||||
ssd1306_WriteString("232", Font_16x26, White);
|
||||
|
||||
ssd1306_UpdateScreenArea(0, 18, 128, 46);
|
||||
}
|
||||
//二极菜单
|
||||
void Menu2_LTE()
|
||||
{
|
||||
ssd1306_FillArea(0, 18, 128, 46, Black);
|
||||
ssd1306_SetCursor(40, 25);
|
||||
ssd1306_WriteString("LTE", Font_16x26, White);
|
||||
ssd1306_UpdateScreenArea(0, 18, 128, 46);
|
||||
}
|
||||
//三极菜单
|
||||
void Menu3_IN()
|
||||
{
|
||||
|
||||
rt_tick_t tick_start, tick_end;
|
||||
|
||||
// tick_start = rt_tick_get();
|
||||
|
||||
while (1)
|
||||
{
|
||||
tick_end = rt_tick_get();
|
||||
if ((tick_end - tick_start) > 1000)
|
||||
{
|
||||
ssd1306_FillArea(0, 18, 128, 46, Black);
|
||||
//ssd1306_SetCursor(2, 20);
|
||||
//ssd1306_WriteString("000 000 000 000", Font_7x10, White);
|
||||
ssd1306_SetCursor(2, 28);
|
||||
rt_sprintf(buf, "%4d", get_IO_count(0));
|
||||
ssd1306_WriteString(buf, Font_6x8, White);
|
||||
|
||||
ssd1306_SetCursor(36, 28);
|
||||
rt_sprintf(buf, "%4d", get_IO_count(1));
|
||||
ssd1306_WriteString(buf, Font_6x8, White);
|
||||
|
||||
ssd1306_SetCursor(70, 28);
|
||||
rt_sprintf(buf, "%4d", get_IO_count(2));
|
||||
ssd1306_WriteString(buf, Font_6x8, White);
|
||||
|
||||
ssd1306_SetCursor(104, 28);
|
||||
rt_sprintf(buf, "%4d", get_IO_count(3));
|
||||
ssd1306_WriteString(buf, Font_6x8, White);
|
||||
|
||||
ssd1306_SetCursor(2, 48);
|
||||
rt_sprintf(buf, "%4d", get_IO_count(4));
|
||||
ssd1306_WriteString(buf, Font_6x8, White);
|
||||
|
||||
ssd1306_SetCursor(36, 48);
|
||||
rt_sprintf(buf, "%4d", get_IO_count(5));
|
||||
ssd1306_WriteString(buf, Font_6x8, White);
|
||||
|
||||
ssd1306_SetCursor(70, 48);
|
||||
rt_sprintf(buf, "%4d", get_IO_count(6));
|
||||
ssd1306_WriteString(buf, Font_6x8, White);
|
||||
|
||||
ssd1306_SetCursor(104, 48);
|
||||
rt_sprintf(buf, "%4d", get_IO_count(7));
|
||||
ssd1306_WriteString(buf, Font_6x8, White);
|
||||
|
||||
ssd1306_UpdateScreenArea(0, 18, 128, 46);
|
||||
tick_start = tick_end;
|
||||
}
|
||||
|
||||
rt_kprintf("3 in\n");
|
||||
if (!rt_pin_read(key_pins[2]))
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
//三极菜单
|
||||
void Menu3_OUT()
|
||||
{
|
||||
rt_tick_t tick_start, tick_end;
|
||||
|
||||
// tick_start = rt_tick_get();
|
||||
|
||||
while (1)
|
||||
{
|
||||
tick_end = rt_tick_get();
|
||||
if ((tick_end - tick_start) > 1000)
|
||||
{
|
||||
ssd1306_FillArea(0, 18, 128, 46, Black);
|
||||
|
||||
ssd1306_SetCursor(2, 28);
|
||||
rt_sprintf(buf, "%4d", get_IO_count(0));
|
||||
ssd1306_WriteString(buf, Font_6x8, White);
|
||||
|
||||
ssd1306_SetCursor(36, 28);
|
||||
rt_sprintf(buf, "%4d", get_IO_count(1));
|
||||
ssd1306_WriteString(buf, Font_6x8, White);
|
||||
|
||||
ssd1306_SetCursor(70, 28);
|
||||
rt_sprintf(buf, "%4d", get_IO_count(2));
|
||||
ssd1306_WriteString(buf, Font_6x8, White);
|
||||
|
||||
ssd1306_SetCursor(104, 28);
|
||||
rt_sprintf(buf, "%4d", get_IO_count(3));
|
||||
ssd1306_WriteString(buf, Font_6x8, White);
|
||||
|
||||
ssd1306_SetCursor(2, 48);
|
||||
rt_sprintf(buf, "%4d", get_IO_count(4));
|
||||
ssd1306_WriteString(buf, Font_6x8, White);
|
||||
|
||||
ssd1306_SetCursor(36, 48);
|
||||
rt_sprintf(buf, "%4d", get_IO_count(5));
|
||||
ssd1306_WriteString(buf, Font_6x8, White);
|
||||
|
||||
ssd1306_SetCursor(70, 48);
|
||||
rt_sprintf(buf, "%4d", get_IO_count(6));
|
||||
ssd1306_WriteString(buf, Font_6x8, White);
|
||||
|
||||
ssd1306_SetCursor(104, 48);
|
||||
rt_sprintf(buf, "%4d", get_IO_count(7));
|
||||
ssd1306_WriteString(buf, Font_6x8, White);
|
||||
|
||||
ssd1306_UpdateScreenArea(0, 18, 128, 46);
|
||||
tick_start = tick_end;
|
||||
}
|
||||
|
||||
rt_kprintf("3 in\n");
|
||||
if (!rt_pin_read(key_pins[2]))
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
//三极菜单
|
||||
void Menu3_485()
|
||||
{
|
||||
// char buf[4];
|
||||
ssd1306_FillArea(0, 18, 128, 46, Black);
|
||||
ssd1306_SetCursor(2, 20);
|
||||
ssd1306_WriteString("addr:", Font_7x10, White);
|
||||
ssd1306_SetCursor(55, 20);
|
||||
rt_sprintf(buf, "0x%2d", get_Modbus_Addr());
|
||||
ssd1306_WriteString(buf, Font_6x8, White);
|
||||
|
||||
ssd1306_SetCursor(2, 32);
|
||||
ssd1306_WriteString("reg:", Font_7x10, White);
|
||||
ssd1306_SetCursor(55, 32);
|
||||
rt_sprintf(buf, "0x%2d", get_Modbus_Reg_Addr());
|
||||
ssd1306_WriteString(buf, Font_6x8, White);
|
||||
|
||||
ssd1306_SetCursor(2, 44);
|
||||
ssd1306_WriteString("r_num:", Font_7x10, White);
|
||||
ssd1306_SetCursor(55, 44);
|
||||
rt_sprintf(buf, "0x%2d", get_Modbus_Reg_Num());
|
||||
ssd1306_WriteString(buf, Font_6x8, White);
|
||||
|
||||
ssd1306_UpdateScreenArea(0, 18, 128, 46);
|
||||
}
|
||||
//三极菜单
|
||||
void Menu3_232()
|
||||
{
|
||||
|
||||
ssd1306_FillArea(0, 18, 128, 46, Black);
|
||||
ssd1306_SetCursor(2, 25);
|
||||
ssd1306_WriteString("addr:", Font_7x10, White);
|
||||
|
||||
ssd1306_SetCursor(2, 40);
|
||||
ssd1306_WriteString("reg:", Font_7x10, White);
|
||||
|
||||
ssd1306_SetCursor(64, 25);
|
||||
ssd1306_WriteString("num:", Font_7x10, White);
|
||||
ssd1306_UpdateScreenArea(0, 18, 128, 46);
|
||||
}
|
||||
//三极菜单
|
||||
void Menu3_LTE()
|
||||
{
|
||||
|
||||
ssd1306_FillArea(0, 18, 128, 46, Black);
|
||||
|
||||
ssd1306_SetCursor(2, 20);
|
||||
ssd1306_WriteString("m_ip:", Font_7x10, White);
|
||||
ssd1306_SetCursor(40, 20);
|
||||
rt_sprintf(buf, "%s", get_MQTT_ADDR());
|
||||
ssd1306_WriteString(buf, Font_6x8, White);
|
||||
|
||||
ssd1306_SetCursor(2, 32);
|
||||
ssd1306_WriteString("mid:", Font_7x10, White);
|
||||
ssd1306_SetCursor(30, 32);
|
||||
rt_sprintf(buf, "%s", get_MQTT_CLI_ID());
|
||||
ssd1306_WriteString(buf, Font_6x8, White);
|
||||
|
||||
ssd1306_SetCursor(2, 44);
|
||||
ssd1306_WriteString("port:", Font_7x10, White);
|
||||
ssd1306_SetCursor(30, 44);
|
||||
rt_sprintf(buf, "%s", get_MQTT_PORT());
|
||||
ssd1306_WriteString(buf, Font_6x8, White);
|
||||
|
||||
ssd1306_UpdateScreenArea(0, 18, 128, 46);
|
||||
|
||||
}
|
||||
|
||||
//结构体数组 每个元素代表一个菜单项
|
||||
key_table menu_table[] = {
|
||||
//菜单界面函数 -- 一级界面
|
||||
{ 0, 5, 1, 0, 0, Menu_one }, //
|
||||
//功能界面函数 -- 二级界面
|
||||
{ 1, 0, 2, 0, 6, Menu2_IN }, //显示IO
|
||||
{ 2, 1, 3, 0, 7, Menu2_OUT }, //显示IO
|
||||
{ 3, 2, 4, 0, 8, Menu2_LTE }, //485
|
||||
{ 4, 3, 5, 0, 9, Menu2_485 }, //232
|
||||
{ 5, 4, 0, 0, 10, Menu2_232 }, //LTE
|
||||
//功能查看界面函数 -- 三级界面
|
||||
{ 6, 6, 6, 1, 1, Menu3_IN }, //
|
||||
{ 7, 7, 7, 2, 2, Menu3_OUT }, //
|
||||
{ 8, 8, 8, 3, 3, Menu3_LTE }, //
|
||||
{ 9, 9, 9, 4, 4, Menu3_485 }, //
|
||||
{ 10, 10, 10, 5, 5, Menu3_232 }, //
|
||||
};
|
||||
|
||||
//获取按键值
|
||||
rt_uint8_t key_Value(void)
|
||||
{
|
||||
|
||||
for (rt_uint8_t var = 0; var < 4; ++var)
|
||||
{
|
||||
if (rt_pin_read(key_pins[var]) == PIN_LOW)
|
||||
{
|
||||
rt_kprintf("%d\n", var);
|
||||
return var + 1;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
//菜单页面管理
|
||||
void oled_menu()
|
||||
{
|
||||
if (menu_index == 0)
|
||||
{
|
||||
if (!cnt)
|
||||
{
|
||||
menu = menu_table[menu_index].menu;
|
||||
(*menu)();
|
||||
cnt = 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (get_LTE_re())
|
||||
{
|
||||
Menu_NO_LTE();
|
||||
}
|
||||
else
|
||||
{
|
||||
Menu_LTE();
|
||||
}
|
||||
|
||||
if (get_L_MQTT_re())
|
||||
{
|
||||
Menu_NO_MQTT();
|
||||
}
|
||||
else
|
||||
{
|
||||
Menu_MQTT();
|
||||
}
|
||||
|
||||
key = key_Value();
|
||||
|
||||
switch (key)
|
||||
{
|
||||
case 1:
|
||||
menu_index = menu_table[menu_index].up; // 向上翻
|
||||
break;
|
||||
case 2:
|
||||
menu_index = menu_table[menu_index].down; // 向下翻
|
||||
break;
|
||||
case 3:
|
||||
menu_index = menu_table[menu_index].back; // 返回
|
||||
break;
|
||||
case 4:
|
||||
menu_index = menu_table[menu_index].enter; // 确认
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
while (!rt_pin_read(key_pins[key - 1]))
|
||||
{
|
||||
}
|
||||
|
||||
menu = menu_table[menu_index].menu;
|
||||
rt_kprintf("index %d\n", menu_index);
|
||||
(*menu)();
|
||||
}
|
||||
|
||||
//初始化
|
||||
void oled_init()
|
||||
{
|
||||
for (rt_uint8_t var = 0; var < 4; var++)
|
||||
{
|
||||
rt_pin_mode(key_pins[var], PIN_MODE_INPUT_PULLUP);
|
||||
}
|
||||
|
||||
ssd1306_Init();
|
||||
//ssd1306_TestFonts();
|
||||
Menu_index();
|
||||
rt_thread_mdelay(1000);
|
||||
}
|
||||
|
||||
51
applications/OLED/gui.h
Normal file
51
applications/OLED/gui.h
Normal file
@ -0,0 +1,51 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-05-09 LJ the first version
|
||||
*/
|
||||
#ifndef APPLICATIONS_OLED_GUI_H_
|
||||
#define APPLICATIONS_OLED_GUI_H_
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <board.h>
|
||||
|
||||
#include <string.h>
|
||||
#include <stdio.h>
|
||||
#include "ssd1306.h"
|
||||
#include <inout.h>
|
||||
#include <LTE.h>
|
||||
#include <mb85rs.h>
|
||||
#include <gui.h>
|
||||
#include <modbus_rtu.h>
|
||||
#include <mqtt.h>
|
||||
#include <adc.h>
|
||||
#include <inout.h>
|
||||
|
||||
typedef struct
|
||||
{
|
||||
rt_uint8_t index;
|
||||
rt_uint8_t up; //上键
|
||||
rt_uint8_t down; //下键
|
||||
rt_uint8_t back; //返回键
|
||||
rt_uint8_t enter; //确认键
|
||||
void (*menu)();
|
||||
} key_table;
|
||||
|
||||
#define KEY_previous GET_PIN(C, 14)//上一页
|
||||
#define KEY_next GET_PIN(C, 13)//下一页
|
||||
#define KEY_back GET_PIN(B, 9)//返回
|
||||
#define KEY_enter GET_PIN(B, 8)//确认
|
||||
|
||||
//初始化
|
||||
void oled_init();
|
||||
|
||||
//菜单页面管理
|
||||
void oled_menu();
|
||||
|
||||
|
||||
#endif /* APPLICATIONS_OLED_GUI_H_ */
|
||||
593
applications/config/console.c
Normal file
593
applications/config/console.c
Normal file
@ -0,0 +1,593 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-04-17 lijian the first version
|
||||
*/
|
||||
|
||||
#include <console.h>
|
||||
|
||||
/**
|
||||
* 十六进制转十进制
|
||||
* @param c
|
||||
* @return
|
||||
*/
|
||||
rt_uint8_t hex_char_to_value(char c)
|
||||
{
|
||||
if (c >= '0' && c <= '9')
|
||||
{
|
||||
return c - '0';
|
||||
}
|
||||
else if (c >= 'A' && c <= 'F')
|
||||
{
|
||||
return 10 + (c - 'A');
|
||||
}
|
||||
else if (c >= 'a' && c <= 'f')
|
||||
{
|
||||
return 10 + (c - 'a');
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* 读取配置
|
||||
*/
|
||||
void read_config()
|
||||
{
|
||||
// char wifi_ssid[9];
|
||||
// char wifi_pwd[16];
|
||||
char mqtt_addr[16];
|
||||
char mqtt_port[9];
|
||||
char mqtt_cli_id[16];
|
||||
char mqtt_username[16];
|
||||
char mqtt_pwd[16];
|
||||
char modbus_addr[3];
|
||||
char modbus_reg_addr[3];
|
||||
char modbus_reg_num[3];
|
||||
// char speed_num[3];
|
||||
// char need_num[3];
|
||||
// char base[1];
|
||||
// char wireless[1];
|
||||
char adc_1[2];
|
||||
char adc_2[2];
|
||||
|
||||
rt_uint8_t err[10];
|
||||
|
||||
// err[0] = mb85rs_read_bytes(i2c_bus, 0, (rt_uint8_t *) base, sizeof(base));
|
||||
// err[1] = mb85rs_read_bytes(i2c_bus, 1, (rt_uint8_t *) wireless, sizeof(wireless));
|
||||
//
|
||||
// //2,3预留
|
||||
// err[2] = mb85rs_read_bytes(i2c_bus, 4, (rt_uint8_t *) wifi_ssid, sizeof(wifi_ssid));
|
||||
// err[3] = mb85rs_read_bytes(i2c_bus, 13, (rt_uint8_t *) wifi_pwd, sizeof(wifi_pwd));
|
||||
|
||||
err[0] = mb85rs_read_bytes(8, (rt_uint8_t *) mqtt_addr, sizeof(mqtt_addr));
|
||||
err[1] = mb85rs_read_bytes(24, (rt_uint8_t *) mqtt_port, sizeof(mqtt_port));
|
||||
err[2] = mb85rs_read_bytes(40, (rt_uint8_t *) mqtt_cli_id, sizeof(mqtt_cli_id));
|
||||
err[3] = mb85rs_read_bytes(56, (rt_uint8_t *) mqtt_username, sizeof(mqtt_username));
|
||||
err[4] = mb85rs_read_bytes(72, (rt_uint8_t *) mqtt_pwd, sizeof(mqtt_pwd));
|
||||
|
||||
err[5] = mb85rs_read_bytes(88, (rt_uint8_t *) modbus_addr, sizeof(modbus_addr));
|
||||
err[6] = mb85rs_read_bytes(91, (rt_uint8_t *) modbus_reg_addr, sizeof(modbus_reg_addr));
|
||||
err[7] = mb85rs_read_bytes(94, (rt_uint8_t *) modbus_reg_num, sizeof(modbus_reg_num));
|
||||
|
||||
err[8] = mb85rs_read_bytes(97, (rt_uint8_t *) adc_1, sizeof(adc_1));
|
||||
err[9] = mb85rs_read_bytes(99, (rt_uint8_t *) adc_2, sizeof(adc_2));
|
||||
// err[12] = mb85rs_read_bytes(i2c_bus, 98, (rt_uint8_t *) speed_num, sizeof(speed_num));
|
||||
// err[13] = mb85rs_read_bytes(i2c_bus, 101, (rt_uint8_t *) need_num, sizeof(need_num));
|
||||
|
||||
|
||||
rt_kprintf("\r\n");
|
||||
for (rt_uint8_t var = 0; var < 10; var++)
|
||||
{
|
||||
if (err[var] != RT_EOK)
|
||||
{
|
||||
rt_kprintf(" Read Fail ! Please Check Hardware ! is in %d config \r\n", err[var]);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
rt_kprintf(" Read Config Successes ! \r\n");
|
||||
|
||||
// //hw_config
|
||||
// set_hw_base(base[0] - '0');
|
||||
// rt_kprintf(" Base : %d \r\n", get_hw_base());
|
||||
// set_hw_wireless(wireless[0] - '0');
|
||||
// rt_uint8_t wirel_temp = get_hw_wireless();
|
||||
// rt_kprintf(" wireless : %d \r\n", wirel_temp);
|
||||
// //设置不同设备使用标准位
|
||||
// if(wirel_temp == 1){
|
||||
// set_WIFI_Key(1);
|
||||
// } else if(wirel_temp==2){
|
||||
// set_ZigBee_Key(1);
|
||||
// } else if(wirel_temp==3){
|
||||
// set_LTE_Key(1);
|
||||
// }
|
||||
//
|
||||
// //wifi config
|
||||
// set_WIFI_SSID(wifi_ssid);
|
||||
// rt_kprintf(" wifi_ssid : %s \r\n", get_WIFI_SSID());
|
||||
// set_WIFI_PWD(wifi_pwd);
|
||||
// rt_kprintf(" wifi_pwd : %s \r\n", get_WIFI_PWD());
|
||||
|
||||
//mqtt config
|
||||
set_MQTT_ADDR(mqtt_addr);
|
||||
rt_kprintf(" mqtt_addr : %s \r\n", get_MQTT_ADDR());
|
||||
set_MQTT_PORT(mqtt_port);
|
||||
rt_kprintf(" mqtt_port : %s \r\n", get_MQTT_PORT());
|
||||
set_MQTT_CLI_ID(mqtt_cli_id);
|
||||
rt_kprintf(" mqtt_cli_id : %s \r\n", get_MQTT_CLI_ID());
|
||||
set_MQTT_USERNAME(mqtt_username);
|
||||
rt_kprintf(" mqtt_username : %s \r\n", get_MQTT_USERNAME());
|
||||
set_MQTT_PWD(mqtt_pwd);
|
||||
rt_kprintf(" mqtt_pwd : %s \r\n", get_MQTT_PWD());
|
||||
|
||||
//modbus config
|
||||
rt_uint8_t high_temp;
|
||||
rt_uint8_t low_temp;
|
||||
high_temp = hex_char_to_value(modbus_addr[0]);
|
||||
low_temp = hex_char_to_value(modbus_addr[1]);
|
||||
set_Modbus_Addr((high_temp << 4) | low_temp);
|
||||
rt_kprintf(" modbus_addr : 0x%X\r\n", get_Modbus_Addr());
|
||||
|
||||
high_temp = hex_char_to_value(modbus_reg_addr[0]);
|
||||
low_temp = hex_char_to_value(modbus_reg_addr[1]);
|
||||
set_Modbus_Reg_Addr((high_temp << 4) | low_temp);
|
||||
rt_kprintf(" modbus_reg_addr : 0x%X\r\n", get_Modbus_Reg_Addr());
|
||||
|
||||
high_temp = hex_char_to_value(modbus_reg_num[0]);
|
||||
low_temp = hex_char_to_value(modbus_reg_num[1]);
|
||||
set_Modbus_Reg_Num((high_temp << 4) | low_temp);
|
||||
rt_kprintf(" modbus_reg_num : 0x%X\r\n", get_Modbus_Reg_Num());
|
||||
|
||||
high_temp = hex_char_to_value(adc_1[0]);
|
||||
set_ADC1_mode(high_temp);
|
||||
rt_kprintf(" ADC1 mode (1:0-10V 2:4-20ma) : %d\r\n", get_ADC1_mode());
|
||||
|
||||
high_temp = hex_char_to_value(adc_2[0]);
|
||||
set_ADC2_mode(high_temp);
|
||||
rt_kprintf(" ADC2 mode (1:0-10V 2:4-20ma) : %d\r\n", get_ADC2_mode());
|
||||
|
||||
// //IO
|
||||
// set_Flag_Speed_IO((((speed_num[0] - '0') * 10) + (speed_num[1] - '0'))-1);
|
||||
// rt_kprintf(" speed io: %d\r\n", get_Flag_Speed_IO()+1);
|
||||
// set_Flag_Needle_IO((((need_num[0] - '0') * 10) + (need_num[1] - '0'))-1);
|
||||
// rt_kprintf(" needl io: %d\r\n ", get_Flag_Needle_IO()+1);
|
||||
|
||||
}
|
||||
|
||||
//配置函数
|
||||
void change_config()
|
||||
{
|
||||
//char buffer[128]; // 输入缓冲区
|
||||
rt_uint8_t var = 0;
|
||||
// char wifi_ssid[9];
|
||||
// char wifi_pwd[16];
|
||||
char mqtt_addr[16];
|
||||
char mqtt_port[9];
|
||||
char mqtt_cli_id[16];
|
||||
char mqtt_username[16];
|
||||
char mqtt_pwd[16];
|
||||
char modbus_addr[3];
|
||||
char modbus_reg_addr[3];
|
||||
char modbus_reg_num[3];
|
||||
// char speed_num[3];
|
||||
// char need_num[3];
|
||||
// char base[1];
|
||||
// char wireless[1];
|
||||
// char mqtt_pub_topic[9];
|
||||
char adc_1[2];
|
||||
char adc_2[2];
|
||||
|
||||
//退格删除的实现
|
||||
// while (var < sizeof(ch) - 1)
|
||||
// {
|
||||
// ch[var] = finsh_getchar();
|
||||
//
|
||||
// if (ch[var] == '\r' || ch[var] == '\n')
|
||||
// {
|
||||
// rt_kprintf("\n");
|
||||
// break;
|
||||
// }
|
||||
//
|
||||
// if (ch[var] == '\b')
|
||||
// {
|
||||
// if (var > 0)
|
||||
// {
|
||||
// rt_kprintf("\b \b");
|
||||
// var--;
|
||||
// continue;
|
||||
// }
|
||||
// else
|
||||
// {
|
||||
// continue;
|
||||
// }
|
||||
// }
|
||||
//
|
||||
// rt_kprintf("%c", ch[var]);
|
||||
// var++;
|
||||
// }
|
||||
|
||||
rt_kprintf("-----------------------\r\n");
|
||||
rt_kprintf(" GetonAgain \r\n");
|
||||
rt_kprintf(" GOATS \r\n");
|
||||
rt_kprintf(" CAMS-DATU \r\n");
|
||||
rt_kprintf(" Setting Config \r\n");
|
||||
rt_kprintf("-----------------------\r\n");
|
||||
|
||||
// //Base
|
||||
rt_kprintf("\r\n");
|
||||
// rt_kprintf("-----------------------\r\n");
|
||||
// rt_kprintf(" Set HardWare config : \r\n");
|
||||
// rt_kprintf(" Base Plate (1.IO&485&4G 2. 3. ) : ");
|
||||
// base[0] = finsh_getchar();
|
||||
// rt_kprintf("%c", base[0]);
|
||||
// rt_kprintf("\r\n");
|
||||
// rt_kprintf(" base: %c \r\n", base[0]);
|
||||
//
|
||||
// //wireless
|
||||
// rt_kprintf("\r\n");
|
||||
// rt_kprintf(" wireless (1.WIFI 2. ZigBee 3. 4G) : ");
|
||||
// wireless[0] = finsh_getchar();
|
||||
// rt_kprintf("%c", wireless[0]);
|
||||
// rt_kprintf("\r\n");
|
||||
// rt_kprintf(" wireless: %c \r\n", wireless[0]);
|
||||
//
|
||||
// //Set WIFI
|
||||
// rt_kprintf("\r\n");
|
||||
// rt_kprintf("-----------------------\r\n");
|
||||
// rt_kprintf(" Set WIFI (Length:16) \r\n");
|
||||
//
|
||||
// //WIFI SSID
|
||||
// rt_kprintf(" WIFI SSID: ");
|
||||
// for (var = 0; var < 8; var++)
|
||||
// {
|
||||
// wifi_ssid[var] = finsh_getchar();
|
||||
// rt_kprintf("%c", wifi_ssid[var]);
|
||||
// // rt_kprintf("%c %d\r\n", wifi_ssid[var] , var);
|
||||
//
|
||||
// // 检查是否是回车或换行符
|
||||
// if (wifi_ssid[var] == '\r' || wifi_ssid[var] == '\n')
|
||||
// {
|
||||
// break;
|
||||
// }
|
||||
// }
|
||||
// wifi_ssid[var] = '\0';
|
||||
// // rt_kprintf("%c %d\r\n", wifi_ssid[var] , var);
|
||||
// rt_kprintf(" WIFI SSID: %s num: %d\r\n", wifi_ssid, var);
|
||||
//
|
||||
// // WIFI_PWD
|
||||
// rt_kprintf(" WIFI_PWD: ");
|
||||
// for (var = 0; var < 16; var++)
|
||||
// {
|
||||
// wifi_pwd[var] = finsh_getchar();
|
||||
// rt_kprintf("%c", wifi_pwd[var]);
|
||||
//
|
||||
// // 检查是否是回车或换行符
|
||||
// if (wifi_pwd[var] == '\r' || wifi_pwd[var] == '\n')
|
||||
// {
|
||||
// break;
|
||||
// }
|
||||
// }
|
||||
// wifi_pwd[var] = '\0';
|
||||
// rt_kprintf("\r\n");
|
||||
// rt_kprintf(" WIFI PWD: %s num: %d\r\n", wifi_pwd, var);
|
||||
// rt_kprintf("\r\n");
|
||||
//
|
||||
// rt_kprintf("\r\n");
|
||||
// rt_kprintf("-----------------------\r\n");
|
||||
|
||||
// Set MQTT
|
||||
rt_kprintf(" Set MQTT (Length:16)\r\n");
|
||||
|
||||
//MQTT_ADDR
|
||||
rt_kprintf(" MQTT_ADDR: ");
|
||||
for (var = 0; var < 16; var++)
|
||||
{
|
||||
mqtt_addr[var] = finsh_getchar();
|
||||
rt_kprintf("%c", mqtt_addr[var]);
|
||||
|
||||
// 检查是否是回车或换行符
|
||||
if (mqtt_addr[var] == '\r' || mqtt_addr[var] == '\n')
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
mqtt_addr[var] = '\0';
|
||||
rt_kprintf("\r\n");
|
||||
rt_kprintf(" MQTT_ADDR: %s num: %d\r\n", mqtt_addr, var);
|
||||
|
||||
//MQTT_PORT
|
||||
rt_kprintf(" MQTT_PORT: ");
|
||||
for (var = 0; var < 8; var++)
|
||||
{
|
||||
mqtt_port[var] = finsh_getchar();
|
||||
rt_kprintf("%c", mqtt_port[var]);
|
||||
|
||||
// 检查是否是回车或换行符
|
||||
if (mqtt_port[var] == '\r' || mqtt_port[var] == '\n')
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
mqtt_port[var] = '\0';
|
||||
rt_kprintf("\r\n");
|
||||
rt_kprintf(" MQTT_PORT: %s num: %d\r\n", mqtt_port, var);
|
||||
|
||||
//MQTT_CLI_ID
|
||||
rt_kprintf(" MQTT_CLI_ID: ");
|
||||
for (var = 0; var < 16; var++)
|
||||
{
|
||||
mqtt_cli_id[var] = finsh_getchar();
|
||||
rt_kprintf("%c", mqtt_cli_id[var]);
|
||||
|
||||
// 检查是否是回车或换行符
|
||||
if (mqtt_cli_id[var] == '\r' || mqtt_cli_id[var] == '\n')
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
mqtt_cli_id[var] = '\0';
|
||||
rt_kprintf("\r\n");
|
||||
rt_kprintf(" MQTT_CLI_ID: %s num: %d\r\n", mqtt_cli_id, var);
|
||||
|
||||
//MQTT_USERNAME
|
||||
rt_kprintf(" MQTT_USERNAME: ");
|
||||
for (var = 0; var < 16; var++)
|
||||
{
|
||||
mqtt_username[var] = finsh_getchar();
|
||||
rt_kprintf("%c", mqtt_username[var]);
|
||||
|
||||
// 检查是否是回车或换行符
|
||||
if (mqtt_username[var] == '\r' || mqtt_username[var] == '\n')
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
mqtt_username[var] = '\0';
|
||||
rt_kprintf("\r\n");
|
||||
rt_kprintf(" MQTT_USERNAME: %s num: %d\r\n", mqtt_username, var);
|
||||
|
||||
//MQTT_PWD
|
||||
rt_kprintf(" MQTT_PWD: ");
|
||||
for (var = 0; var < 16; var++)
|
||||
{
|
||||
mqtt_pwd[var] = finsh_getchar();
|
||||
rt_kprintf("%c", mqtt_pwd[var]);
|
||||
|
||||
// 检查是否是回车或换行符
|
||||
if (mqtt_pwd[var] == '\r' || mqtt_pwd[var] == '\n')
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
mqtt_pwd[var] = '\0';
|
||||
rt_kprintf("\r\n");
|
||||
rt_kprintf(" MQTT_PWD: %s %d num: %d\r\n", mqtt_pwd, mqtt_pwd[0], var);
|
||||
|
||||
rt_kprintf("\r\n");
|
||||
// //mqtt_pub_topic
|
||||
// rt_kprintf(" MQTT_TOPIC: ");
|
||||
// for (var = 0; var < 8; var++)
|
||||
// {
|
||||
// mqtt_pub_topic[var] = finsh_getchar();
|
||||
// rt_kprintf("%c", mqtt_pub_topic[var]);
|
||||
//
|
||||
// // 检查是否是回车或换行符
|
||||
// if (mqtt_pub_topic[var] == '\r' || mqtt_pub_topic[var] == '\n')
|
||||
// {
|
||||
// break;
|
||||
// }
|
||||
// }
|
||||
// mqtt_pub_topic[var] = '\0';
|
||||
// rt_kprintf("\r\n");
|
||||
// rt_kprintf(" MQTT_TOPIC: %s num: %d\r\n", mqtt_pub_topic, var);
|
||||
// rt_kprintf("\r\n");
|
||||
|
||||
rt_kprintf("\r\n");
|
||||
rt_kprintf("-----------------------\r\n");
|
||||
|
||||
// //Set IO
|
||||
// rt_kprintf(" Set IO (Length:2 eg: 01 12)\r\n");
|
||||
//
|
||||
// //Set Speed
|
||||
// rt_kprintf(" Speed IO : ");
|
||||
// for (var = 0; var < 2; var++)
|
||||
// {
|
||||
// speed_num[var] = finsh_getchar();
|
||||
// rt_kprintf("%c", speed_num[var]);
|
||||
//
|
||||
// // 检查是否是回车或换行符
|
||||
// if (speed_num[var] == '\r' || speed_num[var] == '\n')
|
||||
// {
|
||||
// break;
|
||||
// }
|
||||
// }
|
||||
// speed_num[var] = '\0';
|
||||
// rt_kprintf("\r\n");
|
||||
// rt_kprintf(" Speed IO: %s num: %d\r\n", speed_num, var);
|
||||
//
|
||||
// //Set NeedleCount
|
||||
// rt_kprintf(" Needle IO : ");
|
||||
// for (var = 0; var < 2; var++)
|
||||
// {
|
||||
// need_num[var] = finsh_getchar();
|
||||
// rt_kprintf("%c", need_num[var]);
|
||||
//
|
||||
// // 检查是否是回车或换行符
|
||||
// if (need_num[var] == '\r' || need_num[var] == '\n')
|
||||
// {
|
||||
// break;
|
||||
// }
|
||||
// }
|
||||
// need_num[var] = '\0';
|
||||
// rt_kprintf("\r\n");
|
||||
// rt_kprintf(" Needle IO: %s num: %d\r\n", need_num, var);
|
||||
// rt_kprintf("\r\n");
|
||||
//
|
||||
// rt_kprintf("\r\n");
|
||||
// rt_kprintf("-----------------------\r\n");
|
||||
//Set Modbus
|
||||
rt_kprintf(" Set Modbus (Length:2 eg: AA 30)\r\n");
|
||||
|
||||
//Set Modbus_addr
|
||||
rt_kprintf(" Modbus_addr : ");
|
||||
for (var = 0; var < 2; var++)
|
||||
{
|
||||
modbus_addr[var] = finsh_getchar();
|
||||
rt_kprintf("%c", modbus_addr[var]);
|
||||
|
||||
// 检查是否是回车或换行符
|
||||
if (modbus_addr[var] == '\r' || modbus_addr[var] == '\n')
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
modbus_addr[var] = '\0';
|
||||
rt_kprintf("\r\n");
|
||||
rt_kprintf(" Modbus_addr: %s num: %d\r\n", modbus_addr, var);
|
||||
|
||||
//Set Modbus_reg_addr
|
||||
rt_kprintf(" Modbus_reg_addr : ");
|
||||
for (var = 0; var < 2; var++)
|
||||
{
|
||||
modbus_reg_addr[var] = finsh_getchar();
|
||||
rt_kprintf("%c", modbus_reg_addr[var]);
|
||||
|
||||
// 检查是否是回车或换行符
|
||||
if (modbus_reg_addr[var] == '\r' || modbus_reg_addr[var] == '\n')
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
modbus_reg_addr[var] = '\0';
|
||||
rt_kprintf("\r\n");
|
||||
rt_kprintf(" Modbus_reg_addr: %s num: %d\r\n", modbus_reg_addr, var);
|
||||
|
||||
//Set Modbus_reg_num
|
||||
rt_kprintf(" Modbus_reg_num : ");
|
||||
for (var = 0; var < 2; var++)
|
||||
{
|
||||
modbus_reg_num[var] = finsh_getchar();
|
||||
rt_kprintf("%c", modbus_reg_num[var]);
|
||||
|
||||
// 检查是否是回车或换行符
|
||||
if (modbus_reg_num[var] == '\r' || modbus_reg_num[var] == '\n')
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
modbus_reg_num[var] = '\0';
|
||||
rt_kprintf("\r\n");
|
||||
rt_kprintf(" Modbus_reg_num: %s num: %d\r\n", modbus_reg_num, var);
|
||||
|
||||
rt_kprintf("\r\n");
|
||||
|
||||
rt_kprintf("\r\n");
|
||||
rt_kprintf("-----------------------\r\n");
|
||||
|
||||
//ADC
|
||||
rt_kprintf("\r\n");
|
||||
rt_kprintf(" Set ADC (1:0-10V 2:4-20ma) : \r\n");
|
||||
rt_kprintf(" ADC1_IN0 : ");
|
||||
adc_1[0] = finsh_getchar();
|
||||
rt_kprintf("%c\n", adc_1[0]);
|
||||
adc_1[1] = '\0';
|
||||
rt_kprintf(" ADC_1: %c \r\n", adc_1[0]);
|
||||
rt_kprintf("\r\n");
|
||||
|
||||
rt_kprintf("\r\n");
|
||||
rt_kprintf(" ADC2_IN4 : ");
|
||||
adc_2[0] = finsh_getchar();
|
||||
rt_kprintf("%c\n", adc_2[0]);
|
||||
adc_2[1] = '\0';
|
||||
rt_kprintf(" ADC_2: %c \r\n", adc_2[0]);
|
||||
rt_kprintf("\r\n");
|
||||
|
||||
rt_kprintf("-----------------------\r\n");
|
||||
rt_kprintf("\r\n");
|
||||
|
||||
//SAVE
|
||||
rt_kprintf(" Save Setting ? y/n: ");
|
||||
char ch = finsh_getchar();
|
||||
rt_kprintf("%c", ch);
|
||||
|
||||
if (ch == 'y')
|
||||
{
|
||||
rt_kprintf("\r\n");
|
||||
rt_kprintf(" please wait, Saving ...... \r\n");
|
||||
|
||||
rt_uint8_t err[10];
|
||||
// err[0] = mb85rs_write_bytes(0, (rt_uint8_t *)base, sizeof(base));
|
||||
// err[1] = mb85rs_write_bytes(1, (rt_uint8_t *)wireless, sizeof(wireless));
|
||||
//
|
||||
// //2,3预留
|
||||
// err[2] = mb85rs_write_bytes(4, (rt_uint8_t *)wifi_ssid, sizeof(wifi_ssid));
|
||||
// err[3] = mb85rs_write_bytes(13, (rt_uint8_t *)wifi_pwd, sizeof(wifi_pwd));
|
||||
|
||||
err[0] = mb85rs_write_bytes(8, (rt_uint8_t *) mqtt_addr, sizeof(mqtt_addr));
|
||||
err[1] = mb85rs_write_bytes(24, (rt_uint8_t *) mqtt_port, sizeof(mqtt_port));
|
||||
err[2] = mb85rs_write_bytes(40, (rt_uint8_t *) mqtt_cli_id, sizeof(mqtt_cli_id));
|
||||
err[3] = mb85rs_write_bytes(56, (rt_uint8_t *) mqtt_username, sizeof(mqtt_username));
|
||||
err[4] = mb85rs_write_bytes(72, (rt_uint8_t *) mqtt_pwd, sizeof(mqtt_pwd));
|
||||
|
||||
err[5] = mb85rs_write_bytes(88, (rt_uint8_t *) modbus_addr, sizeof(modbus_addr));
|
||||
err[6] = mb85rs_write_bytes(91, (rt_uint8_t *) modbus_reg_addr, sizeof(modbus_reg_addr));
|
||||
err[7] = mb85rs_write_bytes(94, (rt_uint8_t *) modbus_reg_num, sizeof(modbus_reg_num));
|
||||
|
||||
err[8] = mb85rs_write_bytes(97, (rt_uint8_t *) adc_1, sizeof(adc_1));
|
||||
err[9] = mb85rs_write_bytes(99, (rt_uint8_t *) adc_2, sizeof(adc_2));
|
||||
|
||||
// err[12] = mb85rs_write_bytes(98, (rt_uint8_t *)speed_num, sizeof(speed_num));
|
||||
// err[13] = mb85rs_write_bytes(101, (rt_uint8_t *)need_num, sizeof(need_num));
|
||||
|
||||
for (rt_uint8_t var = 0; var < 10; var++)
|
||||
{
|
||||
if (err[var] != RT_EOK)
|
||||
{
|
||||
rt_kprintf(" Config Save Fail ! Please Check Hardware ! is in %d config \r\n", err[var]);
|
||||
return;
|
||||
}
|
||||
}
|
||||
rt_kprintf(" Config Save Successes ! Please Reboot !\r\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("\r\n");
|
||||
rt_kprintf("switch no is exit \r\n");
|
||||
}
|
||||
rt_kprintf("\r\n");
|
||||
}
|
||||
|
||||
void log_modbus()
|
||||
{
|
||||
set_modbus_log(1);
|
||||
}
|
||||
|
||||
void log_lte()
|
||||
{
|
||||
set_LTE_log(1);
|
||||
set_mqtt_log(1);
|
||||
}
|
||||
|
||||
void log_adc()
|
||||
{
|
||||
set_ADC_log(1);
|
||||
}
|
||||
|
||||
void no_log()
|
||||
{
|
||||
|
||||
set_modbus_log(0);
|
||||
set_LTE_log(0);
|
||||
set_mqtt_log(0);
|
||||
set_ADC_log(0);
|
||||
}
|
||||
|
||||
MSH_CMD_EXPORT(change_config, save to flash);
|
||||
MSH_CMD_EXPORT(log_modbus, view_log to console);
|
||||
MSH_CMD_EXPORT(log_lte, view_log to console);
|
||||
MSH_CMD_EXPORT(log_adc, view_log to console);
|
||||
MSH_CMD_EXPORT(no_log, no_log to console);
|
||||
25
applications/config/console.h
Normal file
25
applications/config/console.h
Normal file
@ -0,0 +1,25 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-04-17 GOATS the first version
|
||||
*/
|
||||
#ifndef APPLICATIONS_CONFIG_CONSOLE_H_
|
||||
#define APPLICATIONS_CONFIG_CONSOLE_H_
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <board.h>
|
||||
#include <rtdevice.h>
|
||||
#include <shell.h>
|
||||
#include <mb85rs.h>
|
||||
#include <adc.h>
|
||||
#include <mqtt.h>
|
||||
#include "modbus_rtu.h"
|
||||
|
||||
//读取配置
|
||||
void read_config();
|
||||
|
||||
#endif /* APPLICATIONS_CONFIG_CONSOLE_H_ */
|
||||
170
applications/fram/mb85rs.c
Normal file
170
applications/fram/mb85rs.c
Normal file
@ -0,0 +1,170 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-05-08 LJ the first version
|
||||
*/
|
||||
|
||||
#include <mb85rs.h>
|
||||
|
||||
#define SPI_DEVICE_NAME "spi3"
|
||||
#define MB85RS_SPI_DEVICE_NAME "spi30"
|
||||
struct rt_spi_device *spi_dev_mb85rs;
|
||||
|
||||
/**
|
||||
rt_uint8_t data_to_write[] = {0xAA, 0xBB, 0xCC, 0xDD};
|
||||
rt_uint16_t write_address = 0x0102;
|
||||
rt_uint16_t num_bytes_to_write = sizeof(data_to_write);
|
||||
rt_uint8_t read_buff[num_bytes_to_write];
|
||||
|
||||
// mb85rs_write_bytes(write_address, data_to_write, num_bytes_to_write);
|
||||
|
||||
mb85rs_read_bytes(write_address, read_buff, num_bytes_to_write);
|
||||
|
||||
for (int i = 0; i < num_bytes_to_write; i++) {
|
||||
rt_kprintf("%02X ", read_buff[i]);
|
||||
}
|
||||
rt_kprintf("\n");
|
||||
*/
|
||||
|
||||
//初始化
|
||||
void spi_flash_mb85rs_init(void)
|
||||
{
|
||||
struct rt_spi_configuration cfg;
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE()
|
||||
;
|
||||
|
||||
//先把设备挂载到总线上
|
||||
rt_hw_spi_device_attach(SPI_DEVICE_NAME, MB85RS_SPI_DEVICE_NAME, GPIOA, GPIO_PIN_15);
|
||||
//查找设备
|
||||
spi_dev_mb85rs = (struct rt_spi_device *) rt_device_find(MB85RS_SPI_DEVICE_NAME);
|
||||
|
||||
cfg.data_width = 8;
|
||||
cfg.mode = RT_SPI_MASTER | RT_SPI_MODE_0 | RT_SPI_MSB;
|
||||
cfg.max_hz = MB85RS_SPICLOCK; /* 20M */
|
||||
|
||||
rt_spi_configure(spi_dev_mb85rs, &cfg);
|
||||
}
|
||||
//INIT_COMPONENT_EXPORT(rt_hw_spi_flash_init);
|
||||
|
||||
/**
|
||||
* 读取ID
|
||||
*/
|
||||
void mb85rs_read_id()
|
||||
{
|
||||
|
||||
rt_uint8_t read_id = REG_READ_DEVICE_ID;
|
||||
rt_uint8_t id[5] = { 0 };
|
||||
|
||||
rt_spi_send_then_recv(spi_dev_mb85rs, &read_id, 1, id, 5);
|
||||
rt_kprintf("spi recv ID is:%x%x%x%x%x\n", id[0], id[1], id[2], id[3], id[4]);
|
||||
|
||||
rt_kprintf("Device ID: %02X %02X %02X %02X\n", id[0], id[1], id[2], id[3]);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* 写使能
|
||||
* @param select
|
||||
*/
|
||||
void mb85rs_write_enable(rt_uint8_t select)
|
||||
{
|
||||
rt_spi_send(spi_dev_mb85rs, &select, 1);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* 写单字节
|
||||
* @param write_addr
|
||||
* @param write_data
|
||||
*/
|
||||
rt_uint8_t mb85rs_write_byte(rt_uint16_t write_addr, rt_uint8_t write_data)
|
||||
{
|
||||
rt_uint8_t send_buff[3];
|
||||
rt_uint8_t err;
|
||||
mb85rs_write_enable(REG_WRITE_ENABLE);
|
||||
send_buff[0] = REG_WRITE_COMMAND;
|
||||
send_buff[1] = (write_addr >> 8) & 0xff;
|
||||
send_buff[2] = write_addr & 0xff;
|
||||
err = rt_spi_send_then_send(spi_dev_mb85rs, send_buff, 3, &write_data, 1);
|
||||
mb85rs_write_enable(REG_WRITE_DISABLE);
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* 写多字节
|
||||
* @param write_addr
|
||||
* @param write_buff
|
||||
* @param write_bytes
|
||||
*/
|
||||
rt_uint8_t mb85rs_write_bytes(rt_uint16_t write_addr, rt_uint8_t *write_buff, rt_uint16_t write_bytes)
|
||||
{
|
||||
rt_uint8_t send_buff[3];
|
||||
rt_uint8_t err;
|
||||
mb85rs_write_enable(REG_WRITE_ENABLE);
|
||||
send_buff[0] = REG_WRITE_COMMAND;
|
||||
send_buff[1] = (write_addr >> 8) & 0xff;
|
||||
send_buff[2] = write_addr & 0xff;
|
||||
err = rt_spi_send_then_send(spi_dev_mb85rs, send_buff, 3, write_buff, write_bytes);
|
||||
mb85rs_write_enable(REG_WRITE_DISABLE);
|
||||
return err;
|
||||
}
|
||||
|
||||
/**
|
||||
* 读取字节
|
||||
* @param read_addr
|
||||
* @param read_buff
|
||||
* @param read_bytes
|
||||
*/
|
||||
rt_uint8_t mb85rs_read_bytes(rt_uint16_t read_addr, rt_uint8_t *read_buff, rt_uint16_t read_bytes)
|
||||
{
|
||||
rt_uint8_t send_buff[3] = { 0 };
|
||||
send_buff[0] = REG_READ_COMMAND;
|
||||
send_buff[1] = (read_addr >> 8) & 0xff;
|
||||
send_buff[2] = read_addr & 0xff;
|
||||
return rt_spi_send_then_recv(spi_dev_mb85rs, send_buff, 3, read_buff, read_bytes);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
void mb85rs_read_device_id_write_status(rt_uint8_t write_data)
|
||||
{
|
||||
rt_uint8_t send_buff[2];
|
||||
|
||||
send_buff[0] = REG_WRITE_STATUS;
|
||||
send_buff[1] = write_data;
|
||||
rt_spi_send(spi_dev_mb85rs, send_buff, 2);
|
||||
}
|
||||
|
||||
/**
|
||||
* 读取状态
|
||||
* @return
|
||||
*/
|
||||
rt_uint8_t mb85rs_read_status(void)
|
||||
{
|
||||
rt_uint8_t read_status = 0, send_buff[1];
|
||||
|
||||
send_buff[0] = REG_READ_STATUS;
|
||||
rt_spi_send_then_recv(spi_dev_mb85rs, send_buff, 1, &read_status, 1);
|
||||
|
||||
return read_status;
|
||||
}
|
||||
|
||||
/**
|
||||
* 写状态寄存器
|
||||
* @param write_data
|
||||
*/
|
||||
void mb85rs_write_status(rt_uint8_t write_data)
|
||||
{
|
||||
rt_uint8_t send_buff[2];
|
||||
|
||||
send_buff[0] = REG_WRITE_STATUS;
|
||||
send_buff[1] = write_data;
|
||||
rt_spi_send(spi_dev_mb85rs, send_buff, 2);
|
||||
}
|
||||
|
||||
76
applications/fram/mb85rs.h
Normal file
76
applications/fram/mb85rs.h
Normal file
@ -0,0 +1,76 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-05-08 LJ the first version
|
||||
*/
|
||||
#ifndef APPLICATIONS_FRAM_MB85RS_H_
|
||||
#define APPLICATIONS_FRAM_MB85RS_H_
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <drv_common.h>
|
||||
#include <board.h>
|
||||
#include "drv_spi.h"
|
||||
//#include "drv_gpio.h"
|
||||
|
||||
//频率
|
||||
#define MB85RS_SPICLOCK 20000000
|
||||
|
||||
//MB85RS64命令
|
||||
#define REG_READ_COMMAND 0x03 //读数据
|
||||
#define REG_WRITE_COMMAND 0x02 //写数据
|
||||
#define REG_WRITE_ENABLE 0x06 //写使能
|
||||
#define REG_WRITE_DISABLE 0x04 //写失能
|
||||
#define REG_READ_STATUS 0x05 //读取状态寄存器
|
||||
#define REG_WRITE_STATUS 0x01 //写入状态寄存器
|
||||
#define REG_READ_DEVICE_ID 0x9F
|
||||
|
||||
//初始化
|
||||
void spi_flash_mb85rs_init(void);
|
||||
|
||||
/**
|
||||
* 读取ID
|
||||
*/
|
||||
void mb85rs_read_id();
|
||||
|
||||
|
||||
/**
|
||||
* 读取字节
|
||||
* @param read_addr
|
||||
* @param read_buff
|
||||
* @param read_bytes
|
||||
*/
|
||||
rt_uint8_t mb85rs_read_bytes(rt_uint16_t read_addr, rt_uint8_t *read_buff, rt_uint16_t read_bytes);
|
||||
|
||||
/**
|
||||
* 写多字节
|
||||
* @param write_addr
|
||||
* @param write_buff
|
||||
* @param write_bytes
|
||||
*/
|
||||
rt_uint8_t mb85rs_write_bytes(rt_uint16_t write_addr, rt_uint8_t *write_buff, rt_uint16_t write_bytes);
|
||||
|
||||
/**
|
||||
* 写使能
|
||||
* @param select
|
||||
*/
|
||||
void mb85rs_write_enable(rt_uint8_t select);
|
||||
|
||||
/**
|
||||
* 读取状态
|
||||
* @return
|
||||
*/
|
||||
rt_uint8_t mb85rs_read_status(void);
|
||||
|
||||
/**
|
||||
* 写状态寄存器
|
||||
* @param write_data
|
||||
*/
|
||||
void mb85rs_write_status(rt_uint8_t write_data);
|
||||
|
||||
|
||||
#endif /* APPLICATIONS_FRAM_MB85RS_H_ */
|
||||
172
applications/fram/w25q.c
Normal file
172
applications/fram/w25q.c
Normal file
@ -0,0 +1,172 @@
|
||||
///*
|
||||
// * Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
// *
|
||||
// * SPDX-License-Identifier: Apache-2.0
|
||||
// *
|
||||
// * Change Logs:
|
||||
// * Date Author Notes
|
||||
// * 2024-05-10 LJ the first version
|
||||
// */
|
||||
//#include <rtthread.h>
|
||||
//#include <rtdevice.h>
|
||||
//#include <drv_common.h>
|
||||
//#include "spi_flash.h"
|
||||
//#include "spi_flash_sfud.h"
|
||||
//#include "board.h"
|
||||
//#include "drv_spi.h"
|
||||
//
|
||||
//#define W25Q_SPI_DEVICE_NAME "spi30"
|
||||
//struct rt_spi_device *spi_dev;
|
||||
//
|
||||
//
|
||||
//int w25q_spi_device_init(void)
|
||||
//{
|
||||
//
|
||||
// struct rt_spi_configuration cfg;
|
||||
// __HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
//
|
||||
// rt_hw_spi_device_attach("spi3", W25Q_SPI_DEVICE_NAME, GPIOA, GPIO_PIN_15);
|
||||
// spi_dev = (struct rt_spi_device *) rt_device_find(W25Q_SPI_DEVICE_NAME);
|
||||
//
|
||||
// cfg.data_width=8;
|
||||
// cfg.mode=RT_SPI_MASTER|RT_SPI_MODE_0|RT_SPI_MSB;
|
||||
// cfg.max_hz= 20 * 1000 *1000; /* 20M */
|
||||
//
|
||||
// rt_spi_configure(spi_dev, &cfg);
|
||||
//
|
||||
//}
|
||||
//
|
||||
//void spi_w25q_ID(void)
|
||||
//{
|
||||
// rt_uint8_t w25x_read_id = 0x9f;
|
||||
// rt_uint8_t id[5] = {0};
|
||||
//
|
||||
// rt_spi_send_then_recv(spi_dev, &w25x_read_id, 1, id, 5);
|
||||
//
|
||||
// rt_kprintf("use rt_spi_send_then_recv() read w25q ID is:%x%x%x%x%x\n", id[0], id[1], id[2], id[3], id[4]);
|
||||
//
|
||||
//// struct rt_spi_message msg1, msg2;
|
||||
////
|
||||
//// msg1.send_buf = &w25x_read_id;
|
||||
//// msg1.recv_buf = RT_NULL;
|
||||
//// msg1.length = 1;
|
||||
//// msg1.cs_take = 1;
|
||||
//// msg1.cs_release = 0;
|
||||
//// msg1.next = &msg2;
|
||||
////
|
||||
//// msg2.send_buf = RT_NULL;
|
||||
//// msg2.recv_buf = id;
|
||||
//// msg2.length = 5;
|
||||
//// msg2.cs_take = 0;
|
||||
//// msg2.cs_release = 1;
|
||||
//// msg2.next = RT_NULL;
|
||||
////
|
||||
//// rt_spi_transfer_message(spi_dev, &msg1);
|
||||
//// rt_kprintf("use rt_spi_transfer_message() read w25q ID is:%x%x\n", id[3], id[4]);
|
||||
//
|
||||
//}
|
||||
|
||||
//#define W25Q_SPI_DEVICE_NAME "spi30"
|
||||
////extern SPI_HandleTypeDef hspi3;
|
||||
//static int rt_hw_spi_flash_init(void)
|
||||
//{
|
||||
// struct rt_spi_device *spi_device = RT_NULL;
|
||||
//
|
||||
// spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
|
||||
// if(RT_NULL == spi_device)
|
||||
// {
|
||||
// rt_kprintf("Failed to malloc the spi device.");
|
||||
// return -RT_ENOMEM;
|
||||
// }
|
||||
// if (RT_EOK != rt_spi_bus_attach_device_cspin(spi_device, "spi30", "spi3",GET_PIN(A, 15), RT_NULL))
|
||||
// {
|
||||
// rt_kprintf("Failed to attach the spi device.");
|
||||
// return -RT_ERROR;
|
||||
// }
|
||||
//// if (RT_NULL == rt_sfud_flash_probe("W25Q64", "spi30"))
|
||||
//// {
|
||||
//// rt_kprintf("Failed to probe the W25Q64.");
|
||||
// return -RT_ERROR;
|
||||
//// };
|
||||
//
|
||||
// return RT_EOK;
|
||||
//}
|
||||
//
|
||||
//INIT_COMPONENT_EXPORT(rt_hw_spi_flash_init);
|
||||
//
|
||||
//static void spi_w25q_sample(int argc, char *argv[])
|
||||
//{
|
||||
// struct rt_spi_device *spi_dev_w25q;
|
||||
// char name[RT_NAME_MAX];
|
||||
// rt_uint8_t w25x_read_id = 0x9F;
|
||||
// rt_uint8_t id[5] = {0};
|
||||
////
|
||||
////// if (argc == 2)
|
||||
////// {
|
||||
////// rt_strncpy(name, argv[1], RT_NAME_MAX);
|
||||
////// }
|
||||
////// else
|
||||
////// {
|
||||
////// rt_strncpy(name, W25Q_SPI_DEVICE_NAME, RT_NAME_MAX);
|
||||
////// }
|
||||
////
|
||||
// spi_dev_w25q = (struct rt_spi_device *)rt_device_find("spi30");
|
||||
// if (!spi_dev_w25q)
|
||||
// {
|
||||
// rt_kprintf("spi sample run failed! can't find %s device!\n", name);
|
||||
// }
|
||||
// else
|
||||
// {
|
||||
// rt_spi_send_then_recv(spi_dev_w25q, &w25x_read_id, 1, id, 5);
|
||||
// rt_kprintf("use rt_spi_send_then_recv() read w25q ID is:%x%x\n", id[3], id[4]);
|
||||
//
|
||||
//// struct rt_spi_message msg1, msg2;
|
||||
////
|
||||
//// msg1.send_buf = &w25x_read_id;
|
||||
//// msg1.recv_buf = RT_NULL;
|
||||
//// msg1.length = 1;
|
||||
//// msg1.cs_take = 1;
|
||||
//// msg1.cs_release = 0;
|
||||
//// msg1.next = &msg2;
|
||||
////
|
||||
//// msg2.send_buf = RT_NULL;
|
||||
//// msg2.recv_buf = id;
|
||||
//// msg2.length = 5;
|
||||
//// msg2.cs_take = 0;
|
||||
//// msg2.cs_release = 1;
|
||||
//// msg2.next = RT_NULL;
|
||||
////
|
||||
//// rt_spi_transfer_message(spi_dev_w25q, &msg1);
|
||||
//// rt_kprintf("use rt_spi_transfer_message() read w25q ID is:%x%x\n", id[3], id[4]);
|
||||
//
|
||||
//
|
||||
//// rt_uint8_t cmd = 0x9F; // 读取JEDEC ID的命令
|
||||
//// rt_uint8_t id[3]; // 存储ID的数组
|
||||
//// rt_uint32_t jedecID;
|
||||
//// char msg[50];
|
||||
//// /* USER CODE END 2 */
|
||||
//// rt_pin_mode(GET_PIN(A, 15), PIN_MODE_OUTPUT);
|
||||
//// // 默认为高电平
|
||||
//// rt_pin_write(GET_PIN(A, 15), PIN_HIGH);
|
||||
//// /* Infinite loop */
|
||||
//// /* USER CODE BEGIN WHILE */
|
||||
//// while (1)
|
||||
//// {
|
||||
////
|
||||
////
|
||||
//// rt_pin_write(GET_PIN(A, 15), PIN_LOW);
|
||||
//// HAL_SPI_Transmit(&hspi3, &cmd, 1, HAL_MAX_DELAY); // 发送读ID命令
|
||||
//// HAL_SPI_Receive(&hspi3, id, 3, HAL_MAX_DELAY); // 读取3字节的ID
|
||||
//// rt_pin_write(GET_PIN(A, 15), PIN_HIGH);
|
||||
////
|
||||
////
|
||||
//// jedecID = (id[0] << 16) | (id[1] << 8) | id[2]; // 组合ID
|
||||
////
|
||||
////
|
||||
//// rt_kprintf("JEDEC ID: %lX\r\n", jedecID);
|
||||
////
|
||||
//// rt_thread_mdelay(3000);
|
||||
//
|
||||
// }
|
||||
//}
|
||||
//MSH_CMD_EXPORT(spi_w25q_sample, spi w25q sample);
|
||||
38
applications/main.c
Normal file
38
applications/main.c
Normal file
@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-05-04 RT-Thread first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#define DBG_TAG "main"
|
||||
#define DBG_LVL DBG_LOG
|
||||
#include <rtdbg.h>
|
||||
#include <thread.h>
|
||||
|
||||
int main(void)
|
||||
{
|
||||
thread_IO_Key();
|
||||
thread_Wireless();
|
||||
thread_LCD();
|
||||
thread_IO_Speed();
|
||||
thread_485();
|
||||
thread_IO_ADC();
|
||||
|
||||
while (1)
|
||||
{
|
||||
// LOG_D("Hello RT-Thread!");
|
||||
rt_thread_mdelay(10);
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
325
applications/thread/thread.c
Normal file
325
applications/thread/thread.c
Normal file
@ -0,0 +1,325 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-04-23 lijian the first version
|
||||
*/
|
||||
#include <thread.h>
|
||||
|
||||
/* 使用静态线程时，线程的栈需要设置字节对齐 */
|
||||
rt_align(RT_ALIGN_SIZE)
|
||||
|
||||
static rt_uint8_t thread_io_key_stack[THREAD_STACK_SIZE_512];
|
||||
static rt_uint8_t thread_io_speed_stack[THREAD_STACK_SIZE_512];
|
||||
static rt_uint8_t thread_io_adc_stack[THREAD_STACK_SIZE_512];
|
||||
static rt_uint8_t thread_wireless_stack[THREAD_STACK_SIZE_512];
|
||||
static rt_uint8_t thread_485_stack[THREAD_STACK_SIZE_1024];
|
||||
static rt_uint8_t thread_lcd_stack[THREAD_STACK_SIZE_1024];
|
||||
static rt_uint8_t thread_yields_stack[THREAD_STACK_SIZE_256];
|
||||
static rt_uint8_t thread_check_save_stack[THREAD_STACK_SIZE_256];
|
||||
|
||||
/*
|
||||
* 优先级（从5开始，因4被定时器占据）
|
||||
* 电平检测 5
|
||||
* 速度 6
|
||||
* adc 6
|
||||
* 无线与MQTT 7
|
||||
* 485 8
|
||||
* OLED 7
|
||||
* 产量计算 8
|
||||
* 掉电检测与历史数据保存 5
|
||||
*/
|
||||
|
||||
//static rt_uint8_t thread_lcd_stack[THREAD_STACK_SIZE_512];
|
||||
static struct rt_thread tid_IO_Key;
|
||||
static struct rt_thread tid_IO_Speed;
|
||||
static struct rt_thread tid_IO_ADC;
|
||||
static struct rt_thread tid_WL;
|
||||
static struct rt_thread tid_485;
|
||||
static struct rt_thread tid_LCD;
|
||||
static struct rt_thread tid_Yields;
|
||||
static struct rt_thread tid_Check_Save;
|
||||
|
||||
/**
|
||||
* 定时器回调函数，30秒一次的心跳
|
||||
* @param parameter
|
||||
*/
|
||||
//static void timer_callback(void* parameter)
|
||||
//{
|
||||
//// if (get_WIFI_STATUS() && get_MQTT_STATUS())
|
||||
//// {
|
||||
//// if (get_MQTT_UPDATE_FLAG())
|
||||
//// {
|
||||
//// MQTT_Keep_Alive();
|
||||
//// }
|
||||
//// }
|
||||
//}
|
||||
|
||||
/* 线程的入口函数 */
|
||||
static void Task_IO_Key(void *parameter)
|
||||
{
|
||||
gpio_input_init();
|
||||
gpio_output_init();
|
||||
while (1)
|
||||
{
|
||||
// chage_IO_key();
|
||||
// updateKeyValue();
|
||||
rt_thread_mdelay(1);
|
||||
}
|
||||
}
|
||||
|
||||
static void Task_IO_Speed(void *parameter)
|
||||
{
|
||||
spi_flash_mb85rs_init();
|
||||
read_config();
|
||||
while (1)
|
||||
{
|
||||
|
||||
rt_thread_mdelay(1000);
|
||||
}
|
||||
}
|
||||
|
||||
static void Task_IO_ADC(void *parameter)
|
||||
{
|
||||
adc_init();
|
||||
while (1)
|
||||
{
|
||||
adc_read();
|
||||
rt_thread_mdelay(500);
|
||||
}
|
||||
}
|
||||
|
||||
static void Task_Wireless(void *parameter)
|
||||
{
|
||||
|
||||
AT_device_init();
|
||||
LTE_init();
|
||||
MQTT_init();
|
||||
|
||||
// rt_uint8_t var, Keep_Alive_OK,
|
||||
rt_tick_t tick_start, tick_end;
|
||||
|
||||
tick_start = rt_tick_get();
|
||||
while (1)
|
||||
{
|
||||
tick_end = rt_tick_get();
|
||||
//两秒交替一次检测状态
|
||||
if ((tick_end - tick_start) > 2000)
|
||||
{
|
||||
check_LTE_MQTT();
|
||||
tick_start = tick_end;
|
||||
}
|
||||
|
||||
//send MQTT
|
||||
|
||||
rt_thread_mdelay(3000);
|
||||
|
||||
}
|
||||
|
||||
// rt_timer_t timer = rt_timer_create("timer", // 定时器名称
|
||||
// timer_callback, // 定时器到期时调用的回调函数
|
||||
// RT_NULL, // 传递给回调函数的参数
|
||||
// rt_tick_from_millisecond(30000), // 定时器超时时间，单位为tick
|
||||
// RT_TIMER_FLAG_PERIODIC); // 定时器模式，周期性执行
|
||||
//
|
||||
// // 启动定时器
|
||||
// if (timer != RT_NULL)
|
||||
// {
|
||||
// rt_timer_start(timer);
|
||||
// }
|
||||
}
|
||||
|
||||
static void Task_485(void *parameter)
|
||||
{
|
||||
while (1)
|
||||
{
|
||||
Modbus_init();
|
||||
rt_thread_mdelay(100);
|
||||
}
|
||||
}
|
||||
|
||||
static void Task_Lcd(void *parameter)
|
||||
{
|
||||
oled_init();
|
||||
|
||||
while (1)
|
||||
{
|
||||
oled_menu();
|
||||
|
||||
rt_thread_mdelay(50);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
static void Task_Yields(void *parameter)
|
||||
{
|
||||
// rt_uint32_t count = 0;
|
||||
|
||||
while (1)
|
||||
{
|
||||
|
||||
//rt_kprintf("thread Yields count: %d\n", count++);
|
||||
rt_thread_mdelay(500);
|
||||
}
|
||||
}
|
||||
|
||||
static void Task_Check_Save(void *parameter)
|
||||
{
|
||||
while (1)
|
||||
{
|
||||
// updateNeedleCount();
|
||||
rt_thread_mdelay(1);
|
||||
}
|
||||
}
|
||||
|
||||
/* 线程 */
|
||||
rt_uint8_t thread_IO_Key(void)
|
||||
{
|
||||
/* 静态创建线程 */
|
||||
|
||||
/* 初始化IO线程 ，名称是 Thread_IO，入口是 THREAD_IO*/
|
||||
rt_thread_init(&tid_IO_Key, //指向线程控制块的指针，是用户定义的一个静态或全局变量，线程控制块通常包含了线程的状态信息、栈指针、优先级
|
||||
"Thread_IO_Key", //线程的名称
|
||||
Task_IO_Key, //线程的入口函数，即线程开始执行时调用的函数
|
||||
RT_NULL, //传递给线程入口函数的参数
|
||||
thread_io_key_stack, //线程栈的起始地址，通常是一个指向预分配栈空间的指针，线程在运行中会在这个栈上存储局部变量、函数参数等
|
||||
THREAD_STACK_SIZE_512, //线程栈的大小，单位通常是字节
|
||||
THREAD_PRIORITY_5, //线程的优先级，数值越小表示优先级越高
|
||||
THREAD_TIMESLICE_5); //时间片，用于调度同优先级的线程。当有多个相同优先级的线程时，它们会按照时间片轮转的方式共享CPU时间
|
||||
/* 启动线程 */
|
||||
rt_thread_startup(&tid_IO_Key);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
rt_uint8_t thread_IO_Speed(void)
|
||||
{
|
||||
/* 初始化速度线程 */
|
||||
rt_thread_init(&tid_IO_Speed, "Thread_IO_Speed", Task_IO_Speed,
|
||||
RT_NULL, thread_io_speed_stack,
|
||||
THREAD_STACK_SIZE_512,
|
||||
THREAD_PRIORITY_6,
|
||||
THREAD_TIMESLICE_5);
|
||||
|
||||
/* 启动线程 */
|
||||
rt_thread_startup(&tid_IO_Speed);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
rt_uint8_t thread_IO_ADC(void)
|
||||
{
|
||||
/* 初始化针数线程 */
|
||||
rt_thread_init(&tid_IO_ADC, "Thread_IO_ADC", Task_IO_ADC,
|
||||
RT_NULL, thread_io_adc_stack,
|
||||
THREAD_STACK_SIZE_512,
|
||||
THREAD_PRIORITY_6,
|
||||
THREAD_TIMESLICE_3);
|
||||
|
||||
/* 启动线程 */
|
||||
rt_thread_startup(&tid_IO_ADC);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
rt_uint8_t thread_Wireless(void)
|
||||
{
|
||||
/* 初始化网络线程 */
|
||||
rt_thread_init(&tid_WL, "Thread_wireless", Task_Wireless,
|
||||
RT_NULL, thread_wireless_stack,
|
||||
THREAD_STACK_SIZE_512,
|
||||
THREAD_PRIORITY_7,
|
||||
THREAD_TIMESLICE_5);
|
||||
|
||||
/* 启动线程 */
|
||||
rt_thread_startup(&tid_WL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
rt_uint8_t thread_485(void)
|
||||
{
|
||||
/* 初始化485线程 */
|
||||
rt_thread_init(&tid_485, "Thread_485", Task_485,
|
||||
RT_NULL, thread_485_stack,
|
||||
THREAD_STACK_SIZE_1024,
|
||||
THREAD_PRIORITY_8,
|
||||
THREAD_TIMESLICE_3);
|
||||
|
||||
/* 启动线程 */
|
||||
rt_thread_startup(&tid_485);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
rt_uint8_t thread_LCD(void)
|
||||
{
|
||||
/* 初始化LCD线程 */
|
||||
rt_thread_init(&tid_LCD, "Thread_lcd", Task_Lcd,
|
||||
RT_NULL, thread_lcd_stack,
|
||||
THREAD_STACK_SIZE_1024,
|
||||
THREAD_PRIORITY_7,
|
||||
THREAD_TIMESLICE_6);
|
||||
|
||||
/* 启动线程 */
|
||||
rt_thread_startup(&tid_LCD);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
rt_uint8_t thread_Yields(void)
|
||||
{
|
||||
/* 初始化产量线程 */
|
||||
rt_thread_init(&tid_Yields, "Thread_yields", Task_Yields,
|
||||
RT_NULL, thread_yields_stack,
|
||||
THREAD_STACK_SIZE_256,
|
||||
THREAD_PRIORITY_8,
|
||||
THREAD_TIMESLICE_5);
|
||||
|
||||
/* 启动线程 */
|
||||
rt_thread_startup(&tid_Yields);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
rt_uint8_t thread_Check_Save(void)
|
||||
{
|
||||
/* 初始化掉电保存线程 */
|
||||
rt_thread_init(&tid_Check_Save, "Thread_check_save", Task_Check_Save,
|
||||
RT_NULL, thread_check_save_stack,
|
||||
THREAD_STACK_SIZE_256,
|
||||
THREAD_PRIORITY_5,
|
||||
THREAD_TIMESLICE_3);
|
||||
|
||||
/* 启动线程 */
|
||||
rt_thread_startup(&tid_Check_Save);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* 动态线程示例 */
|
||||
//int thread(void)
|
||||
//{
|
||||
// /* 动态线程 ，名称是 thread1，入口是 thread1_entry*/
|
||||
// tid1 = rt_thread_create("thread1",
|
||||
// thread1_entry, RT_NULL,
|
||||
// THREAD_STACK_SIZE,
|
||||
// THREAD_PRIORITY, THREAD_TIMESLICE);
|
||||
// if (tid1 != RT_NULL)
|
||||
// rt_thread_startup(tid1);
|
||||
//
|
||||
//}
|
||||
//static void thread1_entry(void *parameter)
|
||||
//{
|
||||
// rt_uint32_t count = 0;
|
||||
//
|
||||
// while (1)
|
||||
// {
|
||||
// /* 线程 1 采用低优先级运行，一直打印计数值 */
|
||||
// rt_kprintf("thread1 count: %d\n", count ++);
|
||||
// rt_thread_mdelay(500);
|
||||
// }
|
||||
//}
|
||||
50
applications/thread/thread.h
Normal file
50
applications/thread/thread.h
Normal file
@ -0,0 +1,50 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-04-23 lijian the first version
|
||||
*/
|
||||
#ifndef APPLICATIONS_THREAD_THREAD_H_
|
||||
#define APPLICATIONS_THREAD_THREAD_H_
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <drv_common.h>
|
||||
#include <rtdevice.h>
|
||||
#include <inout.h>
|
||||
#include <LTE.h>
|
||||
#include <mb85rs.h>
|
||||
#include <gui.h>
|
||||
#include <modbus_rtu.h>
|
||||
#include <console.h>
|
||||
#include <mqtt.h>
|
||||
#include <adc.h>
|
||||
|
||||
#define THREAD_PRIORITY_5 5
|
||||
#define THREAD_PRIORITY_6 6
|
||||
#define THREAD_PRIORITY_7 7
|
||||
#define THREAD_PRIORITY_8 8
|
||||
#define THREAD_PRIORITY_9 9
|
||||
|
||||
#define THREAD_STACK_SIZE_1024 1024
|
||||
#define THREAD_STACK_SIZE_2048 2048
|
||||
#define THREAD_STACK_SIZE_512 512
|
||||
#define THREAD_STACK_SIZE_256 256
|
||||
#define THREAD_STACK_SIZE_128 128
|
||||
#define THREAD_TIMESLICE_3 3
|
||||
#define THREAD_TIMESLICE_5 5
|
||||
#define THREAD_TIMESLICE_6 6
|
||||
#define THREAD_TIMESLICE_10 10
|
||||
|
||||
rt_uint8_t thread_IO_Key(void);
|
||||
rt_uint8_t thread_IO_Speed(void);
|
||||
rt_uint8_t thread_IO_ADC(void);
|
||||
rt_uint8_t thread_Wireless(void);
|
||||
rt_uint8_t thread_485(void);
|
||||
rt_uint8_t thread_LCD(void);
|
||||
rt_uint8_t thread_Yields(void);
|
||||
rt_uint8_t thread_Check_Save(void);
|
||||
|
||||
#endif /* APPLICATIONS_THREAD_THREAD_H_ */
|
||||
410
drivers/board.c
Normal file
410
drivers/board.c
Normal file
@ -0,0 +1,410 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-05-04 RealThread first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <board.h>
|
||||
#include <drv_common.h>
|
||||
|
||||
SPI_HandleTypeDef hspi3;
|
||||
ADC_HandleTypeDef hadc1;
|
||||
ADC_HandleTypeDef hadc2;
|
||||
ADC_HandleTypeDef hadc3;
|
||||
|
||||
void HAL_SPI3_MspInit(void);
|
||||
|
||||
rt_weak void rt_hw_board_init()
|
||||
{
|
||||
extern void hw_board_init(char *clock_src, int32_t clock_src_freq, int32_t clock_target_freq);
|
||||
|
||||
/* Heap initialization */
|
||||
#if defined(RT_USING_HEAP)
|
||||
rt_system_heap_init((void *) HEAP_BEGIN, (void *) HEAP_END);
|
||||
#endif
|
||||
|
||||
hw_board_init(BSP_CLOCK_SOURCE, BSP_CLOCK_SOURCE_FREQ_MHZ, BSP_CLOCK_SYSTEM_FREQ_MHZ);
|
||||
|
||||
/* Set the shell console output device */
|
||||
#if defined(RT_USING_DEVICE) && defined(RT_USING_CONSOLE)
|
||||
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||
#endif
|
||||
|
||||
/* Board underlying hardware initialization */
|
||||
#ifdef RT_USING_COMPONENTS_INIT
|
||||
rt_components_board_init();
|
||||
#endif
|
||||
HAL_SPI3_MspInit();
|
||||
|
||||
MX_ADC1_Init();
|
||||
MX_ADC2_Init();
|
||||
MX_ADC3_Init();
|
||||
}
|
||||
|
||||
|
||||
void MX_SPI3_Init(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN SPI3_Init 0 */
|
||||
|
||||
/* USER CODE END SPI3_Init 0 */
|
||||
|
||||
/* USER CODE BEGIN SPI3_Init 1 */
|
||||
|
||||
/* USER CODE END SPI3_Init 1 */
|
||||
/* SPI3 parameter configuration*/
|
||||
hspi3.Instance = SPI3;
|
||||
hspi3.Init.Mode = SPI_MODE_MASTER;
|
||||
hspi3.Init.Direction = SPI_DIRECTION_2LINES;
|
||||
hspi3.Init.DataSize = SPI_DATASIZE_8BIT;
|
||||
hspi3.Init.CLKPolarity = SPI_POLARITY_LOW;
|
||||
hspi3.Init.CLKPhase = SPI_PHASE_1EDGE;
|
||||
hspi3.Init.NSS = SPI_NSS_SOFT;
|
||||
hspi3.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
|
||||
hspi3.Init.FirstBit = SPI_FIRSTBIT_MSB;
|
||||
hspi3.Init.TIMode = SPI_TIMODE_DISABLE;
|
||||
hspi3.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
||||
hspi3.Init.CRCPolynomial = 10;
|
||||
if (HAL_SPI_Init(&hspi3) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN SPI3_Init 2 */
|
||||
|
||||
/* USER CODE END SPI3_Init 2 */
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
void HAL_SPI3_MspInit(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||||
|
||||
/* USER CODE BEGIN SPI3_MspInit 0 */
|
||||
|
||||
/* USER CODE END SPI3_MspInit 0 */
|
||||
/* Peripheral clock enable */
|
||||
__HAL_RCC_AFIO_CLK_ENABLE();
|
||||
__HAL_AFIO_REMAP_SWJ_NOJTAG(); //禁用JTAG
|
||||
|
||||
__HAL_RCC_SPI3_CLK_ENABLE();
|
||||
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
/**SPI3 GPIO Configuration
|
||||
PB3 ------> SPI3_SCK
|
||||
PB4 ------> SPI3_MISO
|
||||
PB5 ------> SPI3_MOSI
|
||||
*/
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_5;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||||
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||||
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_4;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||||
|
||||
/* USER CODE BEGIN SPI3_MspInit 1 */
|
||||
|
||||
/* USER CODE END SPI3_MspInit 1 */
|
||||
|
||||
}
|
||||
|
||||
|
||||
void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
|
||||
{
|
||||
if(hspi->Instance==SPI3)
|
||||
{
|
||||
/* USER CODE BEGIN SPI3_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END SPI3_MspDeInit 0 */
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_SPI3_CLK_DISABLE();
|
||||
|
||||
/**SPI3 GPIO Configuration
|
||||
PB3 ------> SPI3_SCK
|
||||
PB4 ------> SPI3_MISO
|
||||
PB5 ------> SPI3_MOSI
|
||||
*/
|
||||
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5);
|
||||
|
||||
/* USER CODE BEGIN SPI3_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END SPI3_MspDeInit 1 */
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
void MX_ADC1_Init(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN ADC1_Init 0 */
|
||||
|
||||
/* USER CODE END ADC1_Init 0 */
|
||||
|
||||
ADC_ChannelConfTypeDef sConfig = {0};
|
||||
|
||||
/* USER CODE BEGIN ADC1_Init 1 */
|
||||
|
||||
/* USER CODE END ADC1_Init 1 */
|
||||
|
||||
/** Common config
|
||||
*/
|
||||
hadc1.Instance = ADC1;
|
||||
hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
|
||||
hadc1.Init.ContinuousConvMode = DISABLE;
|
||||
hadc1.Init.DiscontinuousConvMode = DISABLE;
|
||||
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
|
||||
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
|
||||
hadc1.Init.NbrOfConversion = 1;
|
||||
if (HAL_ADC_Init(&hadc1) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/** Configure Regular Channel
|
||||
*/
|
||||
sConfig.Channel = ADC_CHANNEL_0;
|
||||
sConfig.Rank = ADC_REGULAR_RANK_1;
|
||||
sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
|
||||
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN ADC1_Init 2 */
|
||||
|
||||
/* USER CODE END ADC1_Init 2 */
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief ADC2 Initialization Function
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void MX_ADC2_Init(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN ADC2_Init 0 */
|
||||
|
||||
/* USER CODE END ADC2_Init 0 */
|
||||
|
||||
ADC_ChannelConfTypeDef sConfig = {0};
|
||||
|
||||
/* USER CODE BEGIN ADC2_Init 1 */
|
||||
|
||||
/* USER CODE END ADC2_Init 1 */
|
||||
|
||||
/** Common config
|
||||
*/
|
||||
hadc2.Instance = ADC2;
|
||||
hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE;
|
||||
hadc2.Init.ContinuousConvMode = DISABLE;
|
||||
hadc2.Init.DiscontinuousConvMode = DISABLE;
|
||||
hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START;
|
||||
hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT;
|
||||
hadc2.Init.NbrOfConversion = 1;
|
||||
if (HAL_ADC_Init(&hadc2) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/** Configure Regular Channel
|
||||
*/
|
||||
sConfig.Channel = ADC_CHANNEL_4;
|
||||
sConfig.Rank = ADC_REGULAR_RANK_1;
|
||||
sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
|
||||
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN ADC2_Init 2 */
|
||||
|
||||
/* USER CODE END ADC2_Init 2 */
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief ADC3 Initialization Function
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void MX_ADC3_Init(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN ADC3_Init 0 */
|
||||
|
||||
/* USER CODE END ADC3_Init 0 */
|
||||
|
||||
ADC_ChannelConfTypeDef sConfig = {0};
|
||||
|
||||
/* USER CODE BEGIN ADC3_Init 1 */
|
||||
|
||||
/* USER CODE END ADC3_Init 1 */
|
||||
|
||||
/** Common config
|
||||
*/
|
||||
hadc3.Instance = ADC3;
|
||||
hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE;
|
||||
hadc3.Init.ContinuousConvMode = DISABLE;
|
||||
hadc3.Init.DiscontinuousConvMode = DISABLE;
|
||||
hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START;
|
||||
hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT;
|
||||
hadc3.Init.NbrOfConversion = 1;
|
||||
if (HAL_ADC_Init(&hadc3) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/** Configure Regular Channel
|
||||
*/
|
||||
sConfig.Channel = ADC_CHANNEL_11;
|
||||
sConfig.Rank = ADC_REGULAR_RANK_1;
|
||||
sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
|
||||
if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN ADC3_Init 2 */
|
||||
|
||||
/* USER CODE END ADC3_Init 2 */
|
||||
|
||||
}
|
||||
|
||||
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||||
if(hadc->Instance==ADC1)
|
||||
{
|
||||
/* USER CODE BEGIN ADC1_MspInit 0 */
|
||||
|
||||
/* USER CODE END ADC1_MspInit 0 */
|
||||
/* Peripheral clock enable */
|
||||
__HAL_RCC_ADC1_CLK_ENABLE();
|
||||
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
/**ADC1 GPIO Configuration
|
||||
PA0-WKUP ------> ADC1_IN0
|
||||
*/
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_0;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
/* USER CODE BEGIN ADC1_MspInit 1 */
|
||||
|
||||
/* USER CODE END ADC1_MspInit 1 */
|
||||
}
|
||||
else if(hadc->Instance==ADC2)
|
||||
{
|
||||
/* USER CODE BEGIN ADC2_MspInit 0 */
|
||||
|
||||
/* USER CODE END ADC2_MspInit 0 */
|
||||
/* Peripheral clock enable */
|
||||
__HAL_RCC_ADC2_CLK_ENABLE();
|
||||
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
/**ADC2 GPIO Configuration
|
||||
PA4 ------> ADC2_IN4
|
||||
*/
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_4;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
/* USER CODE BEGIN ADC2_MspInit 1 */
|
||||
|
||||
/* USER CODE END ADC2_MspInit 1 */
|
||||
}
|
||||
else if(hadc->Instance==ADC3)
|
||||
{
|
||||
/* USER CODE BEGIN ADC3_MspInit 0 */
|
||||
|
||||
/* USER CODE END ADC3_MspInit 0 */
|
||||
/* Peripheral clock enable */
|
||||
__HAL_RCC_ADC3_CLK_ENABLE();
|
||||
|
||||
__HAL_RCC_GPIOC_CLK_ENABLE();
|
||||
/**ADC3 GPIO Configuration
|
||||
PC0 ------> ADC3_IN10
|
||||
PC1 ------> ADC3_IN11
|
||||
*/
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
||||
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
||||
|
||||
/* USER CODE BEGIN ADC3_MspInit 1 */
|
||||
|
||||
/* USER CODE END ADC3_MspInit 1 */
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief ADC MSP De-Initialization
|
||||
* This function freeze the hardware resources used in this example
|
||||
* @param hadc: ADC handle pointer
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
|
||||
{
|
||||
if(hadc->Instance==ADC1)
|
||||
{
|
||||
/* USER CODE BEGIN ADC1_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END ADC1_MspDeInit 0 */
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_ADC1_CLK_DISABLE();
|
||||
|
||||
/**ADC1 GPIO Configuration
|
||||
PA0-WKUP ------> ADC1_IN0
|
||||
*/
|
||||
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0);
|
||||
|
||||
/* USER CODE BEGIN ADC1_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END ADC1_MspDeInit 1 */
|
||||
}
|
||||
else if(hadc->Instance==ADC2)
|
||||
{
|
||||
/* USER CODE BEGIN ADC2_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END ADC2_MspDeInit 0 */
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_ADC2_CLK_DISABLE();
|
||||
|
||||
/**ADC2 GPIO Configuration
|
||||
PA4 ------> ADC2_IN4
|
||||
*/
|
||||
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4);
|
||||
|
||||
/* USER CODE BEGIN ADC2_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END ADC2_MspDeInit 1 */
|
||||
}
|
||||
else if(hadc->Instance==ADC3)
|
||||
{
|
||||
/* USER CODE BEGIN ADC3_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END ADC3_MspDeInit 0 */
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_ADC3_CLK_DISABLE();
|
||||
|
||||
/**ADC3 GPIO Configuration
|
||||
PC0 ------> ADC3_IN10
|
||||
PC1 ------> ADC3_IN11
|
||||
*/
|
||||
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0|GPIO_PIN_1);
|
||||
|
||||
/* USER CODE BEGIN ADC3_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END ADC3_MspDeInit 1 */
|
||||
}
|
||||
|
||||
}
|
||||
386
drivers/board.h
Normal file
386
drivers/board.h
Normal file
@ -0,0 +1,386 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-05-04 RealThread first version
|
||||
*/
|
||||
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include <stm32f1xx.h>
|
||||
#include <drv_common.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*-------------------------- CHIP CONFIG BEGIN --------------------------*/
|
||||
|
||||
#define CHIP_FAMILY_STM32
|
||||
#define CHIP_SERIES_STM32F1
|
||||
#define CHIP_NAME_STM32F103RC
|
||||
|
||||
/*-------------------------- CHIP CONFIG END --------------------------*/
|
||||
|
||||
/*-------------------------- ROM/RAM CONFIG BEGIN --------------------------*/
|
||||
|
||||
#define ROM_START ((uint32_t)0x08000000)
|
||||
#define ROM_SIZE (256 * 1024)
|
||||
#define ROM_END ((uint32_t)(ROM_START + ROM_SIZE))
|
||||
|
||||
#define RAM_START (0x20000000)
|
||||
#define RAM_SIZE (48 * 1024)
|
||||
#define RAM_END (RAM_START + RAM_SIZE)
|
||||
|
||||
/*-------------------------- ROM/RAM CONFIG END --------------------------*/
|
||||
|
||||
/*-------------------------- CLOCK CONFIG BEGIN --------------------------*/
|
||||
|
||||
#define BSP_CLOCK_SOURCE ("HSE")
|
||||
#define BSP_CLOCK_SOURCE_FREQ_MHZ ((int32_t)0)
|
||||
#define BSP_CLOCK_SYSTEM_FREQ_MHZ ((int32_t)72)
|
||||
|
||||
/*-------------------------- CLOCK CONFIG END --------------------------*/
|
||||
|
||||
/*-------------------------- UART CONFIG BEGIN --------------------------*/
|
||||
|
||||
/** After configuring corresponding UART or UART DMA, you can use it.
|
||||
*
|
||||
* STEP 1, define macro define related to the serial port opening based on the serial port number
|
||||
* such as #define BSP_USING_UART1
|
||||
*
|
||||
* STEP 2, according to the corresponding pin of serial port, define the related serial port information macro
|
||||
* such as #define BSP_UART1_TX_PIN "PA9"
|
||||
* #define BSP_UART1_RX_PIN "PA10"
|
||||
*
|
||||
* STEP 3, if you want using SERIAL DMA, you must open it in the RT-Thread Settings.
|
||||
* RT-Thread Setting -> Components -> Device Drivers -> Serial Device Drivers -> Enable Serial DMA Mode
|
||||
*
|
||||
* STEP 4, according to serial port number to define serial port tx/rx DMA function in the board.h file
|
||||
* such as #define BSP_UART1_RX_USING_DMA
|
||||
*
|
||||
*/
|
||||
|
||||
#define BSP_USING_UART1
|
||||
#define BSP_UART1_TX_PIN "PA9"
|
||||
#define BSP_UART1_RX_PIN "PA10"
|
||||
#define BSP_USING_UART2
|
||||
#define BSP_UART2_TX_PIN "PA2"
|
||||
#define BSP_UART2_RX_PIN "PA3"
|
||||
#define BSP_USING_UART3
|
||||
#define BSP_UART3_TX_PIN "PB10"
|
||||
#define BSP_UART3_RX_PIN "PB11"
|
||||
#define BSP_UART3_RX_USING_DMA
|
||||
#define BSP_USING_UART4
|
||||
#define BSP_UART4_TX_PIN "PC10"
|
||||
#define BSP_UART4_RX_PIN "PC11"
|
||||
#define BSP_USING_UART5
|
||||
#define BSP_UART5_TX_PIN "PC12"
|
||||
#define BSP_UART5_RX_PIN "PD2"
|
||||
//#define BSP_UART3_RX_USING_DMA
|
||||
|
||||
/*-------------------------- UART CONFIG END --------------------------*/
|
||||
|
||||
/*-------------------------- I2C CONFIG BEGIN --------------------------*/
|
||||
|
||||
/** if you want to use i2c bus(soft simulate) you can use the following instructions.
|
||||
*
|
||||
* STEP 1, open i2c driver framework(soft simulate) support in the RT-Thread Settings file
|
||||
*
|
||||
* STEP 2, define macro related to the i2c bus
|
||||
* such as #define BSP_USING_I2C1
|
||||
*
|
||||
* STEP 3, according to the corresponding pin of i2c port, modify the related i2c port and pin information
|
||||
* such as #define BSP_I2C1_SCL_PIN GET_PIN(port, pin) -> GET_PIN(C, 11)
|
||||
* #define BSP_I2C1_SDA_PIN GET_PIN(port, pin) -> GET_PIN(C, 12)
|
||||
*/
|
||||
|
||||
#define BSP_USING_I2C1
|
||||
#ifdef BSP_USING_I2C1
|
||||
#define BSP_I2C1_SCL_PIN GET_PIN(B, 6)
|
||||
#define BSP_I2C1_SDA_PIN GET_PIN(B, 7)
|
||||
#endif
|
||||
|
||||
/*#define BSP_USING_I2C2*/
|
||||
#ifdef BSP_USING_I2C2
|
||||
#define BSP_I2C2_SCL_PIN GET_PIN(port, pin)
|
||||
#define BSP_I2C2_SDA_PIN GET_PIN(port, pin)
|
||||
#endif
|
||||
|
||||
/*-------------------------- I2C CONFIG END --------------------------*/
|
||||
|
||||
/*-------------------------- SPI CONFIG BEGIN --------------------------*/
|
||||
|
||||
/** if you want to use spi bus you can use the following instructions.
|
||||
*
|
||||
* STEP 1, open spi driver framework support in the RT-Thread Settings file
|
||||
*
|
||||
* STEP 2, define macro related to the spi bus
|
||||
* such as #define BSP_USING_SPI1
|
||||
*
|
||||
* STEP 3, copy your spi init function from stm32xxxx_hal_msp.c generated by stm32cubemx to the end of board.c file
|
||||
* such as void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
|
||||
*
|
||||
* STEP 4, modify your stm32xxxx_hal_config.h file to support spi peripherals. define macro related to the peripherals
|
||||
* such as #define HAL_SPI_MODULE_ENABLED
|
||||
*/
|
||||
|
||||
#define BSP_USING_SPI3
|
||||
#define wcs_pin_ GET_PIN(A, 15)
|
||||
/*#define BSP_USING_SPI2*/
|
||||
/*#define BSP_USING_SPI1*/
|
||||
|
||||
/*-------------------------- SPI CONFIG END --------------------------*/
|
||||
|
||||
/*-------------------------- QSPI CONFIG BEGIN --------------------------*/
|
||||
|
||||
/** if you want to use qspi you can use the following instructions.
|
||||
*
|
||||
* STEP 1, open qspi driver framework support in the RT-Thread Settings file
|
||||
*
|
||||
* STEP 2, define macro related to the qspi
|
||||
* such as #define BSP_USING_QSPI
|
||||
*
|
||||
* STEP 3, copy your qspi init function from stm32xxxx_hal_msp.c generated by stm32cubemx to the end of board.c file
|
||||
* such as void HAL_QSPI_MspInit(QSPI_HandleTypeDef* hqspi)
|
||||
*
|
||||
* STEP 4, modify your stm32xxxx_hal_config.h file to support qspi peripherals. define macro related to the peripherals
|
||||
* such as #define HAL_QSPI_MODULE_ENABLED
|
||||
*
|
||||
*/
|
||||
|
||||
/*#define BSP_USING_QSPI*/
|
||||
|
||||
/*-------------------------- QSPI CONFIG END --------------------------*/
|
||||
|
||||
/*-------------------------- PWM CONFIG BEGIN --------------------------*/
|
||||
|
||||
/** if you want to use pwm you can use the following instructions.
|
||||
*
|
||||
* STEP 1, open pwm driver framework support in the RT-Thread Settings file
|
||||
*
|
||||
* STEP 2, define macro related to the pwm
|
||||
* such as #define BSP_USING_PWM1
|
||||
*
|
||||
* STEP 3, copy your pwm timer init function from stm32xxxx_hal_msp.c generated by stm32cubemx to the end if board.c file
|
||||
* such as void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) and
|
||||
* void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
|
||||
*
|
||||
* STEP 4, modify your stm32xxxx_hal_config.h file to support pwm peripherals. define macro related to the peripherals
|
||||
* such as #define HAL_TIM_MODULE_ENABLED
|
||||
*
|
||||
*/
|
||||
|
||||
/*#define BSP_USING_PWM1*/
|
||||
/*#define BSP_USING_PWM2*/
|
||||
/*#define BSP_USING_PWM3*/
|
||||
|
||||
/*-------------------------- PWM CONFIG END --------------------------*/
|
||||
|
||||
/*-------------------------- ADC CONFIG BEGIN --------------------------*/
|
||||
|
||||
/** if you want to use adc you can use the following instructions.
|
||||
*
|
||||
* STEP 1, open adc driver framework support in the RT-Thread Settings file
|
||||
*
|
||||
* STEP 2, define macro related to the adc
|
||||
* such as #define BSP_USING_ADC1
|
||||
*
|
||||
* STEP 3, copy your adc init function from stm32xxxx_hal_msp.c generated by stm32cubemx to the end of board.c file
|
||||
* such as void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
|
||||
*
|
||||
* STEP 4, modify your stm32xxxx_hal_config.h file to support adc peripherals. define macro related to the peripherals
|
||||
* such as #define HAL_ADC_MODULE_ENABLED
|
||||
*
|
||||
*/
|
||||
|
||||
#define BSP_USING_ADC1
|
||||
#define BSP_USING_ADC2
|
||||
#define BSP_USING_ADC3
|
||||
|
||||
/*-------------------------- ADC CONFIG END --------------------------*/
|
||||
|
||||
/*-------------------------- WDT CONFIG BEGIN --------------------------*/
|
||||
|
||||
/** if you want to use wdt you can use the following instructions.
|
||||
*
|
||||
* STEP 1, open wdt driver framework support in the RT-Thread Settings file
|
||||
*
|
||||
* STEP 2, modify your stm32xxxx_hal_config.h file to support wdt peripherals. define macro related to the peripherals
|
||||
* such as #define HAL_IWDG_MODULE_ENABLED
|
||||
*
|
||||
*/
|
||||
|
||||
/*-------------------------- WDT CONFIG END --------------------------*/
|
||||
|
||||
/*-------------------------- HARDWARE TIMER CONFIG BEGIN --------------------------*/
|
||||
|
||||
/** if you want to use hardware timer you can use the following instructions.
|
||||
*
|
||||
* STEP 1, open hwtimer driver framework support in the RT-Thread Settings file
|
||||
*
|
||||
* STEP 2, define macro related to the hwtimer
|
||||
* such as #define BSP_USING_TIM and
|
||||
* #define BSP_USING_TIM1
|
||||
*
|
||||
* STEP 3, copy your hardwire timer init function from stm32xxxx_hal_msp.c generated by stm32cubemx to the end of board.c file
|
||||
* such as void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
|
||||
*
|
||||
* STEP 4, modify your stm32xxxx_hal_config.h file to support hardwere timer peripherals. define macro related to the peripherals
|
||||
* such as #define HAL_TIM_MODULE_ENABLED
|
||||
*
|
||||
*/
|
||||
|
||||
/*#define BSP_USING_TIM*/
|
||||
#ifdef BSP_USING_TIM
|
||||
/*#define BSP_USING_TIM15*/
|
||||
/*#define BSP_USING_TIM16*/
|
||||
/*#define BSP_USING_TIM17*/
|
||||
#endif
|
||||
|
||||
/*-------------------------- HAREWARE TIMER CONFIG END --------------------------*/
|
||||
|
||||
/*-------------------------- RTC CONFIG BEGIN --------------------------*/
|
||||
|
||||
/** if you want to use rtc(hardware) you can use the following instructions.
|
||||
*
|
||||
* STEP 1, open rtc driver framework(hardware) support in the RT-Thread Settings file
|
||||
*
|
||||
* STEP 2, define macro related to the rtc
|
||||
* such as BSP_USING_ONCHIP_RTC
|
||||
*
|
||||
* STEP 3, modify your stm32xxxx_hal_config.h file to support rtc peripherals. define macro related to the peripherals
|
||||
* such as #define HAL_RTC_MODULE_ENABLED
|
||||
*
|
||||
*/
|
||||
/*#define BSP_USING_ONCHIP_RTC*/
|
||||
|
||||
/*-------------------------- RTC CONFIG END --------------------------*/
|
||||
|
||||
/*-------------------------- SDIO CONFIG BEGIN --------------------------*/
|
||||
|
||||
/** if you want to use sdio you can use the following instructions.
|
||||
*
|
||||
* STEP 1, open sdio driver framework support in the RT-Thread Settings file
|
||||
*
|
||||
* STEP 2, define macro related to the sdio
|
||||
* such as BSP_USING_SDIO
|
||||
*
|
||||
* STEP 3, copy your sdio init function from stm32xxxx_hal_msp.c generated by stm32cubemx to the end of board.c file
|
||||
* such as void HAL_SD_MspInit(SD_HandleTypeDef* hsd)
|
||||
*
|
||||
* STEP 4, modify your stm32xxxx_hal_config.h file to support sdio peripherals. define macro related to the peripherals
|
||||
* such as #define HAL_SD_MODULE_ENABLED
|
||||
*
|
||||
* STEP 5, config your device file system or another applications
|
||||
*
|
||||
*/
|
||||
|
||||
/*#define BSP_USING_SDIO*/
|
||||
|
||||
/*-------------------------- SDIO CONFIG END --------------------------*/
|
||||
|
||||
/*-------------------------- ETH CONFIG BEGIN --------------------------*/
|
||||
|
||||
/** if you want to use eth you can use the following instructions.
|
||||
*
|
||||
* STEP 1, define macro related to the eth
|
||||
* such as BSP_USING_ETH
|
||||
*
|
||||
* STEP 2, copy your eth init function from stm32xxxx_hal_msp.c generated by stm32cubemx to the end if board.c file
|
||||
* such as void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
|
||||
*
|
||||
* STEP 3, modify your stm32xxxx_hal_config.h file to support eth peripherals. define macro related to the peripherals
|
||||
* such as #define HAL_ETH_MODULE_ENABLED
|
||||
*
|
||||
* STEP 4, config your phy type
|
||||
* such as #define PHY_USING_LAN8720A
|
||||
* #define PHY_USING_DM9161CEP
|
||||
* #define PHY_USING_DP83848C
|
||||
* STEP 5, implement your phy reset function in the end of board.c file
|
||||
* void phy_reset(void)
|
||||
*
|
||||
* STEP 6, config your lwip or other network stack
|
||||
*
|
||||
*/
|
||||
|
||||
/*#define BSP_USING_ETH*/
|
||||
#ifdef BSP_USING_ETH
|
||||
/*#define PHY_USING_LAN8720A*/
|
||||
/*#define PHY_USING_DM9161CEP*/
|
||||
/*#define PHY_USING_DP83848C*/
|
||||
#endif
|
||||
/*-------------------------- ETH CONFIG END --------------------------*/
|
||||
|
||||
/*-------------------------- USB HOST CONFIG BEGIN --------------------------*/
|
||||
|
||||
/** if you want to use usb host you can use the following instructions.
|
||||
*
|
||||
* STEP 1, open usb host driver framework support in the RT-Thread Settings file
|
||||
*
|
||||
* STEP 2, define macro related to the usb host
|
||||
* such as BSP_USING_USBHOST
|
||||
*
|
||||
* STEP 3, copy your usb host init function from stm32xxxx_hal_msp.c generated by stm32cubemx to the end of board.c file
|
||||
* such as void HAL_HCD_MspInit(HCD_HandleTypeDef* hhcd)
|
||||
*
|
||||
* STEP 4, config your usb peripheral clock in SystemClock_Config() generated by STM32CubeMX and replace this function in board.c
|
||||
*
|
||||
* STEP 5, modify your stm32xxxx_hal_config.h file to support usb host peripherals. define macro related to the peripherals
|
||||
* such as #define HAL_HCD_MODULE_ENABLED
|
||||
*
|
||||
*/
|
||||
|
||||
/*#define BSP_USING_USBHOST*/
|
||||
|
||||
/*-------------------------- USB HOST CONFIG END --------------------------*/
|
||||
|
||||
/*-------------------------- USB DEVICE CONFIG BEGIN --------------------------*/
|
||||
|
||||
/** if you want to use usb device you can use the following instructions.
|
||||
*
|
||||
* STEP 1, open usb device driver framework support in the RT-Thread Settings file
|
||||
*
|
||||
* STEP 2 define macro related to the usb device
|
||||
* such as BSP_USING_USBDEVICE
|
||||
*
|
||||
* STEP 3, copy your usb device init function from stm32xxxx_hal_msp.c generated by stm32cubemx to the end of board.c file
|
||||
* such as void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd)
|
||||
*
|
||||
* STEP 4, config your usb peripheral clock in SystemClock_Config() generated by STM32CubeMX and replace this function in board.c
|
||||
*
|
||||
* STEP 5, modify your stm32xxxx_hal_config.h file to support usb device peripherals. define macro related to the peripherals
|
||||
* such as #define HAL_PCD_MODULE_ENABLED
|
||||
*
|
||||
*/
|
||||
|
||||
/*#define BSP_USING_USBDEVICE*/
|
||||
|
||||
/*-------------------------- USB DEVICE CONFIG END --------------------------*/
|
||||
|
||||
/*-------------------------- ON_CHIP_FLASH CONFIG BEGIN --------------------------*/
|
||||
|
||||
/** if you want to use on chip flash you can use the following instructions.
|
||||
*
|
||||
* STEP 1 define macro related to the on chip flash
|
||||
* such as BSP_USING_ON_CHIP_FLASH
|
||||
*
|
||||
* STEP 2, modify your stm32xxxx_hal_config.h file to support on chip flash peripherals. define macro related to the peripherals
|
||||
* such as #define HAL_FLASH_MODULE_ENABLED
|
||||
*
|
||||
*/
|
||||
|
||||
/*#define BSP_USING_ON_CHIP_FLASH*/
|
||||
|
||||
/*-------------------------- ON_CHIP_FLASH CONFIG END --------------------------*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __BOARD_H__ */
|
||||
286
drivers/drv_adc.c
Normal file
286
drivers/drv_adc.c
Normal file
@ -0,0 +1,286 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-05 zylx first version
|
||||
* 2018-12-12 greedyhao Porting for stm32f7xx
|
||||
* 2019-02-01 yuneizhilin fix the stm32_adc_init function initialization issue
|
||||
*/
|
||||
|
||||
#include <board.h>
|
||||
#include<rtthread.h>
|
||||
#include<rtdevice.h>
|
||||
|
||||
#if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3)
|
||||
#include "drv_config.h"
|
||||
|
||||
//#define DRV_DEBUG
|
||||
#define LOG_TAG "drv.adc"
|
||||
#include <drv_log.h>
|
||||
|
||||
static ADC_HandleTypeDef adc_config[] =
|
||||
{
|
||||
#ifdef BSP_USING_ADC1
|
||||
ADC1_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_ADC2
|
||||
ADC2_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_ADC3
|
||||
ADC3_CONFIG,
|
||||
#endif
|
||||
};
|
||||
|
||||
struct stm32_adc
|
||||
{
|
||||
ADC_HandleTypeDef ADC_Handler;
|
||||
struct rt_adc_device stm32_adc_device;
|
||||
};
|
||||
|
||||
static struct stm32_adc stm32_adc_obj[sizeof(adc_config) / sizeof(adc_config[0])];
|
||||
|
||||
static rt_err_t stm32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
|
||||
{
|
||||
ADC_HandleTypeDef *stm32_adc_handler;
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
stm32_adc_handler = device->parent.user_data;
|
||||
|
||||
if (enabled)
|
||||
{
|
||||
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
|
||||
ADC_Enable(stm32_adc_handler);
|
||||
#else
|
||||
__HAL_ADC_ENABLE(stm32_adc_handler);
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
|
||||
ADC_Disable(stm32_adc_handler);
|
||||
#else
|
||||
__HAL_ADC_DISABLE(stm32_adc_handler);
|
||||
#endif
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_uint32_t stm32_adc_get_channel(rt_uint32_t channel)
|
||||
{
|
||||
rt_uint32_t stm32_channel = 0;
|
||||
|
||||
switch (channel)
|
||||
{
|
||||
case 0:
|
||||
stm32_channel = ADC_CHANNEL_0;
|
||||
break;
|
||||
case 1:
|
||||
stm32_channel = ADC_CHANNEL_1;
|
||||
break;
|
||||
case 2:
|
||||
stm32_channel = ADC_CHANNEL_2;
|
||||
break;
|
||||
case 3:
|
||||
stm32_channel = ADC_CHANNEL_3;
|
||||
break;
|
||||
case 4:
|
||||
stm32_channel = ADC_CHANNEL_4;
|
||||
break;
|
||||
case 5:
|
||||
stm32_channel = ADC_CHANNEL_5;
|
||||
break;
|
||||
case 6:
|
||||
stm32_channel = ADC_CHANNEL_6;
|
||||
break;
|
||||
case 7:
|
||||
stm32_channel = ADC_CHANNEL_7;
|
||||
break;
|
||||
case 8:
|
||||
stm32_channel = ADC_CHANNEL_8;
|
||||
break;
|
||||
case 9:
|
||||
stm32_channel = ADC_CHANNEL_9;
|
||||
break;
|
||||
case 10:
|
||||
stm32_channel = ADC_CHANNEL_10;
|
||||
break;
|
||||
case 11:
|
||||
stm32_channel = ADC_CHANNEL_11;
|
||||
break;
|
||||
case 12:
|
||||
stm32_channel = ADC_CHANNEL_12;
|
||||
break;
|
||||
case 13:
|
||||
stm32_channel = ADC_CHANNEL_13;
|
||||
break;
|
||||
case 14:
|
||||
stm32_channel = ADC_CHANNEL_14;
|
||||
break;
|
||||
case 15:
|
||||
stm32_channel = ADC_CHANNEL_15;
|
||||
break;
|
||||
#ifdef ADC_CHANNEL_16
|
||||
case 16:
|
||||
stm32_channel = ADC_CHANNEL_16;
|
||||
break;
|
||||
#endif
|
||||
case 17:
|
||||
stm32_channel = ADC_CHANNEL_17;
|
||||
break;
|
||||
#ifdef ADC_CHANNEL_18
|
||||
case 18:
|
||||
stm32_channel = ADC_CHANNEL_18;
|
||||
break;
|
||||
#endif
|
||||
#ifdef ADC_CHANNEL_19
|
||||
case 19:
|
||||
stm32_channel = ADC_CHANNEL_19;
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
|
||||
return stm32_channel;
|
||||
}
|
||||
|
||||
static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
|
||||
{
|
||||
ADC_ChannelConfTypeDef ADC_ChanConf;
|
||||
ADC_HandleTypeDef *stm32_adc_handler;
|
||||
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
RT_ASSERT(value != RT_NULL);
|
||||
|
||||
stm32_adc_handler = device->parent.user_data;
|
||||
|
||||
rt_memset(&ADC_ChanConf, 0, sizeof(ADC_ChanConf));
|
||||
|
||||
#ifndef ADC_CHANNEL_16
|
||||
if (channel == 16)
|
||||
{
|
||||
LOG_E("ADC channel must not be 16.");
|
||||
return -RT_ERROR;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* ADC channel number is up to 17 */
|
||||
#if !defined(ADC_CHANNEL_18)
|
||||
if (channel <= 17)
|
||||
/* ADC channel number is up to 19 */
|
||||
#elif defined(ADC_CHANNEL_19)
|
||||
if (channel <= 19)
|
||||
/* ADC channel number is up to 18 */
|
||||
#else
|
||||
if (channel <= 18)
|
||||
#endif
|
||||
{
|
||||
/* set stm32 ADC channel */
|
||||
ADC_ChanConf.Channel = stm32_adc_get_channel(channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
#if !defined(ADC_CHANNEL_18)
|
||||
LOG_E("ADC channel must be between 0 and 17.");
|
||||
#elif defined(ADC_CHANNEL_19)
|
||||
LOG_E("ADC channel must be between 0 and 19.");
|
||||
#else
|
||||
LOG_E("ADC channel must be between 0 and 18.");
|
||||
#endif
|
||||
return -RT_ERROR;
|
||||
}
|
||||
ADC_ChanConf.Rank = 1;
|
||||
#if defined(SOC_SERIES_STM32F0)
|
||||
ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_71CYCLES_5;
|
||||
#elif defined(SOC_SERIES_STM32F1)
|
||||
ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_55CYCLES_5;
|
||||
#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||||
ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_112CYCLES;
|
||||
#elif defined(SOC_SERIES_STM32L4)
|
||||
ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_247CYCLES_5;
|
||||
#endif
|
||||
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
|
||||
ADC_ChanConf.Offset = 0;
|
||||
#endif
|
||||
#ifdef SOC_SERIES_STM32L4
|
||||
ADC_ChanConf.OffsetNumber = ADC_OFFSET_NONE;
|
||||
ADC_ChanConf.SingleDiff = LL_ADC_SINGLE_ENDED;
|
||||
#endif
|
||||
HAL_ADC_ConfigChannel(stm32_adc_handler, &ADC_ChanConf);
|
||||
|
||||
/* start ADC */
|
||||
HAL_ADC_Start(stm32_adc_handler);
|
||||
|
||||
/* Wait for the ADC to convert */
|
||||
HAL_ADC_PollForConversion(stm32_adc_handler, 100);
|
||||
|
||||
/* get ADC value */
|
||||
*value = (rt_uint32_t)HAL_ADC_GetValue(stm32_adc_handler);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static const struct rt_adc_ops stm_adc_ops =
|
||||
{
|
||||
.enabled = stm32_adc_enabled,
|
||||
.convert = stm32_get_adc_value,
|
||||
};
|
||||
|
||||
static int stm32_adc_init(void)
|
||||
{
|
||||
int result = RT_EOK;
|
||||
/* save adc name */
|
||||
char name_buf[5] = {'a', 'd', 'c', '0', 0};
|
||||
int i = 0;
|
||||
|
||||
for (i = 0; i < sizeof(adc_config) / sizeof(adc_config[0]); i++)
|
||||
{
|
||||
/* ADC init */
|
||||
name_buf[3] = '0';
|
||||
stm32_adc_obj[i].ADC_Handler = adc_config[i];
|
||||
#if defined(ADC1)
|
||||
if (stm32_adc_obj[i].ADC_Handler.Instance == ADC1)
|
||||
{
|
||||
name_buf[3] = '1';
|
||||
}
|
||||
#endif
|
||||
#if defined(ADC2)
|
||||
if (stm32_adc_obj[i].ADC_Handler.Instance == ADC2)
|
||||
{
|
||||
name_buf[3] = '2';
|
||||
}
|
||||
#endif
|
||||
#if defined(ADC3)
|
||||
if (stm32_adc_obj[i].ADC_Handler.Instance == ADC3)
|
||||
{
|
||||
name_buf[3] = '3';
|
||||
}
|
||||
#endif
|
||||
if (HAL_ADC_Init(&stm32_adc_obj[i].ADC_Handler) != HAL_OK)
|
||||
{
|
||||
LOG_E("%s init failed", name_buf);
|
||||
result = -RT_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* register ADC device */
|
||||
if (rt_hw_adc_register(&stm32_adc_obj[i].stm32_adc_device, name_buf, &stm_adc_ops, &stm32_adc_obj[i].ADC_Handler) == RT_EOK)
|
||||
{
|
||||
LOG_D("%s init success", name_buf);
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_E("%s register failed", name_buf);
|
||||
result = -RT_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
INIT_BOARD_EXPORT(stm32_adc_init);
|
||||
|
||||
#endif /* BSP_USING_ADC */
|
||||
129
drivers/drv_clk.c
Normal file
129
drivers/drv_clk.c
Normal file
@ -0,0 +1,129 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2019, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-10-26 ChenYong first version
|
||||
* 2020-01-08 xiangxistu add HSI configuration
|
||||
*/
|
||||
|
||||
#include <board.h>
|
||||
#include <rtthread.h>
|
||||
#include <stm32f1xx.h>
|
||||
#include "drv_common.h"
|
||||
#define DBG_TAG "board"
|
||||
#define DBG_LVL DBG_INFO
|
||||
#include <rtdbg.h>
|
||||
|
||||
void system_clock_config(int target_freq_Mhz)
|
||||
{
|
||||
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
|
||||
/** Initializes the RCC Oscillators according to the specified parameters
|
||||
* in the RCC_OscInitTypeDef structure.
|
||||
*/
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
||||
RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
||||
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/** Initializes the CPU, AHB and APB buses clocks
|
||||
*/
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
||||
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
||||
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
// RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
// RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
//
|
||||
// /** Initializes the CPU, AHB and APB busses clocks
|
||||
// */
|
||||
// RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
|
||||
// RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
||||
// RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
||||
// RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
// RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
|
||||
//#if defined(STM32F100xB) || defined(STM32F100xE)
|
||||
// RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6;
|
||||
//#endif
|
||||
//#if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG)
|
||||
// RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
|
||||
//#endif
|
||||
//#if defined(STM32F102x6) || defined(STM32F102xB)
|
||||
// RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
|
||||
//#endif
|
||||
//#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
|
||||
// RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16;
|
||||
//#endif
|
||||
//#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
// RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
|
||||
//#endif
|
||||
// if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||||
// {
|
||||
// Error_Handler();
|
||||
// }
|
||||
// /** Initializes the CPU, AHB and APB busses clocks
|
||||
// */
|
||||
// RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
||||
// |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
||||
// RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
||||
// RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
||||
// RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
|
||||
// RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
||||
//
|
||||
//#if defined(STM32F100xB) || defined(STM32F100xE)
|
||||
// if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
|
||||
//#endif
|
||||
//#if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG)
|
||||
// if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
|
||||
//#endif
|
||||
//#if defined(STM32F102x6) || defined(STM32F102xB)
|
||||
// if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
|
||||
//#endif
|
||||
//#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
|
||||
// if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
|
||||
//#endif
|
||||
//#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
// if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
|
||||
//#endif
|
||||
// {
|
||||
// Error_Handler();
|
||||
// }
|
||||
}
|
||||
|
||||
int clock_information(void)
|
||||
{
|
||||
LOG_D("System Clock information");
|
||||
LOG_D("SYSCLK_Frequency = %d", HAL_RCC_GetSysClockFreq());
|
||||
LOG_D("HCLK_Frequency = %d", HAL_RCC_GetHCLKFreq());
|
||||
LOG_D("PCLK1_Frequency = %d", HAL_RCC_GetPCLK1Freq());
|
||||
LOG_D("PCLK2_Frequency = %d", HAL_RCC_GetPCLK2Freq());
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_BOARD_EXPORT(clock_information);
|
||||
|
||||
void clk_init(char *clk_source, int source_freq, int target_freq)
|
||||
{
|
||||
system_clock_config(target_freq);
|
||||
}
|
||||
|
||||
150
drivers/drv_common.c
Normal file
150
drivers/drv_common.c
Normal file
@ -0,0 +1,150 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-7 SummerGift first version
|
||||
*/
|
||||
|
||||
#include "drv_common.h"
|
||||
#include "board.h"
|
||||
|
||||
#ifdef RT_USING_FINSH
|
||||
#include <finsh.h>
|
||||
static void reboot(uint8_t argc, char **argv)
|
||||
{
|
||||
rt_hw_cpu_reset();
|
||||
}
|
||||
//FINSH_FUNCTION_EXPORT_ALIAS(reboot, __cmd_reboot, Reboot System);
|
||||
MSH_CMD_EXPORT(reboot, Reboot System);
|
||||
#endif /* RT_USING_FINSH */
|
||||
|
||||
/* SysTick configuration */
|
||||
void rt_hw_systick_init(void)
|
||||
{
|
||||
#if defined (SOC_SERIES_STM32H7)
|
||||
HAL_SYSTICK_Config((HAL_RCCEx_GetD1SysClockFreq()) / RT_TICK_PER_SECOND);
|
||||
#else
|
||||
HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / RT_TICK_PER_SECOND);
|
||||
#endif
|
||||
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
|
||||
HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* This is the timer interrupt service routine.
|
||||
*
|
||||
*/
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
HAL_IncTick();
|
||||
rt_tick_increase();
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
uint32_t HAL_GetTick(void)
|
||||
{
|
||||
return rt_tick_get() * 1000 / RT_TICK_PER_SECOND;
|
||||
}
|
||||
|
||||
void HAL_SuspendTick(void)
|
||||
{
|
||||
}
|
||||
|
||||
void HAL_ResumeTick(void)
|
||||
{
|
||||
}
|
||||
|
||||
void HAL_Delay(__IO uint32_t Delay)
|
||||
{
|
||||
}
|
||||
|
||||
/* re-implement tick interface for STM32 HAL */
|
||||
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
||||
{
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function is executed in case of error occurrence.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void _Error_Handler(char *s, int num)
|
||||
{
|
||||
/* USER CODE BEGIN Error_Handler */
|
||||
/* User can add his own implementation to report the HAL error return state */
|
||||
while(1)
|
||||
{
|
||||
}
|
||||
/* USER CODE END Error_Handler */
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will delay for some us.
|
||||
*
|
||||
* @param us the delay time of us
|
||||
*/
|
||||
void rt_hw_us_delay(rt_uint32_t us)
|
||||
{
|
||||
rt_uint32_t start, now, delta, reload, us_tick;
|
||||
start = SysTick->VAL;
|
||||
reload = SysTick->LOAD;
|
||||
us_tick = SystemCoreClock / 1000000UL;
|
||||
do {
|
||||
now = SysTick->VAL;
|
||||
delta = start > now ? start - now : reload + start - now;
|
||||
} while(delta < us_tick * us);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will initial STM32 board.
|
||||
*/
|
||||
void hw_board_init(char *clock_src, int32_t clock_src_freq, int32_t clock_target_freq)
|
||||
{
|
||||
extern void rt_hw_systick_init(void);
|
||||
extern void clk_init(char *clk_source, int source_freq, int target_freq);
|
||||
|
||||
#ifdef SCB_EnableICache
|
||||
/* Enable I-Cache---------------------------------------------------------*/
|
||||
SCB_EnableICache();
|
||||
#endif
|
||||
|
||||
#ifdef SCB_EnableDCache
|
||||
/* Enable D-Cache---------------------------------------------------------*/
|
||||
SCB_EnableDCache();
|
||||
#endif
|
||||
|
||||
/* HAL_Init() function is called at the beginning of the program */
|
||||
HAL_Init();
|
||||
|
||||
/* enable interrupt */
|
||||
__set_PRIMASK(0);
|
||||
/* System clock initialization */
|
||||
clk_init(clock_src, clock_src_freq, clock_target_freq);
|
||||
/* disbale interrupt */
|
||||
__set_PRIMASK(1);
|
||||
|
||||
rt_hw_systick_init();
|
||||
|
||||
/* Pin driver initialization is open by default */
|
||||
#ifdef RT_USING_PIN
|
||||
extern int rt_hw_pin_init(void);
|
||||
rt_hw_pin_init();
|
||||
#endif
|
||||
|
||||
/* USART driver initialization is open by default */
|
||||
#ifdef RT_USING_SERIAL
|
||||
extern int rt_hw_usart_init(void);
|
||||
rt_hw_usart_init();
|
||||
#endif
|
||||
|
||||
}
|
||||
667
drivers/drv_eth.c
Normal file
667
drivers/drv_eth.c
Normal file
@ -0,0 +1,667 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-19 SummerGift first version
|
||||
* 2018-12-25 zylx fix some bugs
|
||||
* 2019-06-10 SummerGift optimize PHY state detection process
|
||||
* 2019-09-03 xiaofan optimize link change detection process
|
||||
*/
|
||||
|
||||
#include<rtthread.h>
|
||||
#include<rtdevice.h>
|
||||
#include "board.h"
|
||||
#include "drv_config.h"
|
||||
|
||||
#ifdef BSP_USING_ETH
|
||||
|
||||
#include <netif/ethernetif.h>
|
||||
#include "lwipopts.h"
|
||||
#include "drv_eth.h"
|
||||
|
||||
/*
|
||||
* Emac driver uses CubeMX tool to generate emac and phy's configuration,
|
||||
* the configuration files can be found in CubeMX_Config folder.
|
||||
*/
|
||||
|
||||
/* debug option */
|
||||
//#define ETH_RX_DUMP
|
||||
//#define ETH_TX_DUMP
|
||||
//#define DRV_DEBUG
|
||||
#define LOG_TAG "drv.emac"
|
||||
#include <drv_log.h>
|
||||
|
||||
#define MAX_ADDR_LEN 6
|
||||
|
||||
struct rt_stm32_eth
|
||||
{
|
||||
/* inherit from ethernet device */
|
||||
struct eth_device parent;
|
||||
#ifndef PHY_USING_INTERRUPT_MODE
|
||||
rt_timer_t poll_link_timer;
|
||||
#endif
|
||||
|
||||
/* interface address info, hw address */
|
||||
rt_uint8_t dev_addr[MAX_ADDR_LEN];
|
||||
/* ETH_Speed */
|
||||
uint32_t ETH_Speed;
|
||||
/* ETH_Duplex_Mode */
|
||||
uint32_t ETH_Mode;
|
||||
};
|
||||
|
||||
static ETH_DMADescTypeDef *DMARxDscrTab, *DMATxDscrTab;
|
||||
static rt_uint8_t *Rx_Buff, *Tx_Buff;
|
||||
static ETH_HandleTypeDef EthHandle;
|
||||
static struct rt_stm32_eth stm32_eth_device;
|
||||
|
||||
#if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP)
|
||||
#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ')
|
||||
static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen)
|
||||
{
|
||||
unsigned char *buf = (unsigned char *)ptr;
|
||||
int i, j;
|
||||
|
||||
for (i = 0; i < buflen; i += 16)
|
||||
{
|
||||
rt_kprintf("%08X: ", i);
|
||||
|
||||
for (j = 0; j < 16; j++)
|
||||
if (i + j < buflen)
|
||||
rt_kprintf("%02X ", buf[i + j]);
|
||||
else
|
||||
rt_kprintf(" ");
|
||||
rt_kprintf(" ");
|
||||
|
||||
for (j = 0; j < 16; j++)
|
||||
if (i + j < buflen)
|
||||
rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.');
|
||||
rt_kprintf("\n");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
extern void phy_reset(void);
|
||||
/* EMAC initialization function */
|
||||
static rt_err_t rt_stm32_eth_init(rt_device_t dev)
|
||||
{
|
||||
__HAL_RCC_ETH_CLK_ENABLE();
|
||||
|
||||
phy_reset();
|
||||
|
||||
/* ETHERNET Configuration */
|
||||
EthHandle.Instance = ETH;
|
||||
EthHandle.Init.MACAddr = (rt_uint8_t *)&stm32_eth_device.dev_addr[0];
|
||||
EthHandle.Init.AutoNegotiation = ETH_AUTONEGOTIATION_DISABLE;
|
||||
EthHandle.Init.Speed = ETH_SPEED_100M;
|
||||
EthHandle.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
|
||||
EthHandle.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
|
||||
EthHandle.Init.RxMode = ETH_RXINTERRUPT_MODE;
|
||||
#ifdef RT_LWIP_USING_HW_CHECKSUM
|
||||
EthHandle.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;
|
||||
#else
|
||||
EthHandle.Init.ChecksumMode = ETH_CHECKSUM_BY_SOFTWARE;
|
||||
#endif
|
||||
|
||||
HAL_ETH_DeInit(&EthHandle);
|
||||
|
||||
/* configure ethernet peripheral (GPIOs, clocks, MAC, DMA) */
|
||||
if (HAL_ETH_Init(&EthHandle) != HAL_OK)
|
||||
{
|
||||
LOG_E("eth hardware init failed");
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_D("eth hardware init success");
|
||||
}
|
||||
|
||||
/* Initialize Tx Descriptors list: Chain Mode */
|
||||
HAL_ETH_DMATxDescListInit(&EthHandle, DMATxDscrTab, Tx_Buff, ETH_TXBUFNB);
|
||||
|
||||
/* Initialize Rx Descriptors list: Chain Mode */
|
||||
HAL_ETH_DMARxDescListInit(&EthHandle, DMARxDscrTab, Rx_Buff, ETH_RXBUFNB);
|
||||
|
||||
/* ETH interrupt Init */
|
||||
HAL_NVIC_SetPriority(ETH_IRQn, 0x07, 0);
|
||||
HAL_NVIC_EnableIRQ(ETH_IRQn);
|
||||
|
||||
/* Enable MAC and DMA transmission and reception */
|
||||
if (HAL_ETH_Start(&EthHandle) == HAL_OK)
|
||||
{
|
||||
LOG_D("emac hardware start");
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_E("emac hardware start faild");
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_stm32_eth_open(rt_device_t dev, rt_uint16_t oflag)
|
||||
{
|
||||
LOG_D("emac open");
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_stm32_eth_close(rt_device_t dev)
|
||||
{
|
||||
LOG_D("emac close");
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_size_t rt_stm32_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
|
||||
{
|
||||
LOG_D("emac read");
|
||||
rt_set_errno(-RT_ENOSYS);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static rt_size_t rt_stm32_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
|
||||
{
|
||||
LOG_D("emac write");
|
||||
rt_set_errno(-RT_ENOSYS);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static rt_err_t rt_stm32_eth_control(rt_device_t dev, int cmd, void *args)
|
||||
{
|
||||
switch (cmd)
|
||||
{
|
||||
case NIOCTL_GADDR:
|
||||
/* get mac address */
|
||||
if (args) rt_memcpy(args, stm32_eth_device.dev_addr, 6);
|
||||
else return -RT_ERROR;
|
||||
break;
|
||||
|
||||
default :
|
||||
break;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
/* ethernet device interface */
|
||||
/* transmit data*/
|
||||
rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
|
||||
{
|
||||
rt_err_t ret = RT_ERROR;
|
||||
HAL_StatusTypeDef state;
|
||||
struct pbuf *q;
|
||||
uint8_t *buffer = (uint8_t *)(EthHandle.TxDesc->Buffer1Addr);
|
||||
__IO ETH_DMADescTypeDef *DmaTxDesc;
|
||||
uint32_t framelength = 0;
|
||||
uint32_t bufferoffset = 0;
|
||||
uint32_t byteslefttocopy = 0;
|
||||
uint32_t payloadoffset = 0;
|
||||
|
||||
DmaTxDesc = EthHandle.TxDesc;
|
||||
bufferoffset = 0;
|
||||
|
||||
/* copy frame from pbufs to driver buffers */
|
||||
for (q = p; q != NULL; q = q->next)
|
||||
{
|
||||
/* Is this buffer available? If not, goto error */
|
||||
if ((DmaTxDesc->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
|
||||
{
|
||||
LOG_D("buffer not valid");
|
||||
ret = ERR_USE;
|
||||
goto error;
|
||||
}
|
||||
|
||||
/* Get bytes in current lwIP buffer */
|
||||
byteslefttocopy = q->len;
|
||||
payloadoffset = 0;
|
||||
|
||||
/* Check if the length of data to copy is bigger than Tx buffer size*/
|
||||
while ((byteslefttocopy + bufferoffset) > ETH_TX_BUF_SIZE)
|
||||
{
|
||||
/* Copy data to Tx buffer*/
|
||||
memcpy((uint8_t *)((uint8_t *)buffer + bufferoffset), (uint8_t *)((uint8_t *)q->payload + payloadoffset), (ETH_TX_BUF_SIZE - bufferoffset));
|
||||
|
||||
/* Point to next descriptor */
|
||||
DmaTxDesc = (ETH_DMADescTypeDef *)(DmaTxDesc->Buffer2NextDescAddr);
|
||||
|
||||
/* Check if the buffer is available */
|
||||
if ((DmaTxDesc->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
|
||||
{
|
||||
LOG_E("dma tx desc buffer is not valid");
|
||||
ret = ERR_USE;
|
||||
goto error;
|
||||
}
|
||||
|
||||
buffer = (uint8_t *)(DmaTxDesc->Buffer1Addr);
|
||||
|
||||
byteslefttocopy = byteslefttocopy - (ETH_TX_BUF_SIZE - bufferoffset);
|
||||
payloadoffset = payloadoffset + (ETH_TX_BUF_SIZE - bufferoffset);
|
||||
framelength = framelength + (ETH_TX_BUF_SIZE - bufferoffset);
|
||||
bufferoffset = 0;
|
||||
}
|
||||
|
||||
/* Copy the remaining bytes */
|
||||
memcpy((uint8_t *)((uint8_t *)buffer + bufferoffset), (uint8_t *)((uint8_t *)q->payload + payloadoffset), byteslefttocopy);
|
||||
bufferoffset = bufferoffset + byteslefttocopy;
|
||||
framelength = framelength + byteslefttocopy;
|
||||
}
|
||||
|
||||
#ifdef ETH_TX_DUMP
|
||||
dump_hex(buffer, p->tot_len);
|
||||
#endif
|
||||
|
||||
/* Prepare transmit descriptors to give to DMA */
|
||||
/* TODO Optimize data send speed*/
|
||||
LOG_D("transmit frame length :%d", framelength);
|
||||
|
||||
/* wait for unlocked */
|
||||
while (EthHandle.Lock == HAL_LOCKED);
|
||||
|
||||
state = HAL_ETH_TransmitFrame(&EthHandle, framelength);
|
||||
if (state != HAL_OK)
|
||||
{
|
||||
LOG_E("eth transmit frame faild: %d", state);
|
||||
}
|
||||
|
||||
ret = ERR_OK;
|
||||
|
||||
error:
|
||||
|
||||
/* When Transmit Underflow flag is set, clear it and issue a Transmit Poll Demand to resume transmission */
|
||||
if ((EthHandle.Instance->DMASR & ETH_DMASR_TUS) != (uint32_t)RESET)
|
||||
{
|
||||
/* Clear TUS ETHERNET DMA flag */
|
||||
EthHandle.Instance->DMASR = ETH_DMASR_TUS;
|
||||
|
||||
/* Resume DMA transmission*/
|
||||
EthHandle.Instance->DMATPDR = 0;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* receive data*/
|
||||
struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
|
||||
{
|
||||
|
||||
struct pbuf *p = NULL;
|
||||
struct pbuf *q = NULL;
|
||||
HAL_StatusTypeDef state;
|
||||
uint16_t len = 0;
|
||||
uint8_t *buffer;
|
||||
__IO ETH_DMADescTypeDef *dmarxdesc;
|
||||
uint32_t bufferoffset = 0;
|
||||
uint32_t payloadoffset = 0;
|
||||
uint32_t byteslefttocopy = 0;
|
||||
uint32_t i = 0;
|
||||
|
||||
/* Get received frame */
|
||||
state = HAL_ETH_GetReceivedFrame_IT(&EthHandle);
|
||||
if (state != HAL_OK)
|
||||
{
|
||||
LOG_D("receive frame faild");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Obtain the size of the packet and put it into the "len" variable. */
|
||||
len = EthHandle.RxFrameInfos.length;
|
||||
buffer = (uint8_t *)EthHandle.RxFrameInfos.buffer;
|
||||
|
||||
LOG_D("receive frame len : %d", len);
|
||||
|
||||
if (len > 0)
|
||||
{
|
||||
/* We allocate a pbuf chain of pbufs from the Lwip buffer pool */
|
||||
p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
|
||||
}
|
||||
|
||||
#ifdef ETH_RX_DUMP
|
||||
dump_hex(buffer, p->tot_len);
|
||||
#endif
|
||||
|
||||
if (p != NULL)
|
||||
{
|
||||
dmarxdesc = EthHandle.RxFrameInfos.FSRxDesc;
|
||||
bufferoffset = 0;
|
||||
for (q = p; q != NULL; q = q->next)
|
||||
{
|
||||
byteslefttocopy = q->len;
|
||||
payloadoffset = 0;
|
||||
|
||||
/* Check if the length of bytes to copy in current pbuf is bigger than Rx buffer size*/
|
||||
while ((byteslefttocopy + bufferoffset) > ETH_RX_BUF_SIZE)
|
||||
{
|
||||
/* Copy data to pbuf */
|
||||
memcpy((uint8_t *)((uint8_t *)q->payload + payloadoffset), (uint8_t *)((uint8_t *)buffer + bufferoffset), (ETH_RX_BUF_SIZE - bufferoffset));
|
||||
|
||||
/* Point to next descriptor */
|
||||
dmarxdesc = (ETH_DMADescTypeDef *)(dmarxdesc->Buffer2NextDescAddr);
|
||||
buffer = (uint8_t *)(dmarxdesc->Buffer1Addr);
|
||||
|
||||
byteslefttocopy = byteslefttocopy - (ETH_RX_BUF_SIZE - bufferoffset);
|
||||
payloadoffset = payloadoffset + (ETH_RX_BUF_SIZE - bufferoffset);
|
||||
bufferoffset = 0;
|
||||
}
|
||||
/* Copy remaining data in pbuf */
|
||||
memcpy((uint8_t *)((uint8_t *)q->payload + payloadoffset), (uint8_t *)((uint8_t *)buffer + bufferoffset), byteslefttocopy);
|
||||
bufferoffset = bufferoffset + byteslefttocopy;
|
||||
}
|
||||
}
|
||||
|
||||
/* Release descriptors to DMA */
|
||||
/* Point to first descriptor */
|
||||
dmarxdesc = EthHandle.RxFrameInfos.FSRxDesc;
|
||||
/* Set Own bit in Rx descriptors: gives the buffers back to DMA */
|
||||
for (i = 0; i < EthHandle.RxFrameInfos.SegCount; i++)
|
||||
{
|
||||
dmarxdesc->Status |= ETH_DMARXDESC_OWN;
|
||||
dmarxdesc = (ETH_DMADescTypeDef *)(dmarxdesc->Buffer2NextDescAddr);
|
||||
}
|
||||
|
||||
/* Clear Segment_Count */
|
||||
EthHandle.RxFrameInfos.SegCount = 0;
|
||||
|
||||
/* When Rx Buffer unavailable flag is set: clear it and resume reception */
|
||||
if ((EthHandle.Instance->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET)
|
||||
{
|
||||
/* Clear RBUS ETHERNET DMA flag */
|
||||
EthHandle.Instance->DMASR = ETH_DMASR_RBUS;
|
||||
/* Resume DMA reception */
|
||||
EthHandle.Instance->DMARPDR = 0;
|
||||
}
|
||||
|
||||
return p;
|
||||
}
|
||||
|
||||
/* interrupt service routine */
|
||||
void ETH_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
HAL_ETH_IRQHandler(&EthHandle);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
|
||||
{
|
||||
rt_err_t result;
|
||||
result = eth_device_ready(&(stm32_eth_device.parent));
|
||||
if (result != RT_EOK)
|
||||
LOG_I("RxCpltCallback err = %d", result);
|
||||
}
|
||||
|
||||
void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
|
||||
{
|
||||
LOG_E("eth err");
|
||||
}
|
||||
|
||||
enum {
|
||||
PHY_LINK = (1 << 0),
|
||||
PHY_100M = (1 << 1),
|
||||
PHY_FULL_DUPLEX = (1 << 2),
|
||||
};
|
||||
|
||||
static void phy_linkchange()
|
||||
{
|
||||
static rt_uint8_t phy_speed = 0;
|
||||
rt_uint8_t phy_speed_new = 0;
|
||||
rt_uint32_t status;
|
||||
|
||||
HAL_ETH_ReadPHYRegister(&EthHandle, PHY_BASIC_STATUS_REG, (uint32_t *)&status);
|
||||
LOG_D("phy basic status reg is 0x%X", status);
|
||||
|
||||
if (status & (PHY_AUTONEGO_COMPLETE_MASK | PHY_LINKED_STATUS_MASK))
|
||||
{
|
||||
rt_uint32_t SR = 0;
|
||||
|
||||
phy_speed_new |= PHY_LINK;
|
||||
|
||||
HAL_ETH_ReadPHYRegister(&EthHandle, PHY_Status_REG, (uint32_t *)&SR);
|
||||
LOG_D("phy control status reg is 0x%X", SR);
|
||||
|
||||
if (PHY_Status_SPEED_100M(SR))
|
||||
{
|
||||
phy_speed_new |= PHY_100M;
|
||||
}
|
||||
|
||||
if (PHY_Status_FULL_DUPLEX(SR))
|
||||
{
|
||||
phy_speed_new |= PHY_FULL_DUPLEX;
|
||||
}
|
||||
}
|
||||
|
||||
if (phy_speed != phy_speed_new)
|
||||
{
|
||||
phy_speed = phy_speed_new;
|
||||
if (phy_speed & PHY_LINK)
|
||||
{
|
||||
LOG_D("link up");
|
||||
if (phy_speed & PHY_100M)
|
||||
{
|
||||
LOG_D("100Mbps");
|
||||
stm32_eth_device.ETH_Speed = ETH_SPEED_100M;
|
||||
}
|
||||
else
|
||||
{
|
||||
stm32_eth_device.ETH_Speed = ETH_SPEED_10M;
|
||||
LOG_D("10Mbps");
|
||||
}
|
||||
|
||||
if (phy_speed & PHY_FULL_DUPLEX)
|
||||
{
|
||||
LOG_D("full-duplex");
|
||||
stm32_eth_device.ETH_Mode = ETH_MODE_FULLDUPLEX;
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_D("half-duplex");
|
||||
stm32_eth_device.ETH_Mode = ETH_MODE_HALFDUPLEX;
|
||||
}
|
||||
|
||||
/* send link up. */
|
||||
eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE);
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_I("link down");
|
||||
eth_device_linkchange(&stm32_eth_device.parent, RT_FALSE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef PHY_USING_INTERRUPT_MODE
|
||||
static void eth_phy_isr(void *args)
|
||||
{
|
||||
rt_uint32_t status = 0;
|
||||
|
||||
HAL_ETH_ReadPHYRegister(&EthHandle, PHY_INTERRUPT_FLAG_REG, (uint32_t *)&status);
|
||||
LOG_D("phy interrupt status reg is 0x%X", status);
|
||||
|
||||
phy_linkchange();
|
||||
}
|
||||
#endif /* PHY_USING_INTERRUPT_MODE */
|
||||
|
||||
static void phy_monitor_thread_entry(void *parameter)
|
||||
{
|
||||
uint8_t phy_addr = 0xFF;
|
||||
uint8_t detected_count = 0;
|
||||
|
||||
while(phy_addr == 0xFF)
|
||||
{
|
||||
/* phy search */
|
||||
rt_uint32_t i, temp;
|
||||
for (i = 0; i <= 0x1F; i++)
|
||||
{
|
||||
EthHandle.Init.PhyAddress = i;
|
||||
HAL_ETH_ReadPHYRegister(&EthHandle, PHY_ID1_REG, (uint32_t *)&temp);
|
||||
|
||||
if (temp != 0xFFFF && temp != 0x00)
|
||||
{
|
||||
phy_addr = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
detected_count++;
|
||||
rt_thread_mdelay(1000);
|
||||
|
||||
if (detected_count > 10)
|
||||
{
|
||||
LOG_E("No PHY device was detected, please check hardware!");
|
||||
}
|
||||
}
|
||||
|
||||
LOG_D("Found a phy, address:0x%02X", phy_addr);
|
||||
|
||||
/* RESET PHY */
|
||||
LOG_D("RESET PHY!");
|
||||
HAL_ETH_WritePHYRegister(&EthHandle, PHY_BASIC_CONTROL_REG, PHY_RESET_MASK);
|
||||
rt_thread_mdelay(2000);
|
||||
HAL_ETH_WritePHYRegister(&EthHandle, PHY_BASIC_CONTROL_REG, PHY_AUTO_NEGOTIATION_MASK);
|
||||
|
||||
phy_linkchange();
|
||||
#ifdef PHY_USING_INTERRUPT_MODE
|
||||
/* configuration intterrupt pin */
|
||||
rt_pin_mode(PHY_INT_PIN, PIN_MODE_INPUT_PULLUP);
|
||||
rt_pin_attach_irq(PHY_INT_PIN, PIN_IRQ_MODE_FALLING, eth_phy_isr, (void *)"callbackargs");
|
||||
rt_pin_irq_enable(PHY_INT_PIN, PIN_IRQ_ENABLE);
|
||||
|
||||
/* enable phy interrupt */
|
||||
HAL_ETH_WritePHYRegister(&EthHandle, PHY_INTERRUPT_MASK_REG, PHY_INT_MASK);
|
||||
#if defined(PHY_INTERRUPT_CTRL_REG)
|
||||
HAL_ETH_WritePHYRegister(&EthHandle, PHY_INTERRUPT_CTRL_REG, PHY_INTERRUPT_EN);
|
||||
#endif
|
||||
#else /* PHY_USING_INTERRUPT_MODE */
|
||||
stm32_eth_device.poll_link_timer = rt_timer_create("phylnk", (void (*)(void*))phy_linkchange,
|
||||
NULL, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC);
|
||||
if (!stm32_eth_device.poll_link_timer || rt_timer_start(stm32_eth_device.poll_link_timer) != RT_EOK)
|
||||
{
|
||||
LOG_E("Start link change detection timer failed");
|
||||
}
|
||||
#endif /* PHY_USING_INTERRUPT_MODE */
|
||||
}
|
||||
|
||||
/* Register the EMAC device */
|
||||
static int rt_hw_stm32_eth_init(void)
|
||||
{
|
||||
rt_err_t state = RT_EOK;
|
||||
|
||||
/* Prepare receive and send buffers */
|
||||
Rx_Buff = (rt_uint8_t *)rt_calloc(ETH_RXBUFNB, ETH_MAX_PACKET_SIZE);
|
||||
if (Rx_Buff == RT_NULL)
|
||||
{
|
||||
LOG_E("No memory");
|
||||
state = -RT_ENOMEM;
|
||||
goto __exit;
|
||||
}
|
||||
|
||||
Tx_Buff = (rt_uint8_t *)rt_calloc(ETH_TXBUFNB, ETH_MAX_PACKET_SIZE);
|
||||
if (Tx_Buff == RT_NULL)
|
||||
{
|
||||
LOG_E("No memory");
|
||||
state = -RT_ENOMEM;
|
||||
goto __exit;
|
||||
}
|
||||
|
||||
DMARxDscrTab = (ETH_DMADescTypeDef *)rt_calloc(ETH_RXBUFNB, sizeof(ETH_DMADescTypeDef));
|
||||
if (DMARxDscrTab == RT_NULL)
|
||||
{
|
||||
LOG_E("No memory");
|
||||
state = -RT_ENOMEM;
|
||||
goto __exit;
|
||||
}
|
||||
|
||||
DMATxDscrTab = (ETH_DMADescTypeDef *)rt_calloc(ETH_TXBUFNB, sizeof(ETH_DMADescTypeDef));
|
||||
if (DMATxDscrTab == RT_NULL)
|
||||
{
|
||||
LOG_E("No memory");
|
||||
state = -RT_ENOMEM;
|
||||
goto __exit;
|
||||
}
|
||||
|
||||
stm32_eth_device.ETH_Speed = ETH_SPEED_100M;
|
||||
stm32_eth_device.ETH_Mode = ETH_MODE_FULLDUPLEX;
|
||||
|
||||
/* OUI 00-80-E1 STMICROELECTRONICS. */
|
||||
stm32_eth_device.dev_addr[0] = 0x00;
|
||||
stm32_eth_device.dev_addr[1] = 0x80;
|
||||
stm32_eth_device.dev_addr[2] = 0xE1;
|
||||
/* generate MAC addr from 96bit unique ID (only for test). */
|
||||
stm32_eth_device.dev_addr[3] = *(rt_uint8_t *)(UID_BASE + 4);
|
||||
stm32_eth_device.dev_addr[4] = *(rt_uint8_t *)(UID_BASE + 2);
|
||||
stm32_eth_device.dev_addr[5] = *(rt_uint8_t *)(UID_BASE + 0);
|
||||
|
||||
stm32_eth_device.parent.parent.init = rt_stm32_eth_init;
|
||||
stm32_eth_device.parent.parent.open = rt_stm32_eth_open;
|
||||
stm32_eth_device.parent.parent.close = rt_stm32_eth_close;
|
||||
stm32_eth_device.parent.parent.read = rt_stm32_eth_read;
|
||||
stm32_eth_device.parent.parent.write = rt_stm32_eth_write;
|
||||
stm32_eth_device.parent.parent.control = rt_stm32_eth_control;
|
||||
stm32_eth_device.parent.parent.user_data = RT_NULL;
|
||||
|
||||
stm32_eth_device.parent.eth_rx = rt_stm32_eth_rx;
|
||||
stm32_eth_device.parent.eth_tx = rt_stm32_eth_tx;
|
||||
|
||||
/* register eth device */
|
||||
state = eth_device_init(&(stm32_eth_device.parent), "e0");
|
||||
if (RT_EOK == state)
|
||||
{
|
||||
LOG_D("emac device init success");
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_E("emac device init faild: %d", state);
|
||||
state = -RT_ERROR;
|
||||
goto __exit;
|
||||
}
|
||||
|
||||
/* start phy monitor */
|
||||
rt_thread_t tid;
|
||||
tid = rt_thread_create("phy",
|
||||
phy_monitor_thread_entry,
|
||||
RT_NULL,
|
||||
1024,
|
||||
RT_THREAD_PRIORITY_MAX - 2,
|
||||
2);
|
||||
if (tid != RT_NULL)
|
||||
{
|
||||
rt_thread_startup(tid);
|
||||
}
|
||||
else
|
||||
{
|
||||
state = -RT_ERROR;
|
||||
}
|
||||
__exit:
|
||||
if (state != RT_EOK)
|
||||
{
|
||||
if (Rx_Buff)
|
||||
{
|
||||
rt_free(Rx_Buff);
|
||||
}
|
||||
|
||||
if (Tx_Buff)
|
||||
{
|
||||
rt_free(Tx_Buff);
|
||||
}
|
||||
|
||||
if (DMARxDscrTab)
|
||||
{
|
||||
rt_free(DMARxDscrTab);
|
||||
}
|
||||
|
||||
if (DMATxDscrTab)
|
||||
{
|
||||
rt_free(DMATxDscrTab);
|
||||
}
|
||||
}
|
||||
|
||||
return state;
|
||||
}
|
||||
INIT_DEVICE_EXPORT(rt_hw_stm32_eth_init);
|
||||
|
||||
#endif /* BSP_USING_ETH */
|
||||
|
||||
273
drivers/drv_flash_f1.c
Normal file
273
drivers/drv_flash_f1.c
Normal file
@ -0,0 +1,273 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-5 SummerGift first version
|
||||
* 2020-03-05 redoc support stm32f103vg
|
||||
*
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
|
||||
#ifdef BSP_USING_ON_CHIP_FLASH
|
||||
#include "drv_config.h"
|
||||
#include "drv_flash.h"
|
||||
|
||||
#if defined(PKG_USING_FAL)
|
||||
#include "fal.h"
|
||||
#endif
|
||||
|
||||
//#define DRV_DEBUG
|
||||
#define LOG_TAG "drv.flash"
|
||||
#include <drv_log.h>
|
||||
|
||||
/**
|
||||
* @brief Gets the page of a given address
|
||||
* @param Addr: Address of the FLASH Memory
|
||||
* @retval The page of a given address
|
||||
*/
|
||||
static uint32_t GetPage(uint32_t addr)
|
||||
{
|
||||
uint32_t page = 0;
|
||||
page = RT_ALIGN_DOWN(addr, FLASH_PAGE_SIZE);
|
||||
return page;
|
||||
}
|
||||
|
||||
/**
|
||||
* Read data from flash.
|
||||
* @note This operation's units is word.
|
||||
*
|
||||
* @param addr flash address
|
||||
* @param buf buffer to store read data
|
||||
* @param size read bytes size
|
||||
*
|
||||
* @return result
|
||||
*/
|
||||
int stm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
size_t i;
|
||||
|
||||
if ((addr + size) > STM32_FLASH_END_ADDRESS)
|
||||
{
|
||||
LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size));
|
||||
return -RT_EINVAL;
|
||||
}
|
||||
|
||||
for (i = 0; i < size; i++, buf++, addr++)
|
||||
{
|
||||
*buf = *(rt_uint8_t *) addr;
|
||||
}
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
/**
|
||||
* Write data to flash.
|
||||
* @note This operation's units is word.
|
||||
* @note This operation must after erase. @see flash_erase.
|
||||
*
|
||||
* @param addr flash address
|
||||
* @param buf the write data buffer
|
||||
* @param size write bytes size
|
||||
*
|
||||
* @return result
|
||||
*/
|
||||
int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
rt_uint32_t end_addr = addr + size;
|
||||
|
||||
if (addr % 4 != 0)
|
||||
{
|
||||
LOG_E("write addr must be 4-byte alignment");
|
||||
return -RT_EINVAL;
|
||||
}
|
||||
|
||||
if ((end_addr) > STM32_FLASH_END_ADDRESS)
|
||||
{
|
||||
LOG_E("write outrange flash size! addr is (0x%p)", (void *)(addr + size));
|
||||
return -RT_EINVAL;
|
||||
}
|
||||
|
||||
HAL_FLASH_Unlock();
|
||||
|
||||
while (addr < end_addr)
|
||||
{
|
||||
if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, addr, *((rt_uint32_t *)buf)) == HAL_OK)
|
||||
{
|
||||
if (*(rt_uint32_t *)addr != *(rt_uint32_t *)buf)
|
||||
{
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
addr += 4;
|
||||
buf += 4;
|
||||
}
|
||||
else
|
||||
{
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
HAL_FLASH_Lock();
|
||||
|
||||
if (result != RT_EOK)
|
||||
{
|
||||
return result;
|
||||
}
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
/**
|
||||
* Erase data on flash with bank.
|
||||
* @note This operation is irreversible.
|
||||
* @note This operation's units is different which on many chips.
|
||||
*
|
||||
* @param bank flash bank
|
||||
* @param addr flash address
|
||||
* @param size erase bytes size
|
||||
*
|
||||
* @return result
|
||||
*/
|
||||
int stm32_flash_erase_bank(uint32_t bank, rt_uint32_t addr, size_t size)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
uint32_t PAGEError = 0;
|
||||
|
||||
/*Variable used for Erase procedure*/
|
||||
FLASH_EraseInitTypeDef EraseInitStruct;
|
||||
|
||||
if ((addr + size) > STM32_FLASH_END_ADDRESS)
|
||||
{
|
||||
LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
|
||||
return -RT_EINVAL;
|
||||
}
|
||||
|
||||
HAL_FLASH_Unlock();
|
||||
|
||||
/* Fill EraseInit structure*/
|
||||
EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES;
|
||||
EraseInitStruct.PageAddress = GetPage(addr);
|
||||
EraseInitStruct.NbPages = (size + FLASH_PAGE_SIZE - 1) / FLASH_PAGE_SIZE;
|
||||
EraseInitStruct.Banks = bank;
|
||||
|
||||
if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK)
|
||||
{
|
||||
result = -RT_ERROR;
|
||||
goto __exit;
|
||||
}
|
||||
|
||||
__exit:
|
||||
HAL_FLASH_Lock();
|
||||
|
||||
if (result != RT_EOK)
|
||||
{
|
||||
return result;
|
||||
}
|
||||
|
||||
LOG_D("erase done: addr (0x%p), size %d", (void *)addr, size);
|
||||
return size;
|
||||
}
|
||||
|
||||
/**
|
||||
* Erase data on flash .
|
||||
* @note This operation is irreversible.
|
||||
* @note This operation's units is different which on many chips.
|
||||
*
|
||||
* @param addr flash address
|
||||
* @param size erase bytes size
|
||||
*
|
||||
* @return result
|
||||
*/
|
||||
int stm32_flash_erase(rt_uint32_t addr, size_t size)
|
||||
{
|
||||
#if defined(FLASH_BANK2_END)
|
||||
rt_err_t result = RT_EOK;
|
||||
rt_uint32_t addr_bank1 = 0;
|
||||
rt_uint32_t size_bank1 = 0;
|
||||
rt_uint32_t addr_bank2 = 0;
|
||||
rt_uint32_t size_bank2 = 0;
|
||||
|
||||
if((addr + size) <= FLASH_BANK1_END)
|
||||
{
|
||||
addr_bank1 = addr;
|
||||
size_bank1 = size;
|
||||
size_bank2 = 0;
|
||||
}
|
||||
else if(addr > FLASH_BANK1_END)
|
||||
{
|
||||
size_bank1 = 0;
|
||||
addr_bank2 = addr;
|
||||
size_bank2 = size;
|
||||
}
|
||||
else
|
||||
{
|
||||
addr_bank1 = addr;
|
||||
size_bank1 = FLASH_BANK1_END + 1 - addr_bank1;
|
||||
addr_bank2 = FLASH_BANK1_END + 1;
|
||||
size_bank2 = addr + size - (FLASH_BANK1_END + 1);
|
||||
}
|
||||
|
||||
if(size_bank1)
|
||||
{
|
||||
LOG_D("bank1: addr (0x%p), size %d", (void *)addr_bank1, size_bank1);
|
||||
if(size_bank1 != stm32_flash_erase_bank(FLASH_BANK_1, addr_bank1, size_bank1))
|
||||
{
|
||||
result = -RT_ERROR;
|
||||
goto __exit;
|
||||
}
|
||||
}
|
||||
|
||||
if(size_bank2)
|
||||
{
|
||||
LOG_D("bank2: addr (0x%p), size %d", (void *)addr_bank2, size_bank2);
|
||||
if(size_bank2 != stm32_flash_erase_bank(FLASH_BANK_2, addr_bank2, size_bank2))
|
||||
{
|
||||
result = -RT_ERROR;
|
||||
goto __exit;
|
||||
}
|
||||
}
|
||||
|
||||
__exit:
|
||||
if(result != RT_EOK)
|
||||
{
|
||||
return result;
|
||||
}
|
||||
|
||||
return size_bank1 + size_bank2;
|
||||
#else
|
||||
return stm32_flash_erase_bank(FLASH_BANK_1, addr, size);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
#if defined(PKG_USING_FAL)
|
||||
|
||||
static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size);
|
||||
static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size);
|
||||
static int fal_flash_erase(long offset, size_t size);
|
||||
|
||||
const struct fal_flash_dev stm32_onchip_flash = { "onchip_flash", STM32_FLASH_START_ADRESS, STM32_FLASH_SIZE, FLASH_PAGE_SIZE, {NULL, fal_flash_read, fal_flash_write, fal_flash_erase} };
|
||||
|
||||
static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
return stm32_flash_read(stm32_onchip_flash.addr + offset, buf, size);
|
||||
}
|
||||
|
||||
static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size)
|
||||
{
|
||||
return stm32_flash_write(stm32_onchip_flash.addr + offset, buf, size);
|
||||
}
|
||||
|
||||
static int fal_flash_erase(long offset, size_t size)
|
||||
{
|
||||
return stm32_flash_erase(stm32_onchip_flash.addr + offset, size);
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif /* BSP_USING_ON_CHIP_FLASH */
|
||||
811
drivers/drv_gpio.c
Normal file
811
drivers/drv_gpio.c
Normal file
@ -0,0 +1,811 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-06 balanceTWK first version
|
||||
* 2019-04-23 WillianChan Fix GPIO serial number disorder
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
#include "drv_common.h"
|
||||
|
||||
#ifdef RT_USING_PIN
|
||||
|
||||
#include <rtdevice.h>
|
||||
|
||||
#define __STM32_PIN(index, gpio, gpio_index) \
|
||||
{ \
|
||||
index, GPIO##gpio, GPIO_PIN_##gpio_index \
|
||||
}
|
||||
|
||||
#define __STM32_PIN_RESERVE \
|
||||
{ \
|
||||
-1, 0, 0 \
|
||||
}
|
||||
|
||||
/* STM32 GPIO driver */
|
||||
struct pin_index
|
||||
{
|
||||
int index;
|
||||
GPIO_TypeDef *gpio;
|
||||
uint32_t pin;
|
||||
};
|
||||
|
||||
struct pin_irq_map
|
||||
{
|
||||
rt_uint16_t pinbit;
|
||||
IRQn_Type irqno;
|
||||
};
|
||||
|
||||
|
||||
static const struct pin_index pins[] =
|
||||
{
|
||||
#if defined(GPIOA)
|
||||
__STM32_PIN(0 , A, 0 ),
|
||||
__STM32_PIN(1 , A, 1 ),
|
||||
__STM32_PIN(2 , A, 2 ),
|
||||
__STM32_PIN(3 , A, 3 ),
|
||||
__STM32_PIN(4 , A, 4 ),
|
||||
__STM32_PIN(5 , A, 5 ),
|
||||
__STM32_PIN(6 , A, 6 ),
|
||||
__STM32_PIN(7 , A, 7 ),
|
||||
__STM32_PIN(8 , A, 8 ),
|
||||
__STM32_PIN(9 , A, 9 ),
|
||||
__STM32_PIN(10, A, 10),
|
||||
__STM32_PIN(11, A, 11),
|
||||
__STM32_PIN(12, A, 12),
|
||||
__STM32_PIN(13, A, 13),
|
||||
__STM32_PIN(14, A, 14),
|
||||
__STM32_PIN(15, A, 15),
|
||||
#if defined(GPIOB)
|
||||
__STM32_PIN(16, B, 0),
|
||||
__STM32_PIN(17, B, 1),
|
||||
__STM32_PIN(18, B, 2),
|
||||
__STM32_PIN(19, B, 3),
|
||||
__STM32_PIN(20, B, 4),
|
||||
__STM32_PIN(21, B, 5),
|
||||
__STM32_PIN(22, B, 6),
|
||||
__STM32_PIN(23, B, 7),
|
||||
__STM32_PIN(24, B, 8),
|
||||
__STM32_PIN(25, B, 9),
|
||||
__STM32_PIN(26, B, 10),
|
||||
__STM32_PIN(27, B, 11),
|
||||
__STM32_PIN(28, B, 12),
|
||||
__STM32_PIN(29, B, 13),
|
||||
__STM32_PIN(30, B, 14),
|
||||
__STM32_PIN(31, B, 15),
|
||||
#if defined(GPIOC)
|
||||
__STM32_PIN(32, C, 0),
|
||||
__STM32_PIN(33, C, 1),
|
||||
__STM32_PIN(34, C, 2),
|
||||
__STM32_PIN(35, C, 3),
|
||||
__STM32_PIN(36, C, 4),
|
||||
__STM32_PIN(37, C, 5),
|
||||
__STM32_PIN(38, C, 6),
|
||||
__STM32_PIN(39, C, 7),
|
||||
__STM32_PIN(40, C, 8),
|
||||
__STM32_PIN(41, C, 9),
|
||||
__STM32_PIN(42, C, 10),
|
||||
__STM32_PIN(43, C, 11),
|
||||
__STM32_PIN(44, C, 12),
|
||||
__STM32_PIN(45, C, 13),
|
||||
__STM32_PIN(46, C, 14),
|
||||
__STM32_PIN(47, C, 15),
|
||||
#if defined(GPIOD)
|
||||
__STM32_PIN(48, D, 0),
|
||||
__STM32_PIN(49, D, 1),
|
||||
__STM32_PIN(50, D, 2),
|
||||
__STM32_PIN(51, D, 3),
|
||||
__STM32_PIN(52, D, 4),
|
||||
__STM32_PIN(53, D, 5),
|
||||
__STM32_PIN(54, D, 6),
|
||||
__STM32_PIN(55, D, 7),
|
||||
__STM32_PIN(56, D, 8),
|
||||
__STM32_PIN(57, D, 9),
|
||||
__STM32_PIN(58, D, 10),
|
||||
__STM32_PIN(59, D, 11),
|
||||
__STM32_PIN(60, D, 12),
|
||||
__STM32_PIN(61, D, 13),
|
||||
__STM32_PIN(62, D, 14),
|
||||
__STM32_PIN(63, D, 15),
|
||||
#if defined(GPIOE)
|
||||
__STM32_PIN(64, E, 0),
|
||||
__STM32_PIN(65, E, 1),
|
||||
__STM32_PIN(66, E, 2),
|
||||
__STM32_PIN(67, E, 3),
|
||||
__STM32_PIN(68, E, 4),
|
||||
__STM32_PIN(69, E, 5),
|
||||
__STM32_PIN(70, E, 6),
|
||||
__STM32_PIN(71, E, 7),
|
||||
__STM32_PIN(72, E, 8),
|
||||
__STM32_PIN(73, E, 9),
|
||||
__STM32_PIN(74, E, 10),
|
||||
__STM32_PIN(75, E, 11),
|
||||
__STM32_PIN(76, E, 12),
|
||||
__STM32_PIN(77, E, 13),
|
||||
__STM32_PIN(78, E, 14),
|
||||
__STM32_PIN(79, E, 15),
|
||||
#if defined(GPIOF)
|
||||
__STM32_PIN(80, F, 0),
|
||||
__STM32_PIN(81, F, 1),
|
||||
__STM32_PIN(82, F, 2),
|
||||
__STM32_PIN(83, F, 3),
|
||||
__STM32_PIN(84, F, 4),
|
||||
__STM32_PIN(85, F, 5),
|
||||
__STM32_PIN(86, F, 6),
|
||||
__STM32_PIN(87, F, 7),
|
||||
__STM32_PIN(88, F, 8),
|
||||
__STM32_PIN(89, F, 9),
|
||||
__STM32_PIN(90, F, 10),
|
||||
__STM32_PIN(91, F, 11),
|
||||
__STM32_PIN(92, F, 12),
|
||||
__STM32_PIN(93, F, 13),
|
||||
__STM32_PIN(94, F, 14),
|
||||
__STM32_PIN(95, F, 15),
|
||||
#if defined(GPIOG)
|
||||
__STM32_PIN(96, G, 0),
|
||||
__STM32_PIN(97, G, 1),
|
||||
__STM32_PIN(98, G, 2),
|
||||
__STM32_PIN(99, G, 3),
|
||||
__STM32_PIN(100, G, 4),
|
||||
__STM32_PIN(101, G, 5),
|
||||
__STM32_PIN(102, G, 6),
|
||||
__STM32_PIN(103, G, 7),
|
||||
__STM32_PIN(104, G, 8),
|
||||
__STM32_PIN(105, G, 9),
|
||||
__STM32_PIN(106, G, 10),
|
||||
__STM32_PIN(107, G, 11),
|
||||
__STM32_PIN(108, G, 12),
|
||||
__STM32_PIN(109, G, 13),
|
||||
__STM32_PIN(110, G, 14),
|
||||
__STM32_PIN(111, G, 15),
|
||||
#if defined(GPIOH)
|
||||
__STM32_PIN(112, H, 0),
|
||||
__STM32_PIN(113, H, 1),
|
||||
__STM32_PIN(114, H, 2),
|
||||
__STM32_PIN(115, H, 3),
|
||||
__STM32_PIN(116, H, 4),
|
||||
__STM32_PIN(117, H, 5),
|
||||
__STM32_PIN(118, H, 6),
|
||||
__STM32_PIN(119, H, 7),
|
||||
__STM32_PIN(120, H, 8),
|
||||
__STM32_PIN(121, H, 9),
|
||||
__STM32_PIN(122, H, 10),
|
||||
__STM32_PIN(123, H, 11),
|
||||
__STM32_PIN(124, H, 12),
|
||||
__STM32_PIN(125, H, 13),
|
||||
__STM32_PIN(126, H, 14),
|
||||
__STM32_PIN(127, H, 15),
|
||||
#if defined(GPIOI)
|
||||
__STM32_PIN(128, I, 0),
|
||||
__STM32_PIN(129, I, 1),
|
||||
__STM32_PIN(130, I, 2),
|
||||
__STM32_PIN(131, I, 3),
|
||||
__STM32_PIN(132, I, 4),
|
||||
__STM32_PIN(133, I, 5),
|
||||
__STM32_PIN(134, I, 6),
|
||||
__STM32_PIN(135, I, 7),
|
||||
__STM32_PIN(136, I, 8),
|
||||
__STM32_PIN(137, I, 9),
|
||||
__STM32_PIN(138, I, 10),
|
||||
__STM32_PIN(139, I, 11),
|
||||
__STM32_PIN(140, I, 12),
|
||||
__STM32_PIN(141, I, 13),
|
||||
__STM32_PIN(142, I, 14),
|
||||
__STM32_PIN(143, I, 15),
|
||||
#if defined(GPIOJ)
|
||||
__STM32_PIN(144, J, 0),
|
||||
__STM32_PIN(145, J, 1),
|
||||
__STM32_PIN(146, J, 2),
|
||||
__STM32_PIN(147, J, 3),
|
||||
__STM32_PIN(148, J, 4),
|
||||
__STM32_PIN(149, J, 5),
|
||||
__STM32_PIN(150, J, 6),
|
||||
__STM32_PIN(151, J, 7),
|
||||
__STM32_PIN(152, J, 8),
|
||||
__STM32_PIN(153, J, 9),
|
||||
__STM32_PIN(154, J, 10),
|
||||
__STM32_PIN(155, J, 11),
|
||||
__STM32_PIN(156, J, 12),
|
||||
__STM32_PIN(157, J, 13),
|
||||
__STM32_PIN(158, J, 14),
|
||||
__STM32_PIN(159, J, 15),
|
||||
#if defined(GPIOK)
|
||||
__STM32_PIN(160, K, 0),
|
||||
__STM32_PIN(161, K, 1),
|
||||
__STM32_PIN(162, K, 2),
|
||||
__STM32_PIN(163, K, 3),
|
||||
__STM32_PIN(164, K, 4),
|
||||
__STM32_PIN(165, K, 5),
|
||||
__STM32_PIN(166, K, 6),
|
||||
__STM32_PIN(167, K, 7),
|
||||
__STM32_PIN(168, K, 8),
|
||||
__STM32_PIN(169, K, 9),
|
||||
__STM32_PIN(170, K, 10),
|
||||
__STM32_PIN(171, K, 11),
|
||||
__STM32_PIN(172, K, 12),
|
||||
__STM32_PIN(173, K, 13),
|
||||
__STM32_PIN(174, K, 14),
|
||||
__STM32_PIN(175, K, 15),
|
||||
#endif /* defined(GPIOK) */
|
||||
#endif /* defined(GPIOJ) */
|
||||
#endif /* defined(GPIOI) */
|
||||
#endif /* defined(GPIOH) */
|
||||
#endif /* defined(GPIOG) */
|
||||
#endif /* defined(GPIOF) */
|
||||
#endif /* defined(GPIOE) */
|
||||
#endif /* defined(GPIOD) */
|
||||
#endif /* defined(GPIOC) */
|
||||
#endif /* defined(GPIOB) */
|
||||
#endif /* defined(GPIOA) */
|
||||
};
|
||||
|
||||
static const struct pin_irq_map pin_irq_map[] =
|
||||
{
|
||||
#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0)
|
||||
{GPIO_PIN_0, EXTI0_1_IRQn},
|
||||
{GPIO_PIN_1, EXTI0_1_IRQn},
|
||||
{GPIO_PIN_2, EXTI2_3_IRQn},
|
||||
{GPIO_PIN_3, EXTI2_3_IRQn},
|
||||
{GPIO_PIN_4, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_5, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_6, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_7, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_8, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_9, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_10, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_11, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_12, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_13, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_14, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_15, EXTI4_15_IRQn},
|
||||
#else
|
||||
{GPIO_PIN_0, EXTI0_IRQn},
|
||||
{GPIO_PIN_1, EXTI1_IRQn},
|
||||
{GPIO_PIN_2, EXTI2_IRQn},
|
||||
{GPIO_PIN_3, EXTI3_IRQn},
|
||||
{GPIO_PIN_4, EXTI4_IRQn},
|
||||
{GPIO_PIN_5, EXTI9_5_IRQn},
|
||||
{GPIO_PIN_6, EXTI9_5_IRQn},
|
||||
{GPIO_PIN_7, EXTI9_5_IRQn},
|
||||
{GPIO_PIN_8, EXTI9_5_IRQn},
|
||||
{GPIO_PIN_9, EXTI9_5_IRQn},
|
||||
{GPIO_PIN_10, EXTI15_10_IRQn},
|
||||
{GPIO_PIN_11, EXTI15_10_IRQn},
|
||||
{GPIO_PIN_12, EXTI15_10_IRQn},
|
||||
{GPIO_PIN_13, EXTI15_10_IRQn},
|
||||
{GPIO_PIN_14, EXTI15_10_IRQn},
|
||||
{GPIO_PIN_15, EXTI15_10_IRQn},
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
|
||||
{
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
{-1, 0, RT_NULL, RT_NULL},
|
||||
};
|
||||
static uint32_t pin_irq_enable_mask=0;
|
||||
|
||||
#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
|
||||
static const struct pin_index *get_pin(uint8_t pin)
|
||||
{
|
||||
const struct pin_index *index;
|
||||
|
||||
if (pin < ITEM_NUM(pins))
|
||||
{
|
||||
index = &pins[pin];
|
||||
if (index->index == -1)
|
||||
index = RT_NULL;
|
||||
}
|
||||
else
|
||||
{
|
||||
index = RT_NULL;
|
||||
}
|
||||
|
||||
return index;
|
||||
};
|
||||
|
||||
static void stm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
|
||||
{
|
||||
const struct pin_index *index;
|
||||
|
||||
index = get_pin(pin);
|
||||
if (index == RT_NULL)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
HAL_GPIO_WritePin(index->gpio, index->pin, (GPIO_PinState)value);
|
||||
}
|
||||
|
||||
static int stm32_pin_read(rt_device_t dev, rt_base_t pin)
|
||||
{
|
||||
int value;
|
||||
const struct pin_index *index;
|
||||
|
||||
value = PIN_LOW;
|
||||
|
||||
index = get_pin(pin);
|
||||
if (index == RT_NULL)
|
||||
{
|
||||
return value;
|
||||
}
|
||||
|
||||
value = HAL_GPIO_ReadPin(index->gpio, index->pin);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
static void stm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
|
||||
{
|
||||
const struct pin_index *index;
|
||||
GPIO_InitTypeDef GPIO_InitStruct;
|
||||
|
||||
index = get_pin(pin);
|
||||
if (index == RT_NULL)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/* Configure GPIO_InitStructure */
|
||||
GPIO_InitStruct.Pin = index->pin;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||||
|
||||
if (mode == PIN_MODE_OUTPUT)
|
||||
{
|
||||
/* output setting */
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
}
|
||||
else if (mode == PIN_MODE_INPUT)
|
||||
{
|
||||
/* input setting: not pull. */
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
}
|
||||
else if (mode == PIN_MODE_INPUT_PULLUP)
|
||||
{
|
||||
/* input setting: pull up. */
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
||||
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
||||
}
|
||||
else if (mode == PIN_MODE_INPUT_PULLDOWN)
|
||||
{
|
||||
/* input setting: pull down. */
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
|
||||
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
|
||||
}
|
||||
else if (mode == PIN_MODE_OUTPUT_OD)
|
||||
{
|
||||
/* output setting: od. */
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
}
|
||||
|
||||
HAL_GPIO_Init(index->gpio, &GPIO_InitStruct);
|
||||
}
|
||||
|
||||
rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 32; i++)
|
||||
{
|
||||
if ((0x01 << i) == bit)
|
||||
{
|
||||
return i;
|
||||
}
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
|
||||
{
|
||||
rt_int32_t mapindex = bit2bitno(pinbit);
|
||||
if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
|
||||
{
|
||||
return RT_NULL;
|
||||
}
|
||||
return &pin_irq_map[mapindex];
|
||||
};
|
||||
|
||||
static rt_err_t stm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
|
||||
rt_uint32_t mode, void (*hdr)(void *args), void *args)
|
||||
{
|
||||
const struct pin_index *index;
|
||||
rt_base_t level;
|
||||
rt_int32_t irqindex = -1;
|
||||
|
||||
index = get_pin(pin);
|
||||
if (index == RT_NULL)
|
||||
{
|
||||
return RT_ENOSYS;
|
||||
}
|
||||
irqindex = bit2bitno(index->pin);
|
||||
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
|
||||
{
|
||||
return RT_ENOSYS;
|
||||
}
|
||||
|
||||
level = rt_hw_interrupt_disable();
|
||||
if (pin_irq_hdr_tab[irqindex].pin == pin &&
|
||||
pin_irq_hdr_tab[irqindex].hdr == hdr &&
|
||||
pin_irq_hdr_tab[irqindex].mode == mode &&
|
||||
pin_irq_hdr_tab[irqindex].args == args)
|
||||
{
|
||||
rt_hw_interrupt_enable(level);
|
||||
return RT_EOK;
|
||||
}
|
||||
if (pin_irq_hdr_tab[irqindex].pin != -1)
|
||||
{
|
||||
rt_hw_interrupt_enable(level);
|
||||
return RT_EBUSY;
|
||||
}
|
||||
pin_irq_hdr_tab[irqindex].pin = pin;
|
||||
pin_irq_hdr_tab[irqindex].hdr = hdr;
|
||||
pin_irq_hdr_tab[irqindex].mode = mode;
|
||||
pin_irq_hdr_tab[irqindex].args = args;
|
||||
rt_hw_interrupt_enable(level);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t stm32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
|
||||
{
|
||||
const struct pin_index *index;
|
||||
rt_base_t level;
|
||||
rt_int32_t irqindex = -1;
|
||||
|
||||
index = get_pin(pin);
|
||||
if (index == RT_NULL)
|
||||
{
|
||||
return RT_ENOSYS;
|
||||
}
|
||||
irqindex = bit2bitno(index->pin);
|
||||
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
|
||||
{
|
||||
return RT_ENOSYS;
|
||||
}
|
||||
|
||||
level = rt_hw_interrupt_disable();
|
||||
if (pin_irq_hdr_tab[irqindex].pin == -1)
|
||||
{
|
||||
rt_hw_interrupt_enable(level);
|
||||
return RT_EOK;
|
||||
}
|
||||
pin_irq_hdr_tab[irqindex].pin = -1;
|
||||
pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
|
||||
pin_irq_hdr_tab[irqindex].mode = 0;
|
||||
pin_irq_hdr_tab[irqindex].args = RT_NULL;
|
||||
rt_hw_interrupt_enable(level);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
|
||||
rt_uint32_t enabled)
|
||||
{
|
||||
const struct pin_index *index;
|
||||
const struct pin_irq_map *irqmap;
|
||||
rt_base_t level;
|
||||
rt_int32_t irqindex = -1;
|
||||
GPIO_InitTypeDef GPIO_InitStruct;
|
||||
|
||||
index = get_pin(pin);
|
||||
if (index == RT_NULL)
|
||||
{
|
||||
return RT_ENOSYS;
|
||||
}
|
||||
|
||||
if (enabled == PIN_IRQ_ENABLE)
|
||||
{
|
||||
irqindex = bit2bitno(index->pin);
|
||||
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
|
||||
{
|
||||
return RT_ENOSYS;
|
||||
}
|
||||
|
||||
level = rt_hw_interrupt_disable();
|
||||
|
||||
if (pin_irq_hdr_tab[irqindex].pin == -1)
|
||||
{
|
||||
rt_hw_interrupt_enable(level);
|
||||
return RT_ENOSYS;
|
||||
}
|
||||
|
||||
irqmap = &pin_irq_map[irqindex];
|
||||
|
||||
/* Configure GPIO_InitStructure */
|
||||
GPIO_InitStruct.Pin = index->pin;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
|
||||
switch (pin_irq_hdr_tab[irqindex].mode)
|
||||
{
|
||||
case PIN_IRQ_MODE_RISING:
|
||||
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
|
||||
break;
|
||||
case PIN_IRQ_MODE_FALLING:
|
||||
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
|
||||
break;
|
||||
case PIN_IRQ_MODE_RISING_FALLING:
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING;
|
||||
break;
|
||||
}
|
||||
HAL_GPIO_Init(index->gpio, &GPIO_InitStruct);
|
||||
|
||||
HAL_NVIC_SetPriority(irqmap->irqno, 5, 0);
|
||||
HAL_NVIC_EnableIRQ(irqmap->irqno);
|
||||
pin_irq_enable_mask |= irqmap->pinbit;
|
||||
|
||||
rt_hw_interrupt_enable(level);
|
||||
}
|
||||
else if (enabled == PIN_IRQ_DISABLE)
|
||||
{
|
||||
irqmap = get_pin_irq_map(index->pin);
|
||||
if (irqmap == RT_NULL)
|
||||
{
|
||||
return RT_ENOSYS;
|
||||
}
|
||||
|
||||
level = rt_hw_interrupt_disable();
|
||||
|
||||
HAL_GPIO_DeInit(index->gpio, index->pin);
|
||||
|
||||
pin_irq_enable_mask &= ~irqmap->pinbit;
|
||||
#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
|
||||
if (( irqmap->pinbit>=GPIO_PIN_0 )&&( irqmap->pinbit<=GPIO_PIN_1 ))
|
||||
{
|
||||
if(!(pin_irq_enable_mask&(GPIO_PIN_0|GPIO_PIN_1)))
|
||||
{
|
||||
HAL_NVIC_DisableIRQ(irqmap->irqno);
|
||||
}
|
||||
}
|
||||
else if (( irqmap->pinbit>=GPIO_PIN_2 )&&( irqmap->pinbit<=GPIO_PIN_3 ))
|
||||
{
|
||||
if(!(pin_irq_enable_mask&(GPIO_PIN_2|GPIO_PIN_3)))
|
||||
{
|
||||
HAL_NVIC_DisableIRQ(irqmap->irqno);
|
||||
}
|
||||
}
|
||||
else if (( irqmap->pinbit>=GPIO_PIN_4 )&&( irqmap->pinbit<=GPIO_PIN_15 ))
|
||||
{
|
||||
if(!(pin_irq_enable_mask&(GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|
|
||||
GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15)))
|
||||
{
|
||||
HAL_NVIC_DisableIRQ(irqmap->irqno);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
HAL_NVIC_DisableIRQ(irqmap->irqno);
|
||||
}
|
||||
#else
|
||||
if (( irqmap->pinbit>=GPIO_PIN_5 )&&( irqmap->pinbit<=GPIO_PIN_9 ))
|
||||
{
|
||||
if(!(pin_irq_enable_mask&(GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9)))
|
||||
{
|
||||
HAL_NVIC_DisableIRQ(irqmap->irqno);
|
||||
}
|
||||
}
|
||||
else if (( irqmap->pinbit>=GPIO_PIN_10 )&&( irqmap->pinbit<=GPIO_PIN_15 ))
|
||||
{
|
||||
if(!(pin_irq_enable_mask&(GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15)))
|
||||
{
|
||||
HAL_NVIC_DisableIRQ(irqmap->irqno);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
HAL_NVIC_DisableIRQ(irqmap->irqno);
|
||||
}
|
||||
#endif
|
||||
rt_hw_interrupt_enable(level);
|
||||
}
|
||||
else
|
||||
{
|
||||
return -RT_ENOSYS;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
const static struct rt_pin_ops _stm32_pin_ops =
|
||||
{
|
||||
stm32_pin_mode,
|
||||
stm32_pin_write,
|
||||
stm32_pin_read,
|
||||
stm32_pin_attach_irq,
|
||||
stm32_pin_dettach_irq,
|
||||
stm32_pin_irq_enable,
|
||||
};
|
||||
|
||||
rt_inline void pin_irq_hdr(int irqno)
|
||||
{
|
||||
if (pin_irq_hdr_tab[irqno].hdr)
|
||||
{
|
||||
pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(SOC_SERIES_STM32G0)
|
||||
void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin)
|
||||
{
|
||||
pin_irq_hdr(bit2bitno(GPIO_Pin));
|
||||
}
|
||||
|
||||
void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin)
|
||||
{
|
||||
pin_irq_hdr(bit2bitno(GPIO_Pin));
|
||||
}
|
||||
#else
|
||||
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
|
||||
{
|
||||
pin_irq_hdr(bit2bitno(GPIO_Pin));
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32L0)
|
||||
void EXTI0_1_IRQHandler(void)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void EXTI2_3_IRQHandler(void)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_2);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
void EXTI4_15_IRQHandler(void)
|
||||
{
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_4);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_5);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_6);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_7);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
void EXTI0_IRQHandler(void)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void EXTI1_IRQHandler(void)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void EXTI2_IRQHandler(void)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_2);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void EXTI3_IRQHandler(void)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void EXTI4_IRQHandler(void)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_4);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void EXTI9_5_IRQHandler(void)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_5);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_6);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_7);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void EXTI15_10_IRQHandler(void)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14);
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
|
||||
int rt_hw_pin_init(void)
|
||||
{
|
||||
#if defined(__HAL_RCC_GPIOA_CLK_ENABLE)
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
#endif
|
||||
|
||||
#if defined(__HAL_RCC_GPIOB_CLK_ENABLE)
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
#endif
|
||||
|
||||
#if defined(__HAL_RCC_GPIOC_CLK_ENABLE)
|
||||
__HAL_RCC_GPIOC_CLK_ENABLE();
|
||||
#endif
|
||||
|
||||
#if defined(__HAL_RCC_GPIOD_CLK_ENABLE)
|
||||
__HAL_RCC_GPIOD_CLK_ENABLE();
|
||||
#endif
|
||||
|
||||
#if defined(__HAL_RCC_GPIOE_CLK_ENABLE)
|
||||
__HAL_RCC_GPIOE_CLK_ENABLE();
|
||||
#endif
|
||||
|
||||
#if defined(__HAL_RCC_GPIOF_CLK_ENABLE)
|
||||
__HAL_RCC_GPIOF_CLK_ENABLE();
|
||||
#endif
|
||||
|
||||
#if defined(__HAL_RCC_GPIOG_CLK_ENABLE)
|
||||
#ifdef SOC_SERIES_STM32L4
|
||||
HAL_PWREx_EnableVddIO2();
|
||||
#endif
|
||||
__HAL_RCC_GPIOG_CLK_ENABLE();
|
||||
#endif
|
||||
|
||||
#if defined(__HAL_RCC_GPIOH_CLK_ENABLE)
|
||||
__HAL_RCC_GPIOH_CLK_ENABLE();
|
||||
#endif
|
||||
|
||||
#if defined(__HAL_RCC_GPIOI_CLK_ENABLE)
|
||||
__HAL_RCC_GPIOI_CLK_ENABLE();
|
||||
#endif
|
||||
|
||||
#if defined(__HAL_RCC_GPIOJ_CLK_ENABLE)
|
||||
__HAL_RCC_GPIOJ_CLK_ENABLE();
|
||||
#endif
|
||||
|
||||
#if defined(__HAL_RCC_GPIOK_CLK_ENABLE)
|
||||
__HAL_RCC_GPIOK_CLK_ENABLE();
|
||||
#endif
|
||||
|
||||
return rt_device_pin_register("pin", &_stm32_pin_ops, RT_NULL);
|
||||
}
|
||||
|
||||
#endif /* RT_USING_PIN */
|
||||
555
drivers/drv_hwtimer.c
Normal file
555
drivers/drv_hwtimer.c
Normal file
@ -0,0 +1,555 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-10 zylx first version
|
||||
*/
|
||||
|
||||
#include <board.h>
|
||||
#include<rtthread.h>
|
||||
#include<rtdevice.h>
|
||||
|
||||
#ifdef BSP_USING_TIM
|
||||
#include "drv_config.h"
|
||||
|
||||
//#define DRV_DEBUG
|
||||
#define LOG_TAG "drv.hwtimer"
|
||||
#include <drv_log.h>
|
||||
|
||||
#ifdef RT_USING_HWTIMER
|
||||
enum
|
||||
{
|
||||
#ifdef BSP_USING_TIM1
|
||||
TIM1_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM2
|
||||
TIM2_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM3
|
||||
TIM3_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM4
|
||||
TIM4_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM5
|
||||
TIM5_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM6
|
||||
TIM6_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM7
|
||||
TIM7_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM8
|
||||
TIM8_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM9
|
||||
TIM9_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM10
|
||||
TIM10_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM11
|
||||
TIM11_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM12
|
||||
TIM12_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM13
|
||||
TIM13_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM14
|
||||
TIM14_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM15
|
||||
TIM15_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM16
|
||||
TIM16_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM17
|
||||
TIM17_INDEX,
|
||||
#endif
|
||||
};
|
||||
|
||||
struct stm32_hwtimer
|
||||
{
|
||||
rt_hwtimer_t time_device;
|
||||
TIM_HandleTypeDef tim_handle;
|
||||
IRQn_Type tim_irqn;
|
||||
char *name;
|
||||
};
|
||||
|
||||
static struct stm32_hwtimer stm32_hwtimer_obj[] =
|
||||
{
|
||||
#ifdef BSP_USING_TIM1
|
||||
TIM1_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_TIM2
|
||||
TIM2_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_TIM3
|
||||
TIM3_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_TIM4
|
||||
TIM4_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_TIM5
|
||||
TIM5_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_TIM6
|
||||
TIM6_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_TIM7
|
||||
TIM7_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_TIM8
|
||||
TIM8_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_TIM9
|
||||
TIM9_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_TIM10
|
||||
TIM10_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_TIM11
|
||||
TIM11_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_TIM12
|
||||
TIM12_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_TIM13
|
||||
TIM13_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_TIM14
|
||||
TIM14_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_TIM15
|
||||
TIM15_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_TIM16
|
||||
TIM16_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_TIM17
|
||||
TIM17_CONFIG,
|
||||
#endif
|
||||
};
|
||||
|
||||
static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
|
||||
{
|
||||
uint32_t prescaler_value = 0;
|
||||
TIM_HandleTypeDef *tim = RT_NULL;
|
||||
struct stm32_hwtimer *tim_device = RT_NULL;
|
||||
|
||||
RT_ASSERT(timer != RT_NULL);
|
||||
if (state)
|
||||
{
|
||||
tim = (TIM_HandleTypeDef *)timer->parent.user_data;
|
||||
tim_device = (struct stm32_hwtimer *)timer;
|
||||
|
||||
/* time init */
|
||||
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||||
if (tim->Instance == TIM9 || tim->Instance == TIM10 || tim->Instance == TIM11)
|
||||
#elif defined(SOC_SERIES_STM32L4)
|
||||
if (tim->Instance == TIM15 || tim->Instance == TIM16 || tim->Instance == TIM17)
|
||||
#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
|
||||
if (0)
|
||||
#endif
|
||||
{
|
||||
#if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
|
||||
prescaler_value = (uint32_t)(HAL_RCC_GetPCLK2Freq() * 2 / 10000) - 1;
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
prescaler_value = (uint32_t)(HAL_RCC_GetPCLK1Freq() * 2 / 10000) - 1;
|
||||
}
|
||||
tim->Init.Period = 10000 - 1;
|
||||
tim->Init.Prescaler = prescaler_value;
|
||||
tim->Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
||||
if (timer->info->cntmode == HWTIMER_CNTMODE_UP)
|
||||
{
|
||||
tim->Init.CounterMode = TIM_COUNTERMODE_UP;
|
||||
}
|
||||
else
|
||||
{
|
||||
tim->Init.CounterMode = TIM_COUNTERMODE_DOWN;
|
||||
}
|
||||
tim->Init.RepetitionCounter = 0;
|
||||
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
|
||||
tim->Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
||||
#endif
|
||||
if (HAL_TIM_Base_Init(tim) != HAL_OK)
|
||||
{
|
||||
LOG_E("%s init failed", tim_device->name);
|
||||
return;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* set the TIMx priority */
|
||||
HAL_NVIC_SetPriority(tim_device->tim_irqn, 3, 0);
|
||||
|
||||
/* enable the TIMx global Interrupt */
|
||||
HAL_NVIC_EnableIRQ(tim_device->tim_irqn);
|
||||
|
||||
/* clear update flag */
|
||||
__HAL_TIM_CLEAR_FLAG(tim, TIM_FLAG_UPDATE);
|
||||
/* enable update request source */
|
||||
__HAL_TIM_URS_ENABLE(tim);
|
||||
|
||||
LOG_D("%s init success", tim_device->name);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
TIM_HandleTypeDef *tim = RT_NULL;
|
||||
|
||||
RT_ASSERT(timer != RT_NULL);
|
||||
|
||||
tim = (TIM_HandleTypeDef *)timer->parent.user_data;
|
||||
|
||||
/* set tim cnt */
|
||||
__HAL_TIM_SET_COUNTER(tim, 0);
|
||||
/* set tim arr */
|
||||
__HAL_TIM_SET_AUTORELOAD(tim, t - 1);
|
||||
|
||||
if (opmode == HWTIMER_MODE_ONESHOT)
|
||||
{
|
||||
/* set timer to single mode */
|
||||
tim->Instance->CR1 |= TIM_OPMODE_SINGLE;
|
||||
}
|
||||
else
|
||||
{
|
||||
tim->Instance->CR1 &= (~TIM_OPMODE_SINGLE);
|
||||
}
|
||||
|
||||
/* start timer */
|
||||
if (HAL_TIM_Base_Start_IT(tim) != HAL_OK)
|
||||
{
|
||||
LOG_E("TIM start failed");
|
||||
result = -RT_ERROR;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static void timer_stop(rt_hwtimer_t *timer)
|
||||
{
|
||||
TIM_HandleTypeDef *tim = RT_NULL;
|
||||
|
||||
RT_ASSERT(timer != RT_NULL);
|
||||
|
||||
tim = (TIM_HandleTypeDef *)timer->parent.user_data;
|
||||
|
||||
/* stop timer */
|
||||
HAL_TIM_Base_Stop_IT(tim);
|
||||
|
||||
/* set tim cnt */
|
||||
__HAL_TIM_SET_COUNTER(tim, 0);
|
||||
}
|
||||
|
||||
static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
|
||||
{
|
||||
TIM_HandleTypeDef *tim = RT_NULL;
|
||||
rt_err_t result = RT_EOK;
|
||||
|
||||
RT_ASSERT(timer != RT_NULL);
|
||||
RT_ASSERT(arg != RT_NULL);
|
||||
|
||||
tim = (TIM_HandleTypeDef *)timer->parent.user_data;
|
||||
|
||||
switch (cmd)
|
||||
{
|
||||
case HWTIMER_CTRL_FREQ_SET:
|
||||
{
|
||||
rt_uint32_t freq;
|
||||
rt_uint16_t val;
|
||||
|
||||
/* set timer frequence */
|
||||
freq = *((rt_uint32_t *)arg);
|
||||
|
||||
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||||
if (tim->Instance == TIM9 || tim->Instance == TIM10 || tim->Instance == TIM11)
|
||||
#elif defined(SOC_SERIES_STM32L4)
|
||||
if (tim->Instance == TIM15 || tim->Instance == TIM16 || tim->Instance == TIM17)
|
||||
#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
|
||||
if (0)
|
||||
#endif
|
||||
{
|
||||
#if defined(SOC_SERIES_STM32L4)
|
||||
val = HAL_RCC_GetPCLK2Freq() / freq;
|
||||
#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||||
val = HAL_RCC_GetPCLK2Freq() * 2 / freq;
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||||
val = HAL_RCC_GetPCLK1Freq() * 2 / freq;
|
||||
#elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
|
||||
val = HAL_RCC_GetPCLK1Freq() / freq;
|
||||
#endif
|
||||
}
|
||||
__HAL_TIM_SET_PRESCALER(tim, val - 1);
|
||||
|
||||
/* Update frequency value */
|
||||
tim->Instance->EGR |= TIM_EVENTSOURCE_UPDATE;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
{
|
||||
result = -RT_ENOSYS;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer)
|
||||
{
|
||||
TIM_HandleTypeDef *tim = RT_NULL;
|
||||
|
||||
RT_ASSERT(timer != RT_NULL);
|
||||
|
||||
tim = (TIM_HandleTypeDef *)timer->parent.user_data;
|
||||
|
||||
return tim->Instance->CNT;
|
||||
}
|
||||
|
||||
static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG;
|
||||
|
||||
static const struct rt_hwtimer_ops _ops =
|
||||
{
|
||||
.init = timer_init,
|
||||
.start = timer_start,
|
||||
.stop = timer_stop,
|
||||
.count_get = timer_counter_get,
|
||||
.control = timer_ctrl,
|
||||
};
|
||||
|
||||
#ifdef BSP_USING_TIM2
|
||||
void TIM2_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM2_INDEX].tim_handle);
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM3
|
||||
void TIM3_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM3_INDEX].tim_handle);
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM4
|
||||
void TIM4_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM4_INDEX].tim_handle);
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM5
|
||||
void TIM5_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM5_INDEX].tim_handle);
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM11
|
||||
void TIM1_TRG_COM_TIM11_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM11_INDEX].tim_handle);
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM13
|
||||
void TIM8_UP_TIM13_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM13_INDEX].tim_handle);
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM14
|
||||
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||||
void TIM8_TRG_COM_TIM14_IRQHandler(void)
|
||||
#elif defined(SOC_SERIES_STM32F0)
|
||||
void TIM14_IRQHandler(void)
|
||||
#endif
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM14_INDEX].tim_handle);
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM15
|
||||
void TIM1_BRK_TIM15_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM15_INDEX].tim_handle);
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM16
|
||||
#if defined(SOC_SERIES_STM32L4)
|
||||
void TIM1_UP_TIM16_IRQHandler(void)
|
||||
#elif defined(SOC_SERIES_STM32F0)
|
||||
void TIM16_IRQHandler(void)
|
||||
#endif
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM16_INDEX].tim_handle);
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM17
|
||||
#if defined(SOC_SERIES_STM32L4)
|
||||
void TIM1_TRG_COM_TIM17_IRQHandler(void)
|
||||
#elif defined(SOC_SERIES_STM32F0)
|
||||
void TIM17_IRQHandler(void)
|
||||
#endif
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM17_INDEX].tim_handle);
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
|
||||
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
|
||||
{
|
||||
#ifdef BSP_USING_TIM2
|
||||
if (htim->Instance == TIM2)
|
||||
{
|
||||
rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM2_INDEX].time_device);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM3
|
||||
if (htim->Instance == TIM3)
|
||||
{
|
||||
rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM3_INDEX].time_device);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM4
|
||||
if (htim->Instance == TIM4)
|
||||
{
|
||||
rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM4_INDEX].time_device);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM5
|
||||
if (htim->Instance == TIM5)
|
||||
{
|
||||
rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM5_INDEX].time_device);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM11
|
||||
if (htim->Instance == TIM11)
|
||||
{
|
||||
rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM11_INDEX].time_device);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM13
|
||||
if (htim->Instance == TIM13)
|
||||
{
|
||||
rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM13_INDEX].time_device);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM14
|
||||
if (htim->Instance == TIM14)
|
||||
{
|
||||
rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM14_INDEX].time_device);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM15
|
||||
if (htim->Instance == TIM15)
|
||||
{
|
||||
rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM15_INDEX].time_device);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM16
|
||||
if (htim->Instance == TIM16)
|
||||
{
|
||||
rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM16_INDEX].time_device);
|
||||
}
|
||||
#endif
|
||||
#ifdef BSP_USING_TIM17
|
||||
if (htim->Instance == TIM17)
|
||||
{
|
||||
rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM17_INDEX].time_device);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
static int stm32_hwtimer_init(void)
|
||||
{
|
||||
int i = 0;
|
||||
int result = RT_EOK;
|
||||
|
||||
for (i = 0; i < sizeof(stm32_hwtimer_obj) / sizeof(stm32_hwtimer_obj[0]); i++)
|
||||
{
|
||||
stm32_hwtimer_obj[i].time_device.info = &_info;
|
||||
stm32_hwtimer_obj[i].time_device.ops = &_ops;
|
||||
if (rt_device_hwtimer_register(&stm32_hwtimer_obj[i].time_device, stm32_hwtimer_obj[i].name, &stm32_hwtimer_obj[i].tim_handle) == RT_EOK)
|
||||
{
|
||||
LOG_D("%s register success", stm32_hwtimer_obj[i].name);
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_E("%s register failed", stm32_hwtimer_obj[i].name);
|
||||
result = -RT_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
INIT_BOARD_EXPORT(stm32_hwtimer_init);
|
||||
|
||||
#endif /* RT_USING_HWTIMER */
|
||||
#endif /* BSP_USING_TIM */
|
||||
566
drivers/drv_pwm.c
Normal file
566
drivers/drv_pwm.c
Normal file
@ -0,0 +1,566 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-13 zylx first version
|
||||
*/
|
||||
|
||||
#include <board.h>
|
||||
#include<rtthread.h>
|
||||
#include<rtdevice.h>
|
||||
|
||||
#ifdef RT_USING_PWM
|
||||
#include "drv_config.h"
|
||||
|
||||
//#define DRV_DEBUG
|
||||
#define LOG_TAG "drv.pwm"
|
||||
#include <drv_log.h>
|
||||
|
||||
#define MAX_PERIOD 65535
|
||||
#define MIN_PERIOD 3
|
||||
#define MIN_PULSE 2
|
||||
|
||||
extern void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
|
||||
|
||||
enum
|
||||
{
|
||||
#ifdef BSP_USING_PWM1
|
||||
PWM1_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM2
|
||||
PWM2_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM3
|
||||
PWM3_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM4
|
||||
PWM4_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM5
|
||||
PWM5_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM6
|
||||
PWM6_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM7
|
||||
PWM7_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM8
|
||||
PWM8_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM9
|
||||
PWM9_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM10
|
||||
PWM10_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM11
|
||||
PWM11_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM12
|
||||
PWM12_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM13
|
||||
PWM13_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM14
|
||||
PWM14_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM15
|
||||
PWM15_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM16
|
||||
PWM16_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM17
|
||||
PWM17_INDEX,
|
||||
#endif
|
||||
};
|
||||
|
||||
struct stm32_pwm
|
||||
{
|
||||
struct rt_device_pwm pwm_device;
|
||||
TIM_HandleTypeDef tim_handle;
|
||||
rt_uint8_t channel;
|
||||
char *name;
|
||||
};
|
||||
|
||||
static struct stm32_pwm stm32_pwm_obj[] =
|
||||
{
|
||||
#ifdef BSP_USING_PWM1
|
||||
PWM1_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PWM2
|
||||
PWM2_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PWM3
|
||||
PWM3_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PWM4
|
||||
PWM4_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PWM5
|
||||
PWM5_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PWM6
|
||||
PWM6_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PWM7
|
||||
PWM7_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PWM8
|
||||
PWM8_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PWM9
|
||||
PWM9_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PWM10
|
||||
PWM10_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PWM11
|
||||
PWM11_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PWM12
|
||||
PWM12_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PWM13
|
||||
PWM13_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PWM14
|
||||
PWM14_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PWM15
|
||||
PWM15_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PWM16
|
||||
PWM16_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PWM17
|
||||
PWM17_CONFIG,
|
||||
#endif
|
||||
};
|
||||
|
||||
static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg);
|
||||
static struct rt_pwm_ops drv_ops =
|
||||
{
|
||||
drv_pwm_control
|
||||
};
|
||||
|
||||
static rt_err_t drv_pwm_enable(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration, rt_bool_t enable)
|
||||
{
|
||||
/* Converts the channel number to the channel number of Hal library */
|
||||
rt_uint32_t channel = 0x04 * (configuration->channel - 1);
|
||||
|
||||
if (!enable)
|
||||
{
|
||||
HAL_TIM_PWM_Stop(htim, channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
HAL_TIM_PWM_Start(htim, channel);
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t drv_pwm_get(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration)
|
||||
{
|
||||
/* Converts the channel number to the channel number of Hal library */
|
||||
rt_uint32_t channel = 0x04 * (configuration->channel - 1);
|
||||
rt_uint64_t tim_clock;
|
||||
|
||||
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||||
if (htim->Instance == TIM9 || htim->Instance == TIM10 || htim->Instance == TIM11)
|
||||
#elif defined(SOC_SERIES_STM32L4)
|
||||
if (htim->Instance == TIM15 || htim->Instance == TIM16 || htim->Instance == TIM17)
|
||||
#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
|
||||
if (0)
|
||||
#endif
|
||||
{
|
||||
#if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
|
||||
tim_clock = HAL_RCC_GetPCLK2Freq() * 2;
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
|
||||
tim_clock = HAL_RCC_GetPCLK1Freq();
|
||||
#else
|
||||
tim_clock = HAL_RCC_GetPCLK1Freq() * 2;
|
||||
#endif
|
||||
}
|
||||
|
||||
if (__HAL_TIM_GET_CLOCKDIVISION(htim) == TIM_CLOCKDIVISION_DIV2)
|
||||
{
|
||||
tim_clock = tim_clock / 2;
|
||||
}
|
||||
else if (__HAL_TIM_GET_CLOCKDIVISION(htim) == TIM_CLOCKDIVISION_DIV4)
|
||||
{
|
||||
tim_clock = tim_clock / 4;
|
||||
}
|
||||
|
||||
/* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
|
||||
tim_clock /= 1000000UL;
|
||||
configuration->period = (__HAL_TIM_GET_AUTORELOAD(htim) + 1) * (htim->Instance->PSC + 1) * 1000UL / tim_clock;
|
||||
configuration->pulse = (__HAL_TIM_GET_COMPARE(htim, channel) + 1) * (htim->Instance->PSC + 1) * 1000UL / tim_clock;
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t drv_pwm_set(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration)
|
||||
{
|
||||
rt_uint32_t period, pulse;
|
||||
rt_uint64_t tim_clock, psc;
|
||||
/* Converts the channel number to the channel number of Hal library */
|
||||
rt_uint32_t channel = 0x04 * (configuration->channel - 1);
|
||||
|
||||
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||||
if (htim->Instance == TIM9 || htim->Instance == TIM10 || htim->Instance == TIM11)
|
||||
#elif defined(SOC_SERIES_STM32L4)
|
||||
if (htim->Instance == TIM15 || htim->Instance == TIM16 || htim->Instance == TIM17)
|
||||
#elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
|
||||
if (0)
|
||||
#endif
|
||||
{
|
||||
#if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
|
||||
tim_clock = HAL_RCC_GetPCLK2Freq() * 2;
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
|
||||
tim_clock = HAL_RCC_GetPCLK1Freq();
|
||||
#else
|
||||
tim_clock = HAL_RCC_GetPCLK1Freq() * 2;
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
|
||||
tim_clock /= 1000000UL;
|
||||
period = (unsigned long long)configuration->period * tim_clock / 1000ULL ;
|
||||
psc = period / MAX_PERIOD + 1;
|
||||
period = period / psc;
|
||||
__HAL_TIM_SET_PRESCALER(htim, psc - 1);
|
||||
|
||||
if (period < MIN_PERIOD)
|
||||
{
|
||||
period = MIN_PERIOD;
|
||||
}
|
||||
__HAL_TIM_SET_AUTORELOAD(htim, period - 1);
|
||||
|
||||
pulse = (unsigned long long)configuration->pulse * tim_clock / psc / 1000ULL;
|
||||
if (pulse < MIN_PULSE)
|
||||
{
|
||||
pulse = MIN_PULSE;
|
||||
}
|
||||
else if (pulse > period)
|
||||
{
|
||||
pulse = period;
|
||||
}
|
||||
__HAL_TIM_SET_COMPARE(htim, channel, pulse - 1);
|
||||
__HAL_TIM_SET_COUNTER(htim, 0);
|
||||
|
||||
/* Update frequency value */
|
||||
HAL_TIM_GenerateEvent(htim, TIM_EVENTSOURCE_UPDATE);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
|
||||
{
|
||||
struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
|
||||
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)device->parent.user_data;
|
||||
|
||||
switch (cmd)
|
||||
{
|
||||
case PWM_CMD_ENABLE:
|
||||
return drv_pwm_enable(htim, configuration, RT_TRUE);
|
||||
case PWM_CMD_DISABLE:
|
||||
return drv_pwm_enable(htim, configuration, RT_FALSE);
|
||||
case PWM_CMD_SET:
|
||||
return drv_pwm_set(htim, configuration);
|
||||
case PWM_CMD_GET:
|
||||
return drv_pwm_get(htim, configuration);
|
||||
default:
|
||||
return RT_EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
static rt_err_t stm32_hw_pwm_init(struct stm32_pwm *device)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
TIM_HandleTypeDef *tim = RT_NULL;
|
||||
TIM_OC_InitTypeDef oc_config = {0};
|
||||
TIM_MasterConfigTypeDef master_config = {0};
|
||||
TIM_ClockConfigTypeDef clock_config = {0};
|
||||
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
|
||||
tim = (TIM_HandleTypeDef *)&device->tim_handle;
|
||||
|
||||
/* configure the timer to pwm mode */
|
||||
tim->Init.Prescaler = 0;
|
||||
tim->Init.CounterMode = TIM_COUNTERMODE_UP;
|
||||
tim->Init.Period = 0;
|
||||
tim->Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
||||
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4)
|
||||
tim->Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
||||
#endif
|
||||
|
||||
if (HAL_TIM_PWM_Init(tim) != HAL_OK)
|
||||
{
|
||||
LOG_E("%s pwm init failed", device->name);
|
||||
result = -RT_ERROR;
|
||||
goto __exit;
|
||||
}
|
||||
|
||||
clock_config.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
|
||||
if (HAL_TIM_ConfigClockSource(tim, &clock_config) != HAL_OK)
|
||||
{
|
||||
LOG_E("%s clock init failed", device->name);
|
||||
result = -RT_ERROR;
|
||||
goto __exit;
|
||||
}
|
||||
|
||||
master_config.MasterOutputTrigger = TIM_TRGO_RESET;
|
||||
master_config.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
||||
if (HAL_TIMEx_MasterConfigSynchronization(tim, &master_config) != HAL_OK)
|
||||
{
|
||||
LOG_E("%s master config failed", device->name);
|
||||
result = -RT_ERROR;
|
||||
goto __exit;
|
||||
}
|
||||
|
||||
oc_config.OCMode = TIM_OCMODE_PWM1;
|
||||
oc_config.Pulse = 0;
|
||||
oc_config.OCPolarity = TIM_OCPOLARITY_HIGH;
|
||||
oc_config.OCFastMode = TIM_OCFAST_DISABLE;
|
||||
oc_config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
|
||||
oc_config.OCIdleState = TIM_OCIDLESTATE_RESET;
|
||||
|
||||
/* config pwm channel */
|
||||
if (device->channel & 0x01)
|
||||
{
|
||||
if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_1) != HAL_OK)
|
||||
{
|
||||
LOG_E("%s channel1 config failed", device->name);
|
||||
result = -RT_ERROR;
|
||||
goto __exit;
|
||||
}
|
||||
}
|
||||
|
||||
if (device->channel & 0x02)
|
||||
{
|
||||
if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_2) != HAL_OK)
|
||||
{
|
||||
LOG_E("%s channel2 config failed", device->name);
|
||||
result = -RT_ERROR;
|
||||
goto __exit;
|
||||
}
|
||||
}
|
||||
|
||||
if (device->channel & 0x04)
|
||||
{
|
||||
if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_3) != HAL_OK)
|
||||
{
|
||||
LOG_E("%s channel3 config failed", device->name);
|
||||
result = -RT_ERROR;
|
||||
goto __exit;
|
||||
}
|
||||
}
|
||||
|
||||
if (device->channel & 0x08)
|
||||
{
|
||||
if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_4) != HAL_OK)
|
||||
{
|
||||
LOG_E("%s channel4 config failed", device->name);
|
||||
result = -RT_ERROR;
|
||||
goto __exit;
|
||||
}
|
||||
}
|
||||
|
||||
/* pwm pin configuration */
|
||||
HAL_TIM_MspPostInit(tim);
|
||||
|
||||
/* enable update request source */
|
||||
__HAL_TIM_URS_ENABLE(tim);
|
||||
|
||||
__exit:
|
||||
return result;
|
||||
}
|
||||
|
||||
static void pwm_get_channel(void)
|
||||
{
|
||||
#ifdef BSP_USING_PWM1_CH1
|
||||
stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 0;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM1_CH2
|
||||
stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 1;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM1_CH3
|
||||
stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 2;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM1_CH4
|
||||
stm32_pwm_obj[PWM1_INDEX].channel |= 1 << 3;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM2_CH1
|
||||
stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 0;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM2_CH2
|
||||
stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 1;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM2_CH3
|
||||
stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 2;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM2_CH4
|
||||
stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 3;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM3_CH1
|
||||
stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 0;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM3_CH2
|
||||
stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 1;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM3_CH3
|
||||
stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 2;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM3_CH4
|
||||
stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 3;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM4_CH1
|
||||
stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 0;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM4_CH2
|
||||
stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 1;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM4_CH3
|
||||
stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 2;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM4_CH4
|
||||
stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 3;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM5_CH1
|
||||
stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 0;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM5_CH2
|
||||
stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 1;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM5_CH3
|
||||
stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 2;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM5_CH4
|
||||
stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 3;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM6_CH1
|
||||
stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 0;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM6_CH2
|
||||
stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 1;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM6_CH3
|
||||
stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 2;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM6_CH4
|
||||
stm32_pwm_obj[PWM6_INDEX].channel |= 1 << 3;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM7_CH1
|
||||
stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 0;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM7_CH2
|
||||
stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 1;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM7_CH3
|
||||
stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 2;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM7_CH4
|
||||
stm32_pwm_obj[PWM7_INDEX].channel |= 1 << 3;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM8_CH1
|
||||
stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 0;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM8_CH2
|
||||
stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 1;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM8_CH3
|
||||
stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 2;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM8_CH4
|
||||
stm32_pwm_obj[PWM8_INDEX].channel |= 1 << 3;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM9_CH1
|
||||
stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 0;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM9_CH2
|
||||
stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 1;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM9_CH3
|
||||
stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 2;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM9_CH4
|
||||
stm32_pwm_obj[PWM9_INDEX].channel |= 1 << 3;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM12_CH1
|
||||
stm32_pwm_obj[PWM12_INDEX].channel |= 1 << 0;
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM12_CH2
|
||||
stm32_pwm_obj[PWM12_INDEX].channel |= 1 << 1;
|
||||
#endif
|
||||
}
|
||||
|
||||
static int stm32_pwm_init(void)
|
||||
{
|
||||
int i = 0;
|
||||
int result = RT_EOK;
|
||||
|
||||
pwm_get_channel();
|
||||
|
||||
for (i = 0; i < sizeof(stm32_pwm_obj) / sizeof(stm32_pwm_obj[0]); i++)
|
||||
{
|
||||
/* pwm init */
|
||||
if (stm32_hw_pwm_init(&stm32_pwm_obj[i]) != RT_EOK)
|
||||
{
|
||||
LOG_E("%s init failed", stm32_pwm_obj[i].name);
|
||||
result = -RT_ERROR;
|
||||
goto __exit;
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_D("%s init success", stm32_pwm_obj[i].name);
|
||||
|
||||
/* register pwm device */
|
||||
if (rt_device_pwm_register(&stm32_pwm_obj[i].pwm_device, stm32_pwm_obj[i].name, &drv_ops, &stm32_pwm_obj[i].tim_handle) == RT_EOK)
|
||||
{
|
||||
LOG_D("%s register success", stm32_pwm_obj[i].name);
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_E("%s register failed", stm32_pwm_obj[i].name);
|
||||
result = -RT_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
__exit:
|
||||
return result;
|
||||
}
|
||||
INIT_DEVICE_EXPORT(stm32_pwm_init);
|
||||
#endif /* RT_USING_PWM */
|
||||
398
drivers/drv_qspi.c
Normal file
398
drivers/drv_qspi.c
Normal file
@ -0,0 +1,398 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-27 zylx first version
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
#include<rtthread.h>
|
||||
#include<rtdevice.h>
|
||||
#include "drv_qspi.h"
|
||||
#include "drv_config.h"
|
||||
|
||||
#ifdef RT_USING_QSPI
|
||||
|
||||
#define DRV_DEBUG
|
||||
#define LOG_TAG "drv.qspi"
|
||||
#include <drv_log.h>
|
||||
|
||||
#if defined(BSP_USING_QSPI)
|
||||
|
||||
struct stm32_hw_spi_cs
|
||||
{
|
||||
uint16_t Pin;
|
||||
};
|
||||
|
||||
struct stm32_qspi_bus
|
||||
{
|
||||
QSPI_HandleTypeDef QSPI_Handler;
|
||||
char *bus_name;
|
||||
#ifdef BSP_QSPI_USING_DMA
|
||||
DMA_HandleTypeDef hdma_quadspi;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct rt_spi_bus _qspi_bus1;
|
||||
struct stm32_qspi_bus _stm32_qspi_bus;
|
||||
|
||||
static int stm32_qspi_init(struct rt_qspi_device *device, struct rt_qspi_configuration *qspi_cfg)
|
||||
{
|
||||
int result = RT_EOK;
|
||||
unsigned int i = 1;
|
||||
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
RT_ASSERT(qspi_cfg != RT_NULL);
|
||||
|
||||
struct rt_spi_configuration *cfg = &qspi_cfg->parent;
|
||||
struct stm32_qspi_bus *qspi_bus = device->parent.bus->parent.user_data;
|
||||
rt_memset(&qspi_bus->QSPI_Handler, 0, sizeof(qspi_bus->QSPI_Handler));
|
||||
|
||||
QSPI_HandleTypeDef QSPI_Handler_config = QSPI_BUS_CONFIG;
|
||||
qspi_bus->QSPI_Handler = QSPI_Handler_config;
|
||||
|
||||
while (cfg->max_hz < HAL_RCC_GetHCLKFreq() / (i + 1))
|
||||
{
|
||||
i++;
|
||||
if (i == 255)
|
||||
{
|
||||
LOG_E("QSPI init failed, QSPI frequency(%d) is too low.", cfg->max_hz);
|
||||
return -RT_ERROR;
|
||||
}
|
||||
}
|
||||
/* 80/(1+i) */
|
||||
qspi_bus->QSPI_Handler.Init.ClockPrescaler = i;
|
||||
|
||||
if (!(cfg->mode & RT_SPI_CPOL))
|
||||
{
|
||||
/* QSPI MODE0 */
|
||||
qspi_bus->QSPI_Handler.Init.ClockMode = QSPI_CLOCK_MODE_0;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* QSPI MODE3 */
|
||||
qspi_bus->QSPI_Handler.Init.ClockMode = QSPI_CLOCK_MODE_3;
|
||||
}
|
||||
|
||||
/* flash size */
|
||||
qspi_bus->QSPI_Handler.Init.FlashSize = POSITION_VAL(qspi_cfg->medium_size) - 1;
|
||||
|
||||
result = HAL_QSPI_Init(&qspi_bus->QSPI_Handler);
|
||||
if (result == HAL_OK)
|
||||
{
|
||||
LOG_D("qspi init success!");
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_E("qspi init failed (%d)!", result);
|
||||
}
|
||||
|
||||
#ifdef BSP_QSPI_USING_DMA
|
||||
/* QSPI interrupts must be enabled when using the HAL_QSPI_Receive_DMA */
|
||||
HAL_NVIC_SetPriority(QSPI_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(QSPI_IRQn);
|
||||
HAL_NVIC_SetPriority(QSPI_DMA_IRQ, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(QSPI_DMA_IRQ);
|
||||
|
||||
/* init QSPI DMA */
|
||||
if(QSPI_DMA_RCC == RCC_AHB1ENR_DMA1EN)
|
||||
{
|
||||
__HAL_RCC_DMA1_CLK_ENABLE();
|
||||
}
|
||||
else
|
||||
{
|
||||
__HAL_RCC_DMA2_CLK_ENABLE();
|
||||
}
|
||||
|
||||
HAL_DMA_DeInit(qspi_bus->QSPI_Handler.hdma);
|
||||
DMA_HandleTypeDef hdma_quadspi_config = QSPI_DMA_CONFIG;
|
||||
qspi_bus->hdma_quadspi = hdma_quadspi_config;
|
||||
|
||||
if (HAL_DMA_Init(&qspi_bus->hdma_quadspi) != HAL_OK)
|
||||
{
|
||||
LOG_E("qspi dma init failed (%d)!", result);
|
||||
}
|
||||
|
||||
__HAL_LINKDMA(&qspi_bus->QSPI_Handler, hdma, qspi_bus->hdma_quadspi);
|
||||
#endif /* BSP_QSPI_USING_DMA */
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static void qspi_send_cmd(struct stm32_qspi_bus *qspi_bus, struct rt_qspi_message *message)
|
||||
{
|
||||
RT_ASSERT(qspi_bus != RT_NULL);
|
||||
RT_ASSERT(message != RT_NULL);
|
||||
|
||||
QSPI_CommandTypeDef Cmdhandler;
|
||||
|
||||
/* set QSPI cmd struct */
|
||||
Cmdhandler.Instruction = message->instruction.content;
|
||||
Cmdhandler.Address = message->address.content;
|
||||
Cmdhandler.DummyCycles = message->dummy_cycles;
|
||||
if (message->instruction.qspi_lines == 0)
|
||||
{
|
||||
Cmdhandler.InstructionMode = QSPI_INSTRUCTION_NONE;
|
||||
}
|
||||
else if (message->instruction.qspi_lines == 1)
|
||||
{
|
||||
Cmdhandler.InstructionMode = QSPI_INSTRUCTION_1_LINE;
|
||||
}
|
||||
else if (message->instruction.qspi_lines == 2)
|
||||
{
|
||||
Cmdhandler.InstructionMode = QSPI_INSTRUCTION_2_LINES;
|
||||
}
|
||||
else if (message->instruction.qspi_lines == 4)
|
||||
{
|
||||
Cmdhandler.InstructionMode = QSPI_INSTRUCTION_4_LINES;
|
||||
}
|
||||
if (message->address.qspi_lines == 0)
|
||||
{
|
||||
Cmdhandler.AddressMode = QSPI_ADDRESS_NONE;
|
||||
}
|
||||
else if (message->address.qspi_lines == 1)
|
||||
{
|
||||
Cmdhandler.AddressMode = QSPI_ADDRESS_1_LINE;
|
||||
}
|
||||
else if (message->address.qspi_lines == 2)
|
||||
{
|
||||
Cmdhandler.AddressMode = QSPI_ADDRESS_2_LINES;
|
||||
}
|
||||
else if (message->address.qspi_lines == 4)
|
||||
{
|
||||
Cmdhandler.AddressMode = QSPI_ADDRESS_4_LINES;
|
||||
}
|
||||
if (message->address.size == 24)
|
||||
{
|
||||
Cmdhandler.AddressSize = QSPI_ADDRESS_24_BITS;
|
||||
}
|
||||
else
|
||||
{
|
||||
Cmdhandler.AddressSize = QSPI_ADDRESS_32_BITS;
|
||||
}
|
||||
if (message->qspi_data_lines == 0)
|
||||
{
|
||||
Cmdhandler.DataMode = QSPI_DATA_NONE;
|
||||
}
|
||||
else if (message->qspi_data_lines == 1)
|
||||
{
|
||||
Cmdhandler.DataMode = QSPI_DATA_1_LINE;
|
||||
}
|
||||
else if (message->qspi_data_lines == 2)
|
||||
{
|
||||
Cmdhandler.DataMode = QSPI_DATA_2_LINES;
|
||||
}
|
||||
else if (message->qspi_data_lines == 4)
|
||||
{
|
||||
Cmdhandler.DataMode = QSPI_DATA_4_LINES;
|
||||
}
|
||||
|
||||
Cmdhandler.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
|
||||
Cmdhandler.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
|
||||
Cmdhandler.DdrMode = QSPI_DDR_MODE_DISABLE;
|
||||
Cmdhandler.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
|
||||
Cmdhandler.NbData = message->parent.length;
|
||||
HAL_QSPI_Command(&qspi_bus->QSPI_Handler, &Cmdhandler, 5000);
|
||||
}
|
||||
|
||||
static rt_uint32_t qspixfer(struct rt_spi_device *device, struct rt_spi_message *message)
|
||||
{
|
||||
rt_size_t len = 0;
|
||||
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
RT_ASSERT(device->bus != RT_NULL);
|
||||
|
||||
struct rt_qspi_message *qspi_message = (struct rt_qspi_message *)message;
|
||||
struct stm32_qspi_bus *qspi_bus = device->bus->parent.user_data;
|
||||
#ifdef BSP_QSPI_USING_SOFTCS
|
||||
struct stm32_hw_spi_cs *cs = device->parent.user_data;
|
||||
#endif
|
||||
|
||||
const rt_uint8_t *sndb = message->send_buf;
|
||||
rt_uint8_t *rcvb = message->recv_buf;
|
||||
rt_int32_t length = message->length;
|
||||
|
||||
#ifdef BSP_QSPI_USING_SOFTCS
|
||||
if (message->cs_take)
|
||||
{
|
||||
rt_pin_write(cs->pin, 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* send data */
|
||||
if (sndb)
|
||||
{
|
||||
qspi_send_cmd(qspi_bus, qspi_message);
|
||||
if (qspi_message->parent.length != 0)
|
||||
{
|
||||
if (HAL_QSPI_Transmit(&qspi_bus->QSPI_Handler, (rt_uint8_t *)sndb, 5000) == HAL_OK)
|
||||
{
|
||||
len = length;
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_E("QSPI send data failed(%d)!", qspi_bus->QSPI_Handler.ErrorCode);
|
||||
qspi_bus->QSPI_Handler.State = HAL_QSPI_STATE_READY;
|
||||
goto __exit;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
len = 1;
|
||||
}
|
||||
}
|
||||
else if (rcvb)/* recv data */
|
||||
{
|
||||
qspi_send_cmd(qspi_bus, qspi_message);
|
||||
#ifdef BSP_QSPI_USING_DMA
|
||||
if (HAL_QSPI_Receive_DMA(&qspi_bus->QSPI_Handler, rcvb) == HAL_OK)
|
||||
#else
|
||||
if (HAL_QSPI_Receive(&qspi_bus->QSPI_Handler, rcvb, 5000) == HAL_OK)
|
||||
#endif
|
||||
{
|
||||
len = length;
|
||||
#ifdef BSP_QSPI_USING_DMA
|
||||
while (qspi_bus->QSPI_Handler.RxXferCount != 0);
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_E("QSPI recv data failed(%d)!", qspi_bus->QSPI_Handler.ErrorCode);
|
||||
qspi_bus->QSPI_Handler.State = HAL_QSPI_STATE_READY;
|
||||
goto __exit;
|
||||
}
|
||||
}
|
||||
|
||||
__exit:
|
||||
#ifdef BSP_QSPI_USING_SOFTCS
|
||||
if (message->cs_release)
|
||||
{
|
||||
rt_pin_write(cs->pin, 1);
|
||||
}
|
||||
#endif
|
||||
return len;
|
||||
}
|
||||
|
||||
static rt_err_t qspi_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration)
|
||||
{
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
RT_ASSERT(configuration != RT_NULL);
|
||||
|
||||
struct rt_qspi_device *qspi_device = (struct rt_qspi_device *)device;
|
||||
return stm32_qspi_init(qspi_device, &qspi_device->config);
|
||||
}
|
||||
|
||||
static const struct rt_spi_ops stm32_qspi_ops =
|
||||
{
|
||||
.configure = qspi_configure,
|
||||
.xfer = qspixfer,
|
||||
};
|
||||
|
||||
static int stm32_qspi_register_bus(struct stm32_qspi_bus *qspi_bus, const char *name)
|
||||
{
|
||||
RT_ASSERT(qspi_bus != RT_NULL);
|
||||
RT_ASSERT(name != RT_NULL);
|
||||
|
||||
_qspi_bus1.parent.user_data = qspi_bus;
|
||||
return rt_qspi_bus_register(&_qspi_bus1, name, &stm32_qspi_ops);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function attach device to QSPI bus.
|
||||
* @param device_name QSPI device name
|
||||
* @param pin QSPI cs pin number
|
||||
* @param data_line_width QSPI data lines width, such as 1, 2, 4
|
||||
* @param enter_qspi_mode Callback function that lets FLASH enter QSPI mode
|
||||
* @param exit_qspi_mode Callback function that lets FLASH exit QSPI mode
|
||||
* @retval 0 : success
|
||||
* -1 : failed
|
||||
*/
|
||||
rt_err_t stm32_qspi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin, rt_uint8_t data_line_width, void (*enter_qspi_mode)(), void (*exit_qspi_mode)())
|
||||
{
|
||||
struct rt_qspi_device *qspi_device = RT_NULL;
|
||||
struct stm32_hw_spi_cs *cs_pin = RT_NULL;
|
||||
rt_err_t result = RT_EOK;
|
||||
|
||||
RT_ASSERT(bus_name != RT_NULL);
|
||||
RT_ASSERT(device_name != RT_NULL);
|
||||
RT_ASSERT(data_line_width == 1 || data_line_width == 2 || data_line_width == 4);
|
||||
|
||||
qspi_device = (struct rt_qspi_device *)rt_malloc(sizeof(struct rt_qspi_device));
|
||||
if (qspi_device == RT_NULL)
|
||||
{
|
||||
LOG_E("no memory, qspi bus attach device failed!");
|
||||
result = RT_ENOMEM;
|
||||
goto __exit;
|
||||
}
|
||||
cs_pin = (struct stm32_hw_spi_cs *)rt_malloc(sizeof(struct stm32_hw_spi_cs));
|
||||
if (qspi_device == RT_NULL)
|
||||
{
|
||||
LOG_E("no memory, qspi bus attach device failed!");
|
||||
result = RT_ENOMEM;
|
||||
goto __exit;
|
||||
}
|
||||
|
||||
qspi_device->enter_qspi_mode = enter_qspi_mode;
|
||||
qspi_device->exit_qspi_mode = exit_qspi_mode;
|
||||
qspi_device->config.qspi_dl_width = data_line_width;
|
||||
|
||||
cs_pin->Pin = pin;
|
||||
#ifdef BSP_QSPI_USING_SOFTCS
|
||||
rt_pin_mode(pin, PIN_MODE_OUTPUT);
|
||||
rt_pin_write(pin, 1);
|
||||
#endif
|
||||
|
||||
result = rt_spi_bus_attach_device(&qspi_device->parent, device_name, bus_name, (void *)cs_pin);
|
||||
|
||||
__exit:
|
||||
if (result != RT_EOK)
|
||||
{
|
||||
if (qspi_device)
|
||||
{
|
||||
rt_free(qspi_device);
|
||||
}
|
||||
|
||||
if (cs_pin)
|
||||
{
|
||||
rt_free(cs_pin);
|
||||
}
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
#ifdef BSP_QSPI_USING_DMA
|
||||
void QSPI_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
HAL_QSPI_IRQHandler(&_stm32_qspi_bus.QSPI_Handler);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void QSPI_DMA_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
HAL_DMA_IRQHandler(&_stm32_qspi_bus.hdma_quadspi);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* BSP_QSPI_USING_DMA */
|
||||
|
||||
static int rt_hw_qspi_bus_init(void)
|
||||
{
|
||||
return stm32_qspi_register_bus(&_stm32_qspi_bus, "qspi1");
|
||||
}
|
||||
INIT_BOARD_EXPORT(rt_hw_qspi_bus_init);
|
||||
|
||||
#endif /* BSP_USING_QSPI */
|
||||
#endif /* RT_USING_QSPI */
|
||||
252
drivers/drv_rtc.c
Normal file
252
drivers/drv_rtc.c
Normal file
@ -0,0 +1,252 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-04 balanceTWK first version
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
#include<rtthread.h>
|
||||
#include<rtdevice.h>
|
||||
|
||||
#ifdef BSP_USING_ONCHIP_RTC
|
||||
|
||||
|
||||
#ifndef HAL_RTCEx_BKUPRead
|
||||
#define HAL_RTCEx_BKUPRead(x1, x2) (~BKUP_REG_DATA)
|
||||
#endif
|
||||
#ifndef HAL_RTCEx_BKUPWrite
|
||||
#define HAL_RTCEx_BKUPWrite(x1, x2, x3)
|
||||
#endif
|
||||
#ifndef RTC_BKP_DR1
|
||||
#define RTC_BKP_DR1 RT_NULL
|
||||
#endif
|
||||
|
||||
//#define DRV_DEBUG
|
||||
#define LOG_TAG "drv.rtc"
|
||||
#include <drv_log.h>
|
||||
|
||||
#define BKUP_REG_DATA 0xA5A5
|
||||
|
||||
static struct rt_device rtc;
|
||||
|
||||
static RTC_HandleTypeDef RTC_Handler;
|
||||
|
||||
static time_t get_rtc_timestamp(void)
|
||||
{
|
||||
RTC_TimeTypeDef RTC_TimeStruct = {0};
|
||||
RTC_DateTypeDef RTC_DateStruct = {0};
|
||||
struct tm tm_new;
|
||||
|
||||
HAL_RTC_GetTime(&RTC_Handler, &RTC_TimeStruct, RTC_FORMAT_BIN);
|
||||
HAL_RTC_GetDate(&RTC_Handler, &RTC_DateStruct, RTC_FORMAT_BIN);
|
||||
|
||||
tm_new.tm_sec = RTC_TimeStruct.Seconds;
|
||||
tm_new.tm_min = RTC_TimeStruct.Minutes;
|
||||
tm_new.tm_hour = RTC_TimeStruct.Hours;
|
||||
tm_new.tm_mday = RTC_DateStruct.Date;
|
||||
tm_new.tm_mon = RTC_DateStruct.Month - 1;
|
||||
tm_new.tm_year = RTC_DateStruct.Year + 100;
|
||||
|
||||
LOG_D("get rtc time.");
|
||||
return mktime(&tm_new);
|
||||
}
|
||||
|
||||
static rt_err_t set_rtc_time_stamp(time_t time_stamp)
|
||||
{
|
||||
RTC_TimeTypeDef RTC_TimeStruct = {0};
|
||||
RTC_DateTypeDef RTC_DateStruct = {0};
|
||||
struct tm *p_tm;
|
||||
|
||||
p_tm = localtime(&time_stamp);
|
||||
if (p_tm->tm_year < 100)
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
RTC_TimeStruct.Seconds = p_tm->tm_sec ;
|
||||
RTC_TimeStruct.Minutes = p_tm->tm_min ;
|
||||
RTC_TimeStruct.Hours = p_tm->tm_hour;
|
||||
RTC_DateStruct.Date = p_tm->tm_mday;
|
||||
RTC_DateStruct.Month = p_tm->tm_mon + 1 ;
|
||||
RTC_DateStruct.Year = p_tm->tm_year - 100;
|
||||
RTC_DateStruct.WeekDay = p_tm->tm_wday + 1;
|
||||
|
||||
if (HAL_RTC_SetTime(&RTC_Handler, &RTC_TimeStruct, RTC_FORMAT_BIN) != HAL_OK)
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
if (HAL_RTC_SetDate(&RTC_Handler, &RTC_DateStruct, RTC_FORMAT_BIN) != HAL_OK)
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
LOG_D("set rtc time.");
|
||||
HAL_RTCEx_BKUPWrite(&RTC_Handler, RTC_BKP_DR1, BKUP_REG_DATA);
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static void rt_rtc_init(void)
|
||||
{
|
||||
#ifndef SOC_SERIES_STM32H7
|
||||
__HAL_RCC_PWR_CLK_ENABLE();
|
||||
#endif
|
||||
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
#ifdef BSP_RTC_USING_LSI
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
|
||||
RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
|
||||
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
|
||||
#else
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
|
||||
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
|
||||
RCC_OscInitStruct.LSIState = RCC_LSI_OFF;
|
||||
#endif
|
||||
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
}
|
||||
|
||||
static rt_err_t rt_rtc_config(struct rt_device *dev)
|
||||
{
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||
|
||||
HAL_PWR_EnableBkUpAccess();
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
|
||||
#ifdef BSP_RTC_USING_LSI
|
||||
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
|
||||
#else
|
||||
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
|
||||
#endif
|
||||
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
|
||||
|
||||
/* Enable RTC Clock */
|
||||
__HAL_RCC_RTC_ENABLE();
|
||||
|
||||
RTC_Handler.Instance = RTC;
|
||||
if (HAL_RTCEx_BKUPRead(&RTC_Handler, RTC_BKP_DR1) != BKUP_REG_DATA)
|
||||
{
|
||||
LOG_I("RTC hasn't been configured, please use <date> command to config.");
|
||||
|
||||
#if defined(SOC_SERIES_STM32F1)
|
||||
RTC_Handler.Init.OutPut = RTC_OUTPUTSOURCE_NONE;
|
||||
RTC_Handler.Init.AsynchPrediv = RTC_AUTO_1_SECOND;
|
||||
#elif defined(SOC_SERIES_STM32F0)
|
||||
|
||||
/* set the frequency division */
|
||||
#ifdef BSP_RTC_USING_LSI
|
||||
RTC_Handler.Init.AsynchPrediv = 0XA0;
|
||||
RTC_Handler.Init.SynchPrediv = 0xFA;
|
||||
#else
|
||||
RTC_Handler.Init.AsynchPrediv = 0X7F;
|
||||
RTC_Handler.Init.SynchPrediv = 0x0130;
|
||||
#endif /* BSP_RTC_USING_LSI */
|
||||
|
||||
RTC_Handler.Init.HourFormat = RTC_HOURFORMAT_24;
|
||||
RTC_Handler.Init.OutPut = RTC_OUTPUT_DISABLE;
|
||||
RTC_Handler.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
|
||||
RTC_Handler.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
|
||||
#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32H7)
|
||||
|
||||
/* set the frequency division */
|
||||
#ifdef BSP_RTC_USING_LSI
|
||||
RTC_Handler.Init.AsynchPrediv = 0X7D;
|
||||
#else
|
||||
RTC_Handler.Init.AsynchPrediv = 0X7F;
|
||||
#endif /* BSP_RTC_USING_LSI */
|
||||
RTC_Handler.Init.SynchPrediv = 0XFF;
|
||||
|
||||
RTC_Handler.Init.HourFormat = RTC_HOURFORMAT_24;
|
||||
RTC_Handler.Init.OutPut = RTC_OUTPUT_DISABLE;
|
||||
RTC_Handler.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
|
||||
RTC_Handler.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
|
||||
#endif
|
||||
if (HAL_RTC_Init(&RTC_Handler) != HAL_OK)
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
}
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
RT_ASSERT(dev != RT_NULL);
|
||||
switch (cmd)
|
||||
{
|
||||
case RT_DEVICE_CTRL_RTC_GET_TIME:
|
||||
*(rt_uint32_t *)args = get_rtc_timestamp();
|
||||
LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args);
|
||||
break;
|
||||
|
||||
case RT_DEVICE_CTRL_RTC_SET_TIME:
|
||||
if (set_rtc_time_stamp(*(rt_uint32_t *)args))
|
||||
{
|
||||
result = -RT_ERROR;
|
||||
}
|
||||
LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args);
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
#ifdef RT_USING_DEVICE_OPS
|
||||
const static struct rt_device_ops rtc_ops =
|
||||
{
|
||||
RT_NULL,
|
||||
RT_NULL,
|
||||
RT_NULL,
|
||||
RT_NULL,
|
||||
RT_NULL,
|
||||
rt_rtc_control
|
||||
};
|
||||
#endif
|
||||
|
||||
static rt_err_t rt_hw_rtc_register(rt_device_t device, const char *name, rt_uint32_t flag)
|
||||
{
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
|
||||
rt_rtc_init();
|
||||
if (rt_rtc_config(device) != RT_EOK)
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
#ifdef RT_USING_DEVICE_OPS
|
||||
device->ops = &rtc_ops;
|
||||
#else
|
||||
device->init = RT_NULL;
|
||||
device->open = RT_NULL;
|
||||
device->close = RT_NULL;
|
||||
device->read = RT_NULL;
|
||||
device->write = RT_NULL;
|
||||
device->control = rt_rtc_control;
|
||||
#endif
|
||||
device->type = RT_Device_Class_RTC;
|
||||
device->rx_indicate = RT_NULL;
|
||||
device->tx_complete = RT_NULL;
|
||||
device->user_data = RT_NULL;
|
||||
|
||||
/* register a character device */
|
||||
return rt_device_register(device, name, flag);
|
||||
}
|
||||
|
||||
int rt_hw_rtc_init(void)
|
||||
{
|
||||
rt_err_t result;
|
||||
result = rt_hw_rtc_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR);
|
||||
if (result != RT_EOK)
|
||||
{
|
||||
LOG_E("rtc register err code: %d", result);
|
||||
return result;
|
||||
}
|
||||
LOG_D("rtc init success");
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_DEVICE_EXPORT(rt_hw_rtc_init);
|
||||
|
||||
#endif /* BSP_USING_ONCHIP_RTC */
|
||||
889
drivers/drv_sdio.c
Normal file
889
drivers/drv_sdio.c
Normal file
@ -0,0 +1,889 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-06-22 tyx first
|
||||
* 2018-12-12 balanceTWK first version
|
||||
* 2019-06-11 WillianChan Add SD card hot plug detection
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
#include "drv_sdio.h"
|
||||
#include "drv_config.h"
|
||||
#include<rtthread.h>
|
||||
#include<rtdevice.h>
|
||||
|
||||
#ifdef BSP_USING_SDIO
|
||||
|
||||
//#define DRV_DEBUG
|
||||
#define LOG_TAG "drv.sdio"
|
||||
#include <drv_log.h>
|
||||
|
||||
static struct stm32_sdio_config sdio_config = SDIO_BUS_CONFIG;
|
||||
static struct stm32_sdio_class sdio_obj;
|
||||
static struct rt_mmcsd_host *host;
|
||||
|
||||
#define SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS (100000)
|
||||
|
||||
#define RTHW_SDIO_LOCK(_sdio) rt_mutex_take(&_sdio->mutex, RT_WAITING_FOREVER)
|
||||
#define RTHW_SDIO_UNLOCK(_sdio) rt_mutex_release(&_sdio->mutex);
|
||||
|
||||
struct sdio_pkg
|
||||
{
|
||||
struct rt_mmcsd_cmd *cmd;
|
||||
void *buff;
|
||||
rt_uint32_t flag;
|
||||
};
|
||||
|
||||
struct rthw_sdio
|
||||
{
|
||||
struct rt_mmcsd_host *host;
|
||||
struct stm32_sdio_des sdio_des;
|
||||
struct rt_event event;
|
||||
struct rt_mutex mutex;
|
||||
struct sdio_pkg *pkg;
|
||||
};
|
||||
|
||||
ALIGN(SDIO_ALIGN_LEN)
|
||||
static rt_uint8_t cache_buf[SDIO_BUFF_SIZE];
|
||||
|
||||
static rt_uint32_t stm32_sdio_clk_get(struct stm32_sdio *hw_sdio)
|
||||
{
|
||||
return SDIO_CLOCK_FREQ;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function get order from sdio.
|
||||
* @param data
|
||||
* @retval sdio order
|
||||
*/
|
||||
static int get_order(rt_uint32_t data)
|
||||
{
|
||||
int order = 0;
|
||||
|
||||
switch (data)
|
||||
{
|
||||
case 1:
|
||||
order = 0;
|
||||
break;
|
||||
case 2:
|
||||
order = 1;
|
||||
break;
|
||||
case 4:
|
||||
order = 2;
|
||||
break;
|
||||
case 8:
|
||||
order = 3;
|
||||
break;
|
||||
case 16:
|
||||
order = 4;
|
||||
break;
|
||||
case 32:
|
||||
order = 5;
|
||||
break;
|
||||
case 64:
|
||||
order = 6;
|
||||
break;
|
||||
case 128:
|
||||
order = 7;
|
||||
break;
|
||||
case 256:
|
||||
order = 8;
|
||||
break;
|
||||
case 512:
|
||||
order = 9;
|
||||
break;
|
||||
case 1024:
|
||||
order = 10;
|
||||
break;
|
||||
case 2048:
|
||||
order = 11;
|
||||
break;
|
||||
case 4096:
|
||||
order = 12;
|
||||
break;
|
||||
case 8192:
|
||||
order = 13;
|
||||
break;
|
||||
case 16384:
|
||||
order = 14;
|
||||
break;
|
||||
default :
|
||||
order = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
return order;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function wait sdio completed.
|
||||
* @param sdio rthw_sdio
|
||||
* @retval None
|
||||
*/
|
||||
static void rthw_sdio_wait_completed(struct rthw_sdio *sdio)
|
||||
{
|
||||
rt_uint32_t status;
|
||||
struct rt_mmcsd_cmd *cmd = sdio->pkg->cmd;
|
||||
struct rt_mmcsd_data *data = cmd->data;
|
||||
struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
|
||||
|
||||
if (rt_event_recv(&sdio->event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
|
||||
rt_tick_from_millisecond(5000), &status) != RT_EOK)
|
||||
{
|
||||
LOG_E("wait completed timeout");
|
||||
cmd->err = -RT_ETIMEOUT;
|
||||
return;
|
||||
}
|
||||
|
||||
if (sdio->pkg == RT_NULL)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
cmd->resp[0] = hw_sdio->resp1;
|
||||
cmd->resp[1] = hw_sdio->resp2;
|
||||
cmd->resp[2] = hw_sdio->resp3;
|
||||
cmd->resp[3] = hw_sdio->resp4;
|
||||
|
||||
if (status & HW_SDIO_ERRORS)
|
||||
{
|
||||
if ((status & HW_SDIO_IT_CCRCFAIL) && (resp_type(cmd) & (RESP_R3 | RESP_R4)))
|
||||
{
|
||||
cmd->err = RT_EOK;
|
||||
}
|
||||
else
|
||||
{
|
||||
cmd->err = -RT_ERROR;
|
||||
}
|
||||
|
||||
if (status & HW_SDIO_IT_CTIMEOUT)
|
||||
{
|
||||
cmd->err = -RT_ETIMEOUT;
|
||||
}
|
||||
|
||||
if (status & HW_SDIO_IT_DCRCFAIL)
|
||||
{
|
||||
data->err = -RT_ERROR;
|
||||
}
|
||||
|
||||
if (status & HW_SDIO_IT_DTIMEOUT)
|
||||
{
|
||||
data->err = -RT_ETIMEOUT;
|
||||
}
|
||||
|
||||
if (cmd->err == RT_EOK)
|
||||
{
|
||||
LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_D("err:0x%08x, %s%s%s%s%s%s%s cmd:%d arg:0x%08x rw:%c len:%d blksize:%d",
|
||||
status,
|
||||
status & HW_SDIO_IT_CCRCFAIL ? "CCRCFAIL " : "",
|
||||
status & HW_SDIO_IT_DCRCFAIL ? "DCRCFAIL " : "",
|
||||
status & HW_SDIO_IT_CTIMEOUT ? "CTIMEOUT " : "",
|
||||
status & HW_SDIO_IT_DTIMEOUT ? "DTIMEOUT " : "",
|
||||
status & HW_SDIO_IT_TXUNDERR ? "TXUNDERR " : "",
|
||||
status & HW_SDIO_IT_RXOVERR ? "RXOVERR " : "",
|
||||
status == 0 ? "NULL" : "",
|
||||
cmd->cmd_code,
|
||||
cmd->arg,
|
||||
data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-',
|
||||
data ? data->blks * data->blksize : 0,
|
||||
data ? data->blksize : 0
|
||||
);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
cmd->err = RT_EOK;
|
||||
LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function transfer data by dma.
|
||||
* @param sdio rthw_sdio
|
||||
* @param pkg sdio package
|
||||
* @retval None
|
||||
*/
|
||||
static void rthw_sdio_transfer_by_dma(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
|
||||
{
|
||||
struct rt_mmcsd_data *data;
|
||||
int size;
|
||||
void *buff;
|
||||
struct stm32_sdio *hw_sdio;
|
||||
|
||||
if ((RT_NULL == pkg) || (RT_NULL == sdio))
|
||||
{
|
||||
LOG_E("rthw_sdio_transfer_by_dma invalid args");
|
||||
return;
|
||||
}
|
||||
|
||||
data = pkg->cmd->data;
|
||||
if (RT_NULL == data)
|
||||
{
|
||||
LOG_E("rthw_sdio_transfer_by_dma invalid args");
|
||||
return;
|
||||
}
|
||||
|
||||
buff = pkg->buff;
|
||||
if (RT_NULL == buff)
|
||||
{
|
||||
LOG_E("rthw_sdio_transfer_by_dma invalid args");
|
||||
return;
|
||||
}
|
||||
hw_sdio = sdio->sdio_des.hw_sdio;
|
||||
size = data->blks * data->blksize;
|
||||
|
||||
if (data->flags & DATA_DIR_WRITE)
|
||||
{
|
||||
sdio->sdio_des.txconfig((rt_uint32_t *)buff, (rt_uint32_t *)&hw_sdio->fifo, size);
|
||||
hw_sdio->dctrl |= HW_SDIO_DMA_ENABLE;
|
||||
}
|
||||
else if (data->flags & DATA_DIR_READ)
|
||||
{
|
||||
sdio->sdio_des.rxconfig((rt_uint32_t *)&hw_sdio->fifo, (rt_uint32_t *)buff, size);
|
||||
hw_sdio->dctrl |= HW_SDIO_DMA_ENABLE | HW_SDIO_DPSM_ENABLE;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function send command.
|
||||
* @param sdio rthw_sdio
|
||||
* @param pkg sdio package
|
||||
* @retval None
|
||||
*/
|
||||
static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
|
||||
{
|
||||
struct rt_mmcsd_cmd *cmd = pkg->cmd;
|
||||
struct rt_mmcsd_data *data = cmd->data;
|
||||
struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
|
||||
rt_uint32_t reg_cmd;
|
||||
|
||||
/* save pkg */
|
||||
sdio->pkg = pkg;
|
||||
|
||||
LOG_D("CMD:%d ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c len:%d blksize:%d",
|
||||
cmd->cmd_code,
|
||||
cmd->arg,
|
||||
resp_type(cmd) == RESP_NONE ? "NONE" : "",
|
||||
resp_type(cmd) == RESP_R1 ? "R1" : "",
|
||||
resp_type(cmd) == RESP_R1B ? "R1B" : "",
|
||||
resp_type(cmd) == RESP_R2 ? "R2" : "",
|
||||
resp_type(cmd) == RESP_R3 ? "R3" : "",
|
||||
resp_type(cmd) == RESP_R4 ? "R4" : "",
|
||||
resp_type(cmd) == RESP_R5 ? "R5" : "",
|
||||
resp_type(cmd) == RESP_R6 ? "R6" : "",
|
||||
resp_type(cmd) == RESP_R7 ? "R7" : "",
|
||||
data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-',
|
||||
data ? data->blks * data->blksize : 0,
|
||||
data ? data->blksize : 0
|
||||
);
|
||||
|
||||
/* config cmd reg */
|
||||
reg_cmd = cmd->cmd_code | HW_SDIO_CPSM_ENABLE;
|
||||
if (resp_type(cmd) == RESP_NONE)
|
||||
reg_cmd |= HW_SDIO_RESPONSE_NO;
|
||||
else if (resp_type(cmd) == RESP_R2)
|
||||
reg_cmd |= HW_SDIO_RESPONSE_LONG;
|
||||
else
|
||||
reg_cmd |= HW_SDIO_RESPONSE_SHORT;
|
||||
|
||||
/* config data reg */
|
||||
if (data != RT_NULL)
|
||||
{
|
||||
rt_uint32_t dir = 0;
|
||||
rt_uint32_t size = data->blks * data->blksize;
|
||||
int order;
|
||||
|
||||
hw_sdio->dctrl = 0;
|
||||
hw_sdio->dtimer = HW_SDIO_DATATIMEOUT;
|
||||
hw_sdio->dlen = size;
|
||||
order = get_order(data->blksize);
|
||||
dir = (data->flags & DATA_DIR_READ) ? HW_SDIO_TO_HOST : 0;
|
||||
hw_sdio->dctrl = HW_SDIO_IO_ENABLE | (order << 4) | dir;
|
||||
}
|
||||
|
||||
/* transfer config */
|
||||
if (data != RT_NULL)
|
||||
{
|
||||
rthw_sdio_transfer_by_dma(sdio, pkg);
|
||||
}
|
||||
|
||||
/* open irq */
|
||||
hw_sdio->mask |= HW_SDIO_IT_CMDSENT | HW_SDIO_IT_CMDREND | HW_SDIO_ERRORS;
|
||||
if (data != RT_NULL)
|
||||
{
|
||||
hw_sdio->mask |= HW_SDIO_IT_DATAEND;
|
||||
}
|
||||
|
||||
/* send cmd */
|
||||
hw_sdio->arg = cmd->arg;
|
||||
hw_sdio->cmd = reg_cmd;
|
||||
|
||||
/* wait completed */
|
||||
rthw_sdio_wait_completed(sdio);
|
||||
|
||||
/* Waiting for data to be sent to completion */
|
||||
if (data != RT_NULL)
|
||||
{
|
||||
volatile rt_uint32_t count = SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS;
|
||||
|
||||
while (count && (hw_sdio->sta & (HW_SDIO_IT_TXACT | HW_SDIO_IT_RXACT)))
|
||||
{
|
||||
count--;
|
||||
}
|
||||
|
||||
if ((count == 0) || (hw_sdio->sta & HW_SDIO_ERRORS))
|
||||
{
|
||||
cmd->err = -RT_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/* close irq, keep sdio irq */
|
||||
hw_sdio->mask = hw_sdio->mask & HW_SDIO_IT_SDIOIT ? HW_SDIO_IT_SDIOIT : 0x00;
|
||||
|
||||
/* clear pkg */
|
||||
sdio->pkg = RT_NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function send sdio request.
|
||||
* @param sdio rthw_sdio
|
||||
* @param req request
|
||||
* @retval None
|
||||
*/
|
||||
static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
|
||||
{
|
||||
struct sdio_pkg pkg;
|
||||
struct rthw_sdio *sdio = host->private_data;
|
||||
struct rt_mmcsd_data *data;
|
||||
|
||||
RTHW_SDIO_LOCK(sdio);
|
||||
|
||||
if (req->cmd != RT_NULL)
|
||||
{
|
||||
memset(&pkg, 0, sizeof(pkg));
|
||||
data = req->cmd->data;
|
||||
pkg.cmd = req->cmd;
|
||||
|
||||
if (data != RT_NULL)
|
||||
{
|
||||
rt_uint32_t size = data->blks * data->blksize;
|
||||
|
||||
RT_ASSERT(size <= SDIO_BUFF_SIZE);
|
||||
|
||||
pkg.buff = data->buf;
|
||||
if ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1))
|
||||
{
|
||||
pkg.buff = cache_buf;
|
||||
if (data->flags & DATA_DIR_WRITE)
|
||||
{
|
||||
memcpy(cache_buf, data->buf, size);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
rthw_sdio_send_command(sdio, &pkg);
|
||||
|
||||
if ((data != RT_NULL) && (data->flags & DATA_DIR_READ) && ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1)))
|
||||
{
|
||||
memcpy(data->buf, cache_buf, data->blksize * data->blks);
|
||||
}
|
||||
}
|
||||
|
||||
if (req->stop != RT_NULL)
|
||||
{
|
||||
memset(&pkg, 0, sizeof(pkg));
|
||||
pkg.cmd = req->stop;
|
||||
rthw_sdio_send_command(sdio, &pkg);
|
||||
}
|
||||
|
||||
RTHW_SDIO_UNLOCK(sdio);
|
||||
|
||||
mmcsd_req_complete(sdio->host);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function config sdio.
|
||||
* @param host rt_mmcsd_host
|
||||
* @param io_cfg rt_mmcsd_io_cfg
|
||||
* @retval None
|
||||
*/
|
||||
static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
|
||||
{
|
||||
rt_uint32_t clkcr, div, clk_src;
|
||||
rt_uint32_t clk = io_cfg->clock;
|
||||
struct rthw_sdio *sdio = host->private_data;
|
||||
struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
|
||||
|
||||
clk_src = sdio->sdio_des.clk_get(sdio->sdio_des.hw_sdio);
|
||||
if (clk_src < 400 * 1000)
|
||||
{
|
||||
LOG_E("The clock rate is too low! rata:%d", clk_src);
|
||||
return;
|
||||
}
|
||||
|
||||
if (clk > host->freq_max) clk = host->freq_max;
|
||||
|
||||
if (clk > clk_src)
|
||||
{
|
||||
LOG_W("Setting rate is greater than clock source rate.");
|
||||
clk = clk_src;
|
||||
}
|
||||
|
||||
LOG_D("clk:%d width:%s%s%s power:%s%s%s",
|
||||
clk,
|
||||
io_cfg->bus_width == MMCSD_BUS_WIDTH_8 ? "8" : "",
|
||||
io_cfg->bus_width == MMCSD_BUS_WIDTH_4 ? "4" : "",
|
||||
io_cfg->bus_width == MMCSD_BUS_WIDTH_1 ? "1" : "",
|
||||
io_cfg->power_mode == MMCSD_POWER_OFF ? "OFF" : "",
|
||||
io_cfg->power_mode == MMCSD_POWER_UP ? "UP" : "",
|
||||
io_cfg->power_mode == MMCSD_POWER_ON ? "ON" : ""
|
||||
);
|
||||
|
||||
RTHW_SDIO_LOCK(sdio);
|
||||
|
||||
div = clk_src / clk;
|
||||
if ((clk == 0) || (div == 0))
|
||||
{
|
||||
clkcr = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (div < 2)
|
||||
{
|
||||
div = 2;
|
||||
}
|
||||
else if (div > 0xFF)
|
||||
{
|
||||
div = 0xFF;
|
||||
}
|
||||
div -= 2;
|
||||
clkcr = div | HW_SDIO_CLK_ENABLE;
|
||||
}
|
||||
|
||||
if (io_cfg->bus_width == MMCSD_BUS_WIDTH_8)
|
||||
{
|
||||
clkcr |= HW_SDIO_BUSWIDE_8B;
|
||||
}
|
||||
else if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4)
|
||||
{
|
||||
clkcr |= HW_SDIO_BUSWIDE_4B;
|
||||
}
|
||||
else
|
||||
{
|
||||
clkcr |= HW_SDIO_BUSWIDE_1B;
|
||||
}
|
||||
|
||||
hw_sdio->clkcr = clkcr;
|
||||
|
||||
switch (io_cfg->power_mode)
|
||||
{
|
||||
case MMCSD_POWER_OFF:
|
||||
hw_sdio->power = HW_SDIO_POWER_OFF;
|
||||
break;
|
||||
case MMCSD_POWER_UP:
|
||||
hw_sdio->power = HW_SDIO_POWER_UP;
|
||||
break;
|
||||
case MMCSD_POWER_ON:
|
||||
hw_sdio->power = HW_SDIO_POWER_ON;
|
||||
break;
|
||||
default:
|
||||
LOG_W("unknown power_mode %d", io_cfg->power_mode);
|
||||
break;
|
||||
}
|
||||
|
||||
RTHW_SDIO_UNLOCK(sdio);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function update sdio interrupt.
|
||||
* @param host rt_mmcsd_host
|
||||
* @param enable
|
||||
* @retval None
|
||||
*/
|
||||
void rthw_sdio_irq_update(struct rt_mmcsd_host *host, rt_int32_t enable)
|
||||
{
|
||||
struct rthw_sdio *sdio = host->private_data;
|
||||
struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
|
||||
|
||||
if (enable)
|
||||
{
|
||||
LOG_D("enable sdio irq");
|
||||
hw_sdio->mask |= HW_SDIO_IT_SDIOIT;
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_D("disable sdio irq");
|
||||
hw_sdio->mask &= ~HW_SDIO_IT_SDIOIT;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function delect sdcard.
|
||||
* @param host rt_mmcsd_host
|
||||
* @retval 0x01
|
||||
*/
|
||||
static rt_int32_t rthw_sd_delect(struct rt_mmcsd_host *host)
|
||||
{
|
||||
LOG_D("try to detect device");
|
||||
return 0x01;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function interrupt process function.
|
||||
* @param host rt_mmcsd_host
|
||||
* @retval None
|
||||
*/
|
||||
void rthw_sdio_irq_process(struct rt_mmcsd_host *host)
|
||||
{
|
||||
int complete = 0;
|
||||
struct rthw_sdio *sdio = host->private_data;
|
||||
struct stm32_sdio *hw_sdio = sdio->sdio_des.hw_sdio;
|
||||
rt_uint32_t intstatus = hw_sdio->sta;
|
||||
|
||||
if (intstatus & HW_SDIO_ERRORS)
|
||||
{
|
||||
hw_sdio->icr = HW_SDIO_ERRORS;
|
||||
complete = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (intstatus & HW_SDIO_IT_CMDREND)
|
||||
{
|
||||
hw_sdio->icr = HW_SDIO_IT_CMDREND;
|
||||
|
||||
if (sdio->pkg != RT_NULL)
|
||||
{
|
||||
if (!sdio->pkg->cmd->data)
|
||||
{
|
||||
complete = 1;
|
||||
}
|
||||
else if ((sdio->pkg->cmd->data->flags & DATA_DIR_WRITE))
|
||||
{
|
||||
hw_sdio->dctrl |= HW_SDIO_DPSM_ENABLE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (intstatus & HW_SDIO_IT_CMDSENT)
|
||||
{
|
||||
hw_sdio->icr = HW_SDIO_IT_CMDSENT;
|
||||
|
||||
if (resp_type(sdio->pkg->cmd) == RESP_NONE)
|
||||
{
|
||||
complete = 1;
|
||||
}
|
||||
}
|
||||
|
||||
if (intstatus & HW_SDIO_IT_DATAEND)
|
||||
{
|
||||
hw_sdio->icr = HW_SDIO_IT_DATAEND;
|
||||
complete = 1;
|
||||
}
|
||||
}
|
||||
|
||||
if ((intstatus & HW_SDIO_IT_SDIOIT) && (hw_sdio->mask & HW_SDIO_IT_SDIOIT))
|
||||
{
|
||||
hw_sdio->icr = HW_SDIO_IT_SDIOIT;
|
||||
sdio_irq_wakeup(host);
|
||||
}
|
||||
|
||||
if (complete)
|
||||
{
|
||||
hw_sdio->mask &= ~HW_SDIO_ERRORS;
|
||||
rt_event_send(&sdio->event, intstatus);
|
||||
}
|
||||
}
|
||||
|
||||
static const struct rt_mmcsd_host_ops ops =
|
||||
{
|
||||
rthw_sdio_request,
|
||||
rthw_sdio_iocfg,
|
||||
rthw_sd_delect,
|
||||
rthw_sdio_irq_update,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief This function create mmcsd host.
|
||||
* @param sdio_des stm32_sdio_des
|
||||
* @retval rt_mmcsd_host
|
||||
*/
|
||||
struct rt_mmcsd_host *sdio_host_create(struct stm32_sdio_des *sdio_des)
|
||||
{
|
||||
struct rt_mmcsd_host *host;
|
||||
struct rthw_sdio *sdio = RT_NULL;
|
||||
|
||||
if ((sdio_des == RT_NULL) || (sdio_des->txconfig == RT_NULL) || (sdio_des->rxconfig == RT_NULL))
|
||||
{
|
||||
LOG_E("L:%d F:%s %s %s %s",
|
||||
(sdio_des == RT_NULL ? "sdio_des is NULL" : ""),
|
||||
(sdio_des ? (sdio_des->txconfig ? "txconfig is NULL" : "") : ""),
|
||||
(sdio_des ? (sdio_des->rxconfig ? "rxconfig is NULL" : "") : "")
|
||||
);
|
||||
return RT_NULL;
|
||||
}
|
||||
|
||||
sdio = rt_malloc(sizeof(struct rthw_sdio));
|
||||
if (sdio == RT_NULL)
|
||||
{
|
||||
LOG_E("L:%d F:%s malloc rthw_sdio fail");
|
||||
return RT_NULL;
|
||||
}
|
||||
rt_memset(sdio, 0, sizeof(struct rthw_sdio));
|
||||
|
||||
host = mmcsd_alloc_host();
|
||||
if (host == RT_NULL)
|
||||
{
|
||||
LOG_E("L:%d F:%s mmcsd alloc host fail");
|
||||
rt_free(sdio);
|
||||
return RT_NULL;
|
||||
}
|
||||
|
||||
rt_memcpy(&sdio->sdio_des, sdio_des, sizeof(struct stm32_sdio_des));
|
||||
sdio->sdio_des.hw_sdio = (sdio_des->hw_sdio == RT_NULL ? (struct stm32_sdio *)SDIO_BASE_ADDRESS : sdio_des->hw_sdio);
|
||||
sdio->sdio_des.clk_get = (sdio_des->clk_get == RT_NULL ? stm32_sdio_clk_get : sdio_des->clk_get);
|
||||
|
||||
rt_event_init(&sdio->event, "sdio", RT_IPC_FLAG_FIFO);
|
||||
rt_mutex_init(&sdio->mutex, "sdio", RT_IPC_FLAG_FIFO);
|
||||
|
||||
/* set host defautl attributes */
|
||||
host->ops = &ops;
|
||||
host->freq_min = 400 * 1000;
|
||||
host->freq_max = SDIO_MAX_FREQ;
|
||||
host->valid_ocr = 0X00FFFF80;/* The voltage range supported is 1.65v-3.6v */
|
||||
#ifndef SDIO_USING_1_BIT
|
||||
host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ;
|
||||
#else
|
||||
host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ;
|
||||
#endif
|
||||
host->max_seg_size = SDIO_BUFF_SIZE;
|
||||
host->max_dma_segs = 1;
|
||||
host->max_blk_size = 512;
|
||||
host->max_blk_count = 512;
|
||||
|
||||
/* link up host and sdio */
|
||||
sdio->host = host;
|
||||
host->private_data = sdio;
|
||||
|
||||
rthw_sdio_irq_update(host, 1);
|
||||
|
||||
/* ready to change */
|
||||
mmcsd_change(host);
|
||||
|
||||
return host;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function configures the DMATX.
|
||||
* @param BufferSRC: pointer to the source buffer
|
||||
* @param BufferSize: buffer size
|
||||
* @retval None
|
||||
*/
|
||||
void SD_LowLevel_DMA_TxConfig(uint32_t *src, uint32_t *dst, uint32_t BufferSize)
|
||||
{
|
||||
#if defined(SOC_SERIES_STM32F1)
|
||||
static uint32_t size = 0;
|
||||
size += BufferSize * 4;
|
||||
sdio_obj.cfg = &sdio_config;
|
||||
sdio_obj.dma.handle_tx.Instance = sdio_config.dma_tx.Instance;
|
||||
sdio_obj.dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
|
||||
sdio_obj.dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
|
||||
sdio_obj.dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE;
|
||||
sdio_obj.dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
|
||||
sdio_obj.dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE;
|
||||
sdio_obj.dma.handle_tx.Init.Priority = DMA_PRIORITY_MEDIUM;
|
||||
/* DMA_PFCTRL */
|
||||
HAL_DMA_DeInit(&sdio_obj.dma.handle_tx);
|
||||
HAL_DMA_Init(&sdio_obj.dma.handle_tx);
|
||||
|
||||
HAL_DMA_Start(&sdio_obj.dma.handle_tx, (uint32_t)src, (uint32_t)dst, BufferSize);
|
||||
|
||||
#elif defined(SOC_SERIES_STM32L4)
|
||||
static uint32_t size = 0;
|
||||
size += BufferSize * 4;
|
||||
sdio_obj.cfg = &sdio_config;
|
||||
sdio_obj.dma.handle_tx.Instance = sdio_config.dma_tx.Instance;
|
||||
sdio_obj.dma.handle_tx.Init.Request = sdio_config.dma_tx.request;
|
||||
sdio_obj.dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
|
||||
sdio_obj.dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE;
|
||||
sdio_obj.dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE;
|
||||
sdio_obj.dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
|
||||
sdio_obj.dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
|
||||
sdio_obj.dma.handle_tx.Init.Mode = DMA_NORMAL;
|
||||
sdio_obj.dma.handle_tx.Init.Priority = DMA_PRIORITY_MEDIUM;
|
||||
|
||||
HAL_DMA_DeInit(&sdio_obj.dma.handle_tx);
|
||||
HAL_DMA_Init(&sdio_obj.dma.handle_tx);
|
||||
|
||||
HAL_DMA_Start(&sdio_obj.dma.handle_tx, (uint32_t)src, (uint32_t)dst, BufferSize);
|
||||
#else
|
||||
static uint32_t size = 0;
|
||||
size += BufferSize * 4;
|
||||
sdio_obj.cfg = &sdio_config;
|
||||
sdio_obj.dma.handle_tx.Instance = sdio_config.dma_tx.Instance;
|
||||
sdio_obj.dma.handle_tx.Init.Channel = sdio_config.dma_tx.channel;
|
||||
sdio_obj.dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
|
||||
sdio_obj.dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE;
|
||||
sdio_obj.dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE;
|
||||
sdio_obj.dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
|
||||
sdio_obj.dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
|
||||
sdio_obj.dma.handle_tx.Init.Mode = DMA_PFCTRL;
|
||||
sdio_obj.dma.handle_tx.Init.Priority = DMA_PRIORITY_MEDIUM;
|
||||
sdio_obj.dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
|
||||
sdio_obj.dma.handle_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
|
||||
sdio_obj.dma.handle_tx.Init.MemBurst = DMA_MBURST_INC4;
|
||||
sdio_obj.dma.handle_tx.Init.PeriphBurst = DMA_PBURST_INC4;
|
||||
/* DMA_PFCTRL */
|
||||
HAL_DMA_DeInit(&sdio_obj.dma.handle_tx);
|
||||
HAL_DMA_Init(&sdio_obj.dma.handle_tx);
|
||||
|
||||
HAL_DMA_Start(&sdio_obj.dma.handle_tx, (uint32_t)src, (uint32_t)dst, BufferSize);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function configures the DMARX.
|
||||
* @param BufferDST: pointer to the destination buffer
|
||||
* @param BufferSize: buffer size
|
||||
* @retval None
|
||||
*/
|
||||
void SD_LowLevel_DMA_RxConfig(uint32_t *src, uint32_t *dst, uint32_t BufferSize)
|
||||
{
|
||||
#if defined(SOC_SERIES_STM32F1)
|
||||
sdio_obj.cfg = &sdio_config;
|
||||
sdio_obj.dma.handle_rx.Instance = sdio_config.dma_tx.Instance;
|
||||
sdio_obj.dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
||||
sdio_obj.dma.handle_rx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
|
||||
sdio_obj.dma.handle_rx.Init.MemInc = DMA_MINC_ENABLE;
|
||||
sdio_obj.dma.handle_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
|
||||
sdio_obj.dma.handle_rx.Init.PeriphInc = DMA_PINC_DISABLE;
|
||||
sdio_obj.dma.handle_rx.Init.Priority = DMA_PRIORITY_MEDIUM;
|
||||
|
||||
HAL_DMA_DeInit(&sdio_obj.dma.handle_rx);
|
||||
HAL_DMA_Init(&sdio_obj.dma.handle_rx);
|
||||
|
||||
HAL_DMA_Start(&sdio_obj.dma.handle_rx, (uint32_t)src, (uint32_t)dst, BufferSize);
|
||||
#elif defined(SOC_SERIES_STM32L4)
|
||||
sdio_obj.cfg = &sdio_config;
|
||||
sdio_obj.dma.handle_rx.Instance = sdio_config.dma_tx.Instance;
|
||||
sdio_obj.dma.handle_rx.Init.Request = sdio_config.dma_tx.request;
|
||||
sdio_obj.dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
||||
sdio_obj.dma.handle_rx.Init.PeriphInc = DMA_PINC_DISABLE;
|
||||
sdio_obj.dma.handle_rx.Init.MemInc = DMA_MINC_ENABLE;
|
||||
sdio_obj.dma.handle_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
|
||||
sdio_obj.dma.handle_rx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
|
||||
sdio_obj.dma.handle_rx.Init.Mode = DMA_NORMAL;
|
||||
sdio_obj.dma.handle_rx.Init.Priority = DMA_PRIORITY_LOW;
|
||||
|
||||
HAL_DMA_DeInit(&sdio_obj.dma.handle_rx);
|
||||
HAL_DMA_Init(&sdio_obj.dma.handle_rx);
|
||||
|
||||
HAL_DMA_Start(&sdio_obj.dma.handle_rx, (uint32_t)src, (uint32_t)dst, BufferSize);
|
||||
#else
|
||||
sdio_obj.cfg = &sdio_config;
|
||||
sdio_obj.dma.handle_rx.Instance = sdio_config.dma_tx.Instance;
|
||||
sdio_obj.dma.handle_rx.Init.Channel = sdio_config.dma_tx.channel;
|
||||
sdio_obj.dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
||||
sdio_obj.dma.handle_rx.Init.PeriphInc = DMA_PINC_DISABLE;
|
||||
sdio_obj.dma.handle_rx.Init.MemInc = DMA_MINC_ENABLE;
|
||||
sdio_obj.dma.handle_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
|
||||
sdio_obj.dma.handle_rx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
|
||||
sdio_obj.dma.handle_rx.Init.Mode = DMA_PFCTRL;
|
||||
sdio_obj.dma.handle_rx.Init.Priority = DMA_PRIORITY_MEDIUM;
|
||||
sdio_obj.dma.handle_rx.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
|
||||
sdio_obj.dma.handle_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
|
||||
sdio_obj.dma.handle_rx.Init.MemBurst = DMA_MBURST_INC4;
|
||||
sdio_obj.dma.handle_rx.Init.PeriphBurst = DMA_PBURST_INC4;
|
||||
|
||||
HAL_DMA_DeInit(&sdio_obj.dma.handle_rx);
|
||||
HAL_DMA_Init(&sdio_obj.dma.handle_rx);
|
||||
|
||||
HAL_DMA_Start(&sdio_obj.dma.handle_rx, (uint32_t)src, (uint32_t)dst, BufferSize);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function get stm32 sdio clock.
|
||||
* @param hw_sdio: stm32_sdio
|
||||
* @retval PCLK2Freq
|
||||
*/
|
||||
static rt_uint32_t stm32_sdio_clock_get(struct stm32_sdio *hw_sdio)
|
||||
{
|
||||
return HAL_RCC_GetPCLK2Freq();
|
||||
}
|
||||
|
||||
static rt_err_t DMA_TxConfig(rt_uint32_t *src, rt_uint32_t *dst, int Size)
|
||||
{
|
||||
SD_LowLevel_DMA_TxConfig((uint32_t *)src, (uint32_t *)dst, Size / 4);
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t DMA_RxConfig(rt_uint32_t *src, rt_uint32_t *dst, int Size)
|
||||
{
|
||||
SD_LowLevel_DMA_RxConfig((uint32_t *)src, (uint32_t *)dst, Size / 4);
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
void SDIO_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
/* Process All SDIO Interrupt Sources */
|
||||
rthw_sdio_irq_process(host);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
int rt_hw_sdio_init(void)
|
||||
{
|
||||
struct stm32_sdio_des sdio_des;
|
||||
SD_HandleTypeDef hsd;
|
||||
hsd.Instance = SDCARD_INSTANCE;
|
||||
{
|
||||
rt_uint32_t tmpreg = 0x00U;
|
||||
#if defined(SOC_SERIES_STM32F1)
|
||||
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
|
||||
SET_BIT(RCC->AHBENR, sdio_config.dma_rx.dma_rcc);
|
||||
tmpreg = READ_BIT(RCC->AHBENR, sdio_config.dma_rx.dma_rcc);
|
||||
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
|
||||
SET_BIT(RCC->AHB1ENR, sdio_config.dma_rx.dma_rcc);
|
||||
/* Delay after an RCC peripheral clock enabling */
|
||||
tmpreg = READ_BIT(RCC->AHB1ENR, sdio_config.dma_rx.dma_rcc);
|
||||
#endif
|
||||
UNUSED(tmpreg); /* To avoid compiler warnings */
|
||||
}
|
||||
HAL_NVIC_SetPriority(SDIO_IRQn, 2, 0);
|
||||
HAL_NVIC_EnableIRQ(SDIO_IRQn);
|
||||
HAL_SD_MspInit(&hsd);
|
||||
|
||||
sdio_des.clk_get = stm32_sdio_clock_get;
|
||||
sdio_des.hw_sdio = (struct stm32_sdio *)SDCARD_INSTANCE;
|
||||
sdio_des.rxconfig = DMA_RxConfig;
|
||||
sdio_des.txconfig = DMA_TxConfig;
|
||||
|
||||
host = sdio_host_create(&sdio_des);
|
||||
if (host == RT_NULL)
|
||||
{
|
||||
LOG_E("host create fail");
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
INIT_DEVICE_EXPORT(rt_hw_sdio_init);
|
||||
|
||||
void stm32_mmcsd_change(void)
|
||||
{
|
||||
mmcsd_change(host);
|
||||
}
|
||||
|
||||
#endif
|
||||
222
drivers/drv_soft_i2c.c
Normal file
222
drivers/drv_soft_i2c.c
Normal file
@ -0,0 +1,222 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-08 balanceTWK first version
|
||||
*/
|
||||
|
||||
#include <board.h>
|
||||
#include "drv_soft_i2c.h"
|
||||
#include "drv_config.h"
|
||||
#include<rtthread.h>
|
||||
#include<rtdevice.h>
|
||||
|
||||
#ifdef RT_USING_I2C
|
||||
|
||||
//#define DRV_DEBUG
|
||||
#define LOG_TAG "drv.i2c"
|
||||
#include <drv_log.h>
|
||||
|
||||
#if !defined(BSP_USING_I2C1) && !defined(BSP_USING_I2C2) && !defined(BSP_USING_I2C3) && !defined(BSP_USING_I2C4)
|
||||
#error "Please define at least one BSP_USING_I2Cx"
|
||||
#endif
|
||||
|
||||
static const struct stm32_soft_i2c_config soft_i2c_config[] =
|
||||
{
|
||||
#ifdef BSP_USING_I2C1
|
||||
I2C1_BUS_CONFIG,
|
||||
#endif
|
||||
#ifdef BSP_USING_I2C2
|
||||
I2C2_BUS_CONFIG,
|
||||
#endif
|
||||
#ifdef BSP_USING_I2C3
|
||||
I2C3_BUS_CONFIG,
|
||||
#endif
|
||||
#ifdef BSP_USING_I2C4
|
||||
I2C4_BUS_CONFIG,
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct stm32_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0])];
|
||||
|
||||
/**
|
||||
* This function initializes the i2c pin.
|
||||
*
|
||||
* @param Stm32 i2c dirver class.
|
||||
*/
|
||||
static void stm32_i2c_gpio_init(struct stm32_i2c *i2c)
|
||||
{
|
||||
struct stm32_soft_i2c_config* cfg = (struct stm32_soft_i2c_config*)i2c->ops.data;
|
||||
|
||||
rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD);
|
||||
rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD);
|
||||
|
||||
rt_pin_write(cfg->scl, PIN_HIGH);
|
||||
rt_pin_write(cfg->sda, PIN_HIGH);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function sets the sda pin.
|
||||
*
|
||||
* @param Stm32 config class.
|
||||
* @param The sda pin state.
|
||||
*/
|
||||
static void stm32_set_sda(void *data, rt_int32_t state)
|
||||
{
|
||||
struct stm32_soft_i2c_config* cfg = (struct stm32_soft_i2c_config*)data;
|
||||
if (state)
|
||||
{
|
||||
rt_pin_write(cfg->sda, PIN_HIGH);
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_pin_write(cfg->sda, PIN_LOW);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* This function sets the scl pin.
|
||||
*
|
||||
* @param Stm32 config class.
|
||||
* @param The scl pin state.
|
||||
*/
|
||||
static void stm32_set_scl(void *data, rt_int32_t state)
|
||||
{
|
||||
struct stm32_soft_i2c_config* cfg = (struct stm32_soft_i2c_config*)data;
|
||||
if (state)
|
||||
{
|
||||
rt_pin_write(cfg->scl, PIN_HIGH);
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_pin_write(cfg->scl, PIN_LOW);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* This function gets the sda pin state.
|
||||
*
|
||||
* @param The sda pin state.
|
||||
*/
|
||||
static rt_int32_t stm32_get_sda(void *data)
|
||||
{
|
||||
struct stm32_soft_i2c_config* cfg = (struct stm32_soft_i2c_config*)data;
|
||||
return rt_pin_read(cfg->sda);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function gets the scl pin state.
|
||||
*
|
||||
* @param The scl pin state.
|
||||
*/
|
||||
static rt_int32_t stm32_get_scl(void *data)
|
||||
{
|
||||
struct stm32_soft_i2c_config* cfg = (struct stm32_soft_i2c_config*)data;
|
||||
return rt_pin_read(cfg->scl);
|
||||
}
|
||||
/**
|
||||
* The time delay function.
|
||||
*
|
||||
* @param microseconds.
|
||||
*/
|
||||
static void stm32_udelay(rt_uint32_t us)
|
||||
{
|
||||
rt_uint32_t ticks;
|
||||
rt_uint32_t told, tnow, tcnt = 0;
|
||||
rt_uint32_t reload = SysTick->LOAD;
|
||||
|
||||
ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
|
||||
told = SysTick->VAL;
|
||||
while (1)
|
||||
{
|
||||
tnow = SysTick->VAL;
|
||||
if (tnow != told)
|
||||
{
|
||||
if (tnow < told)
|
||||
{
|
||||
tcnt += told - tnow;
|
||||
}
|
||||
else
|
||||
{
|
||||
tcnt += reload - tnow + told;
|
||||
}
|
||||
told = tnow;
|
||||
if (tcnt >= ticks)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static const struct rt_i2c_bit_ops stm32_bit_ops_default =
|
||||
{
|
||||
.data = RT_NULL,
|
||||
.set_sda = stm32_set_sda,
|
||||
.set_scl = stm32_set_scl,
|
||||
.get_sda = stm32_get_sda,
|
||||
.get_scl = stm32_get_scl,
|
||||
.udelay = stm32_udelay,
|
||||
.delay_us = 1,
|
||||
.timeout = 100
|
||||
};
|
||||
|
||||
/**
|
||||
* if i2c is locked, this function will unlock it
|
||||
*
|
||||
* @param stm32 config class
|
||||
*
|
||||
* @return RT_EOK indicates successful unlock.
|
||||
*/
|
||||
static rt_err_t stm32_i2c_bus_unlock(const struct stm32_soft_i2c_config *cfg)
|
||||
{
|
||||
rt_int32_t i = 0;
|
||||
|
||||
if (PIN_LOW == rt_pin_read(cfg->sda))
|
||||
{
|
||||
while (i++ < 9)
|
||||
{
|
||||
rt_pin_write(cfg->scl, PIN_HIGH);
|
||||
stm32_udelay(100);
|
||||
rt_pin_write(cfg->scl, PIN_LOW);
|
||||
stm32_udelay(100);
|
||||
}
|
||||
}
|
||||
if (PIN_LOW == rt_pin_read(cfg->sda))
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
/* I2C initialization function */
|
||||
int rt_hw_i2c_init(void)
|
||||
{
|
||||
rt_size_t obj_num = sizeof(i2c_obj) / sizeof(struct stm32_i2c);
|
||||
rt_err_t result;
|
||||
|
||||
for (int i = 0; i < obj_num; i++)
|
||||
{
|
||||
i2c_obj[i].ops = stm32_bit_ops_default;
|
||||
i2c_obj[i].ops.data = (void*)&soft_i2c_config[i];
|
||||
i2c_obj[i].i2c2_bus.priv = &i2c_obj[i].ops;
|
||||
stm32_i2c_gpio_init(&i2c_obj[i]);
|
||||
result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c2_bus, soft_i2c_config[i].bus_name);
|
||||
RT_ASSERT(result == RT_EOK);
|
||||
stm32_i2c_bus_unlock(&soft_i2c_config[i]);
|
||||
|
||||
LOG_D("software simulation %s init done, pin scl: %d, pin sda %d",
|
||||
soft_i2c_config[i].bus_name,
|
||||
soft_i2c_config[i].scl,
|
||||
soft_i2c_config[i].sda);
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_BOARD_EXPORT(rt_hw_i2c_init);
|
||||
|
||||
#endif /* RT_USING_I2C */
|
||||
923
drivers/drv_spi.c
Normal file
923
drivers/drv_spi.c
Normal file
@ -0,0 +1,923 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-5 SummerGift first version
|
||||
* 2018-12-11 greedyhao Porting for stm32f7xx
|
||||
* 2019-01-03 zylx modify DMA initialization and spixfer function
|
||||
* 2020-01-15 whj4674672 Porting for stm32h7xx
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
#include<rtthread.h>
|
||||
#include<rtdevice.h>
|
||||
|
||||
#ifdef RT_USING_SPI
|
||||
|
||||
#if defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) || defined(BSP_USING_SPI4) || defined(BSP_USING_SPI5) || defined(BSP_USING_SPI6)
|
||||
|
||||
#include "drv_spi.h"
|
||||
#include "drv_config.h"
|
||||
#include <string.h>
|
||||
|
||||
//#define DRV_DEBUG
|
||||
#define LOG_TAG "drv.spi"
|
||||
#include <drv_log.h>
|
||||
|
||||
enum
|
||||
{
|
||||
#ifdef BSP_USING_SPI1
|
||||
SPI1_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_SPI2
|
||||
SPI2_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_SPI3
|
||||
SPI3_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_SPI4
|
||||
SPI4_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_SPI5
|
||||
SPI5_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_SPI6
|
||||
SPI6_INDEX,
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct stm32_spi_config spi_config[] =
|
||||
{
|
||||
#ifdef BSP_USING_SPI1
|
||||
SPI1_BUS_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_SPI2
|
||||
SPI2_BUS_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_SPI3
|
||||
SPI3_BUS_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_SPI4
|
||||
SPI4_BUS_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_SPI5
|
||||
SPI5_BUS_CONFIG,
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_SPI6
|
||||
SPI6_BUS_CONFIG,
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct stm32_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])] = {0};
|
||||
|
||||
static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configuration *cfg)
|
||||
{
|
||||
RT_ASSERT(spi_drv != RT_NULL);
|
||||
RT_ASSERT(cfg != RT_NULL);
|
||||
|
||||
SPI_HandleTypeDef *spi_handle = &spi_drv->handle;
|
||||
|
||||
if (cfg->mode & RT_SPI_SLAVE)
|
||||
{
|
||||
spi_handle->Init.Mode = SPI_MODE_SLAVE;
|
||||
}
|
||||
else
|
||||
{
|
||||
spi_handle->Init.Mode = SPI_MODE_MASTER;
|
||||
}
|
||||
|
||||
if (cfg->mode & RT_SPI_3WIRE)
|
||||
{
|
||||
spi_handle->Init.Direction = SPI_DIRECTION_1LINE;
|
||||
}
|
||||
else
|
||||
{
|
||||
spi_handle->Init.Direction = SPI_DIRECTION_2LINES;
|
||||
}
|
||||
|
||||
if (cfg->data_width == 8)
|
||||
{
|
||||
spi_handle->Init.DataSize = SPI_DATASIZE_8BIT;
|
||||
spi_handle->TxXferSize = 8;
|
||||
spi_handle->RxXferSize = 8;
|
||||
}
|
||||
else if (cfg->data_width == 16)
|
||||
{
|
||||
spi_handle->Init.DataSize = SPI_DATASIZE_16BIT;
|
||||
}
|
||||
else
|
||||
{
|
||||
return RT_EIO;
|
||||
}
|
||||
|
||||
if (cfg->mode & RT_SPI_CPHA)
|
||||
{
|
||||
spi_handle->Init.CLKPhase = SPI_PHASE_2EDGE;
|
||||
}
|
||||
else
|
||||
{
|
||||
spi_handle->Init.CLKPhase = SPI_PHASE_1EDGE;
|
||||
}
|
||||
|
||||
if (cfg->mode & RT_SPI_CPOL)
|
||||
{
|
||||
spi_handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
|
||||
}
|
||||
else
|
||||
{
|
||||
spi_handle->Init.CLKPolarity = SPI_POLARITY_LOW;
|
||||
}
|
||||
|
||||
if (cfg->mode & RT_SPI_NO_CS)
|
||||
{
|
||||
spi_handle->Init.NSS = SPI_NSS_SOFT;
|
||||
}
|
||||
else
|
||||
{
|
||||
spi_handle->Init.NSS = SPI_NSS_SOFT;
|
||||
}
|
||||
|
||||
uint32_t SPI_APB_CLOCK;
|
||||
|
||||
#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
|
||||
SPI_APB_CLOCK = HAL_RCC_GetPCLK1Freq();
|
||||
#elif defined(SOC_SERIES_STM32H7)
|
||||
SPI_APB_CLOCK = HAL_RCC_GetSysClockFreq();
|
||||
#else
|
||||
SPI_APB_CLOCK = HAL_RCC_GetPCLK2Freq();
|
||||
#endif
|
||||
|
||||
if (cfg->max_hz >= SPI_APB_CLOCK / 2)
|
||||
{
|
||||
spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
|
||||
}
|
||||
else if (cfg->max_hz >= SPI_APB_CLOCK / 4)
|
||||
{
|
||||
spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4;
|
||||
}
|
||||
else if (cfg->max_hz >= SPI_APB_CLOCK / 8)
|
||||
{
|
||||
spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8;
|
||||
}
|
||||
else if (cfg->max_hz >= SPI_APB_CLOCK / 16)
|
||||
{
|
||||
spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;
|
||||
}
|
||||
else if (cfg->max_hz >= SPI_APB_CLOCK / 32)
|
||||
{
|
||||
spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32;
|
||||
}
|
||||
else if (cfg->max_hz >= SPI_APB_CLOCK / 64)
|
||||
{
|
||||
spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_64;
|
||||
}
|
||||
else if (cfg->max_hz >= SPI_APB_CLOCK / 128)
|
||||
{
|
||||
spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_128;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* min prescaler 256 */
|
||||
spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;
|
||||
}
|
||||
|
||||
LOG_D("sys freq: %d, pclk2 freq: %d, SPI limiting freq: %d, BaudRatePrescaler: %d",
|
||||
HAL_RCC_GetSysClockFreq(),
|
||||
SPI_APB_CLOCK,
|
||||
cfg->max_hz,
|
||||
spi_handle->Init.BaudRatePrescaler);
|
||||
|
||||
if (cfg->mode & RT_SPI_MSB)
|
||||
{
|
||||
spi_handle->Init.FirstBit = SPI_FIRSTBIT_MSB;
|
||||
}
|
||||
else
|
||||
{
|
||||
spi_handle->Init.FirstBit = SPI_FIRSTBIT_LSB;
|
||||
}
|
||||
|
||||
spi_handle->Init.TIMode = SPI_TIMODE_DISABLE;
|
||||
spi_handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
||||
spi_handle->State = HAL_SPI_STATE_RESET;
|
||||
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0)
|
||||
spi_handle->Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
|
||||
#elif defined(SOC_SERIES_STM32H7)
|
||||
spi_handle->Init.Mode = SPI_MODE_MASTER;
|
||||
spi_handle->Init.NSS = SPI_NSS_SOFT;
|
||||
spi_handle->Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
|
||||
spi_handle->Init.NSSPolarity = SPI_NSS_POLARITY_LOW;
|
||||
spi_handle->Init.CRCPolynomial = 7;
|
||||
spi_handle->Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
|
||||
spi_handle->Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
|
||||
spi_handle->Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE;
|
||||
spi_handle->Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE;
|
||||
spi_handle->Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE;
|
||||
spi_handle->Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_ENABLE;
|
||||
spi_handle->Init.IOSwap = SPI_IO_SWAP_DISABLE;
|
||||
spi_handle->Init.FifoThreshold = SPI_FIFO_THRESHOLD_08DATA;
|
||||
#endif
|
||||
|
||||
if (HAL_SPI_Init(spi_handle) != HAL_OK)
|
||||
{
|
||||
return RT_EIO;
|
||||
}
|
||||
|
||||
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) \
|
||||
|| defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32G0)
|
||||
SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF);
|
||||
#endif
|
||||
|
||||
/* DMA configuration */
|
||||
if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG)
|
||||
{
|
||||
HAL_DMA_Init(&spi_drv->dma.handle_rx);
|
||||
|
||||
__HAL_LINKDMA(&spi_drv->handle, hdmarx, spi_drv->dma.handle_rx);
|
||||
|
||||
/* NVIC configuration for DMA transfer complete interrupt */
|
||||
HAL_NVIC_SetPriority(spi_drv->config->dma_rx->dma_irq, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(spi_drv->config->dma_rx->dma_irq);
|
||||
}
|
||||
|
||||
if (spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG)
|
||||
{
|
||||
HAL_DMA_Init(&spi_drv->dma.handle_tx);
|
||||
|
||||
__HAL_LINKDMA(&spi_drv->handle, hdmatx, spi_drv->dma.handle_tx);
|
||||
|
||||
/* NVIC configuration for DMA transfer complete interrupt */
|
||||
HAL_NVIC_SetPriority(spi_drv->config->dma_tx->dma_irq, 0, 1);
|
||||
HAL_NVIC_EnableIRQ(spi_drv->config->dma_tx->dma_irq);
|
||||
}
|
||||
|
||||
__HAL_SPI_ENABLE(spi_handle);
|
||||
|
||||
LOG_D("%s init done", spi_drv->config->bus_name);
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
|
||||
{
|
||||
HAL_StatusTypeDef state;
|
||||
rt_size_t message_length, already_send_length;
|
||||
rt_uint16_t send_length;
|
||||
rt_uint8_t *recv_buf;
|
||||
const rt_uint8_t *send_buf;
|
||||
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
RT_ASSERT(device->bus != RT_NULL);
|
||||
RT_ASSERT(device->bus->parent.user_data != RT_NULL);
|
||||
RT_ASSERT(message != RT_NULL);
|
||||
|
||||
struct stm32_spi *spi_drv = rt_container_of(device->bus, struct stm32_spi, spi_bus);
|
||||
SPI_HandleTypeDef *spi_handle = &spi_drv->handle;
|
||||
struct stm32_hw_spi_cs *cs = device->parent.user_data;
|
||||
|
||||
if (message->cs_take)
|
||||
{
|
||||
HAL_GPIO_WritePin(cs->GPIOx, cs->GPIO_Pin, GPIO_PIN_RESET);
|
||||
}
|
||||
|
||||
LOG_D("%s transfer prepare and start", spi_drv->config->bus_name);
|
||||
LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d",
|
||||
spi_drv->config->bus_name,
|
||||
(uint32_t)message->send_buf,
|
||||
(uint32_t)message->recv_buf, message->length);
|
||||
|
||||
message_length = message->length;
|
||||
recv_buf = message->recv_buf;
|
||||
send_buf = message->send_buf;
|
||||
while (message_length)
|
||||
{
|
||||
/* the HAL library use uint16 to save the data length */
|
||||
if (message_length > 65535)
|
||||
{
|
||||
send_length = 65535;
|
||||
message_length = message_length - 65535;
|
||||
}
|
||||
else
|
||||
{
|
||||
send_length = message_length;
|
||||
message_length = 0;
|
||||
}
|
||||
|
||||
/* calculate the start address */
|
||||
already_send_length = message->length - send_length - message_length;
|
||||
send_buf = (rt_uint8_t *)message->send_buf + already_send_length;
|
||||
recv_buf = (rt_uint8_t *)message->recv_buf + already_send_length;
|
||||
|
||||
/* start once data exchange in DMA mode */
|
||||
if (message->send_buf && message->recv_buf)
|
||||
{
|
||||
if ((spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG) && (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG))
|
||||
{
|
||||
state = HAL_SPI_TransmitReceive_DMA(spi_handle, (uint8_t *)send_buf, (uint8_t *)recv_buf, send_length);
|
||||
}
|
||||
else
|
||||
{
|
||||
state = HAL_SPI_TransmitReceive(spi_handle, (uint8_t *)send_buf, (uint8_t *)recv_buf, send_length, 1000);
|
||||
//rt_kprintf("spi HAL_SPI_TransmitReceive error : %d\n", state);
|
||||
}
|
||||
}
|
||||
else if (message->send_buf)
|
||||
{
|
||||
if (spi_drv->spi_dma_flag & SPI_USING_TX_DMA_FLAG)
|
||||
{
|
||||
state = HAL_SPI_Transmit_DMA(spi_handle, (uint8_t *)send_buf, send_length);
|
||||
}
|
||||
else
|
||||
{
|
||||
state = HAL_SPI_Transmit(spi_handle, (uint8_t *)send_buf, send_length, 1000);
|
||||
//rt_kprintf("spi HAL_SPI_Transmit error : %d\n", state);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
memset((uint8_t *)recv_buf, 0xff, send_length);
|
||||
if (spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG)
|
||||
{
|
||||
state = HAL_SPI_Receive_DMA(spi_handle, (uint8_t *)recv_buf, send_length);
|
||||
}
|
||||
else
|
||||
{
|
||||
state = HAL_SPI_Receive(spi_handle, (uint8_t *)recv_buf, send_length, 1000);
|
||||
//rt_kprintf("spi HAL_SPI_Receive error : %d\n", state);
|
||||
// rt_kprintf("Received Data: ");
|
||||
// for (rt_uint8_t i = 0; i < send_length; i++)
|
||||
// {
|
||||
// rt_kprintf("%02X ", recv_buf[i]);
|
||||
// }
|
||||
// rt_kprintf("\n");
|
||||
}
|
||||
}
|
||||
|
||||
if (state != HAL_OK)
|
||||
{
|
||||
LOG_I("spi transfer error : %d", state);
|
||||
message->length = 0;
|
||||
spi_handle->State = HAL_SPI_STATE_READY;
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_D("%s transfer done", spi_drv->config->bus_name);
|
||||
}
|
||||
|
||||
/* For simplicity reasons, this example is just waiting till the end of the
|
||||
transfer, but application may perform other tasks while transfer operation
|
||||
is ongoing. */
|
||||
while (HAL_SPI_GetState(spi_handle) != HAL_SPI_STATE_READY);
|
||||
}
|
||||
|
||||
if (message->cs_release)
|
||||
{
|
||||
HAL_GPIO_WritePin(cs->GPIOx, cs->GPIO_Pin, GPIO_PIN_SET);
|
||||
}
|
||||
|
||||
return message->length;
|
||||
}
|
||||
|
||||
static rt_err_t spi_configure(struct rt_spi_device *device,
|
||||
struct rt_spi_configuration *configuration)
|
||||
{
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
RT_ASSERT(configuration != RT_NULL);
|
||||
|
||||
struct stm32_spi *spi_drv = rt_container_of(device->bus, struct stm32_spi, spi_bus);
|
||||
spi_drv->cfg = configuration;
|
||||
|
||||
return stm32_spi_init(spi_drv, configuration);
|
||||
}
|
||||
|
||||
static const struct rt_spi_ops stm_spi_ops =
|
||||
{
|
||||
.configure = spi_configure,
|
||||
.xfer = spixfer,
|
||||
};
|
||||
|
||||
static int rt_hw_spi_bus_init(void)
|
||||
{
|
||||
rt_err_t result;
|
||||
for (int i = 0; i < sizeof(spi_config) / sizeof(spi_config[0]); i++)
|
||||
{
|
||||
spi_bus_obj[i].config = &spi_config[i];
|
||||
spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i];
|
||||
spi_bus_obj[i].handle.Instance = spi_config[i].Instance;
|
||||
|
||||
if (spi_bus_obj[i].spi_dma_flag & SPI_USING_RX_DMA_FLAG)
|
||||
{
|
||||
/* Configure the DMA handler for Transmission process */
|
||||
spi_bus_obj[i].dma.handle_rx.Instance = spi_config[i].dma_rx->Instance;
|
||||
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||||
spi_bus_obj[i].dma.handle_rx.Init.Channel = spi_config[i].dma_rx->channel;
|
||||
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
|
||||
spi_bus_obj[i].dma.handle_rx.Init.Request = spi_config[i].dma_rx->request;
|
||||
#endif
|
||||
spi_bus_obj[i].dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
||||
spi_bus_obj[i].dma.handle_rx.Init.PeriphInc = DMA_PINC_DISABLE;
|
||||
spi_bus_obj[i].dma.handle_rx.Init.MemInc = DMA_MINC_ENABLE;
|
||||
spi_bus_obj[i].dma.handle_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
||||
spi_bus_obj[i].dma.handle_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
||||
spi_bus_obj[i].dma.handle_rx.Init.Mode = DMA_NORMAL;
|
||||
spi_bus_obj[i].dma.handle_rx.Init.Priority = DMA_PRIORITY_HIGH;
|
||||
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||||
spi_bus_obj[i].dma.handle_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
||||
spi_bus_obj[i].dma.handle_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
|
||||
spi_bus_obj[i].dma.handle_rx.Init.MemBurst = DMA_MBURST_INC4;
|
||||
spi_bus_obj[i].dma.handle_rx.Init.PeriphBurst = DMA_PBURST_INC4;
|
||||
#endif
|
||||
|
||||
{
|
||||
rt_uint32_t tmpreg = 0x00U;
|
||||
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0)
|
||||
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
|
||||
SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
|
||||
tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
|
||||
#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
|
||||
SET_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc);
|
||||
/* Delay after an RCC peripheral clock enabling */
|
||||
tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc);
|
||||
#endif
|
||||
UNUSED(tmpreg); /* To avoid compiler warnings */
|
||||
}
|
||||
}
|
||||
|
||||
if (spi_bus_obj[i].spi_dma_flag & SPI_USING_TX_DMA_FLAG)
|
||||
{
|
||||
/* Configure the DMA handler for Transmission process */
|
||||
spi_bus_obj[i].dma.handle_tx.Instance = spi_config[i].dma_tx->Instance;
|
||||
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||||
spi_bus_obj[i].dma.handle_tx.Init.Channel = spi_config[i].dma_tx->channel;
|
||||
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
|
||||
spi_bus_obj[i].dma.handle_tx.Init.Request = spi_config[i].dma_tx->request;
|
||||
#endif
|
||||
spi_bus_obj[i].dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
|
||||
spi_bus_obj[i].dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE;
|
||||
spi_bus_obj[i].dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE;
|
||||
spi_bus_obj[i].dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
||||
spi_bus_obj[i].dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
||||
spi_bus_obj[i].dma.handle_tx.Init.Mode = DMA_NORMAL;
|
||||
spi_bus_obj[i].dma.handle_tx.Init.Priority = DMA_PRIORITY_LOW;
|
||||
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||||
spi_bus_obj[i].dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
||||
spi_bus_obj[i].dma.handle_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
|
||||
spi_bus_obj[i].dma.handle_tx.Init.MemBurst = DMA_MBURST_INC4;
|
||||
spi_bus_obj[i].dma.handle_tx.Init.PeriphBurst = DMA_PBURST_INC4;
|
||||
#endif
|
||||
|
||||
{
|
||||
rt_uint32_t tmpreg = 0x00U;
|
||||
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0)
|
||||
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
|
||||
SET_BIT(RCC->AHBENR, spi_config[i].dma_tx->dma_rcc);
|
||||
tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_tx->dma_rcc);
|
||||
#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
|
||||
SET_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc);
|
||||
/* Delay after an RCC peripheral clock enabling */
|
||||
tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc);
|
||||
#endif
|
||||
UNUSED(tmpreg); /* To avoid compiler warnings */
|
||||
}
|
||||
}
|
||||
|
||||
result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].bus_name, &stm_spi_ops);
|
||||
RT_ASSERT(result == RT_EOK);
|
||||
|
||||
LOG_D("%s bus init done", spi_config[i].bus_name);
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
/**
|
||||
* Attach the spi device to SPI bus, this function must be used after initialization.
|
||||
*/
|
||||
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef *cs_gpiox, uint16_t cs_gpio_pin)
|
||||
{
|
||||
RT_ASSERT(bus_name != RT_NULL);
|
||||
RT_ASSERT(device_name != RT_NULL);
|
||||
|
||||
rt_err_t result;
|
||||
struct rt_spi_device *spi_device;
|
||||
struct stm32_hw_spi_cs *cs_pin;
|
||||
|
||||
/* initialize the cs pin && select the slave*/
|
||||
GPIO_InitTypeDef GPIO_Initure;
|
||||
GPIO_Initure.Pin = cs_gpio_pin;
|
||||
GPIO_Initure.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
GPIO_Initure.Pull = GPIO_PULLUP;
|
||||
GPIO_Initure.Speed = GPIO_SPEED_FREQ_HIGH;
|
||||
HAL_GPIO_Init(cs_gpiox, &GPIO_Initure);
|
||||
HAL_GPIO_WritePin(cs_gpiox, cs_gpio_pin, GPIO_PIN_SET);
|
||||
|
||||
/* attach the device to spi bus*/
|
||||
spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
|
||||
RT_ASSERT(spi_device != RT_NULL);
|
||||
cs_pin = (struct stm32_hw_spi_cs *)rt_malloc(sizeof(struct stm32_hw_spi_cs));
|
||||
RT_ASSERT(cs_pin != RT_NULL);
|
||||
cs_pin->GPIOx = cs_gpiox;
|
||||
cs_pin->GPIO_Pin = cs_gpio_pin;
|
||||
result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
|
||||
|
||||
if (result != RT_EOK)
|
||||
{
|
||||
LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result);
|
||||
}
|
||||
|
||||
RT_ASSERT(result == RT_EOK);
|
||||
|
||||
LOG_D("%s attach to %s done", device_name, bus_name);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
#if defined(BSP_SPI1_TX_USING_DMA) || defined(BSP_SPI1_RX_USING_DMA)
|
||||
void SPI1_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
HAL_SPI_IRQHandler(&spi_bus_obj[SPI1_INDEX].handle);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_SPI1) && defined(BSP_SPI1_RX_USING_DMA)
|
||||
/**
|
||||
* @brief This function handles DMA Rx interrupt request.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SPI1_DMA_RX_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
HAL_DMA_IRQHandler(&spi_bus_obj[SPI1_INDEX].dma.handle_rx);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_SPI1) && defined(BSP_SPI1_TX_USING_DMA)
|
||||
/**
|
||||
* @brief This function handles DMA Tx interrupt request.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SPI1_DMA_TX_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
HAL_DMA_IRQHandler(&spi_bus_obj[SPI1_INDEX].dma.handle_tx);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* defined(BSP_USING_SPI1) && defined(BSP_SPI_USING_DMA) */
|
||||
|
||||
#if defined(BSP_SPI2_TX_USING_DMA) || defined(BSP_SPI2_RX_USING_DMA)
|
||||
void SPI2_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
HAL_SPI_IRQHandler(&spi_bus_obj[SPI2_INDEX].handle);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_SPI2) && defined(BSP_SPI2_RX_USING_DMA)
|
||||
/**
|
||||
* @brief This function handles DMA Rx interrupt request.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SPI2_DMA_RX_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
HAL_DMA_IRQHandler(&spi_bus_obj[SPI2_INDEX].dma.handle_rx);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_SPI2) && defined(BSP_SPI2_TX_USING_DMA)
|
||||
/**
|
||||
* @brief This function handles DMA Tx interrupt request.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SPI2_DMA_TX_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
HAL_DMA_IRQHandler(&spi_bus_obj[SPI2_INDEX].dma.handle_tx);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* defined(BSP_USING_SPI2) && defined(BSP_SPI_USING_DMA) */
|
||||
|
||||
#if defined(BSP_SPI3_TX_USING_DMA) || defined(BSP_SPI3_RX_USING_DMA)
|
||||
void SPI3_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
HAL_SPI_IRQHandler(&spi_bus_obj[SPI3_INDEX].handle);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_SPI3) && defined(BSP_SPI3_RX_USING_DMA)
|
||||
/**
|
||||
* @brief This function handles DMA Rx interrupt request.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SPI3_DMA_RX_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
HAL_DMA_IRQHandler(&spi_bus_obj[SPI3_INDEX].dma.handle_rx);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_SPI3) && defined(BSP_SPI3_TX_USING_DMA)
|
||||
/**
|
||||
* @brief This function handles DMA Tx interrupt request.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SPI3_DMA_TX_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
HAL_DMA_IRQHandler(&spi_bus_obj[SPI3_INDEX].dma.handle_tx);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* defined(BSP_USING_SPI3) && defined(BSP_SPI_USING_DMA) */
|
||||
|
||||
#if defined(BSP_SPI4_TX_USING_DMA) || defined(BSP_SPI4_RX_USING_DMA)
|
||||
void SPI4_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
HAL_SPI_IRQHandler(&spi_bus_obj[SPI4_INDEX].handle);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_SPI4) && defined(BSP_SPI4_RX_USING_DMA)
|
||||
/**
|
||||
* @brief This function handles DMA Rx interrupt request.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SPI4_DMA_RX_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
HAL_DMA_IRQHandler(&spi_bus_obj[SPI4_INDEX].dma.handle_rx);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_SPI4) && defined(BSP_SPI4_TX_USING_DMA)
|
||||
/**
|
||||
* @brief This function handles DMA Tx interrupt request.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SPI4_DMA_TX_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
HAL_DMA_IRQHandler(&spi_bus_obj[SPI4_INDEX].dma.handle_tx);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* defined(BSP_USING_SPI4) && defined(BSP_SPI_USING_DMA) */
|
||||
|
||||
#if defined(BSP_SPI5_TX_USING_DMA) || defined(BSP_SPI5_RX_USING_DMA)
|
||||
void SPI5_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
HAL_SPI_IRQHandler(&spi_bus_obj[SPI5_INDEX].handle);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_SPI5) && defined(BSP_SPI5_RX_USING_DMA)
|
||||
/**
|
||||
* @brief This function handles DMA Rx interrupt request.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SPI5_DMA_RX_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
HAL_DMA_IRQHandler(&spi_bus_obj[SPI5_INDEX].dma.handle_rx);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_SPI5) && defined(BSP_SPI5_TX_USING_DMA)
|
||||
/**
|
||||
* @brief This function handles DMA Tx interrupt request.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SPI5_DMA_TX_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
HAL_DMA_IRQHandler(&spi_bus_obj[SPI5_INDEX].dma.handle_tx);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* defined(BSP_USING_SPI5) && defined(BSP_SPI_USING_DMA) */
|
||||
|
||||
#if defined(BSP_USING_SPI6) && defined(BSP_SPI6_RX_USING_DMA)
|
||||
/**
|
||||
* @brief This function handles DMA Rx interrupt request.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SPI6_DMA_RX_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
HAL_DMA_IRQHandler(&spi_bus_obj[SPI6_INDEX].dma.handle_rx);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_SPI6) && defined(BSP_SPI6_TX_USING_DMA)
|
||||
/**
|
||||
* @brief This function handles DMA Tx interrupt request.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SPI6_DMA_TX_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
HAL_DMA_IRQHandler(&spi_bus_obj[SPI6_INDEX].dma.handle_tx);
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif /* defined(BSP_USING_SPI6) && defined(BSP_SPI_USING_DMA) */
|
||||
|
||||
static void stm32_get_dma_info(void)
|
||||
{
|
||||
#ifdef BSP_SPI1_RX_USING_DMA
|
||||
spi_bus_obj[SPI1_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
|
||||
static struct dma_config spi1_dma_rx = SPI1_RX_DMA_CONFIG;
|
||||
spi_config[SPI1_INDEX].dma_rx = &spi1_dma_rx;
|
||||
#endif
|
||||
#ifdef BSP_SPI1_TX_USING_DMA
|
||||
spi_bus_obj[SPI1_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
|
||||
static struct dma_config spi1_dma_tx = SPI1_TX_DMA_CONFIG;
|
||||
spi_config[SPI1_INDEX].dma_tx = &spi1_dma_tx;
|
||||
#endif
|
||||
|
||||
#ifdef BSP_SPI2_RX_USING_DMA
|
||||
spi_bus_obj[SPI2_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
|
||||
static struct dma_config spi2_dma_rx = SPI2_RX_DMA_CONFIG;
|
||||
spi_config[SPI2_INDEX].dma_rx = &spi2_dma_rx;
|
||||
#endif
|
||||
#ifdef BSP_SPI2_TX_USING_DMA
|
||||
spi_bus_obj[SPI2_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
|
||||
static struct dma_config spi2_dma_tx = SPI2_TX_DMA_CONFIG;
|
||||
spi_config[SPI2_INDEX].dma_tx = &spi2_dma_tx;
|
||||
#endif
|
||||
|
||||
#ifdef BSP_SPI3_RX_USING_DMA
|
||||
spi_bus_obj[SPI3_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
|
||||
static struct dma_config spi3_dma_rx = SPI3_RX_DMA_CONFIG;
|
||||
spi_config[SPI3_INDEX].dma_rx = &spi3_dma_rx;
|
||||
#endif
|
||||
#ifdef BSP_SPI3_TX_USING_DMA
|
||||
spi_bus_obj[SPI3_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
|
||||
static struct dma_config spi3_dma_tx = SPI3_TX_DMA_CONFIG;
|
||||
spi_config[SPI3_INDEX].dma_tx = &spi3_dma_tx;
|
||||
#endif
|
||||
|
||||
#ifdef BSP_SPI4_RX_USING_DMA
|
||||
spi_bus_obj[SPI4_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
|
||||
static struct dma_config spi4_dma_rx = SPI4_RX_DMA_CONFIG;
|
||||
spi_config[SPI4_INDEX].dma_rx = &spi4_dma_rx;
|
||||
#endif
|
||||
#ifdef BSP_SPI4_TX_USING_DMA
|
||||
spi_bus_obj[SPI4_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
|
||||
static struct dma_config spi4_dma_tx = SPI4_TX_DMA_CONFIG;
|
||||
spi_config[SPI4_INDEX].dma_tx = &spi4_dma_tx;
|
||||
#endif
|
||||
|
||||
#ifdef BSP_SPI5_RX_USING_DMA
|
||||
spi_bus_obj[SPI5_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
|
||||
static struct dma_config spi5_dma_rx = SPI5_RX_DMA_CONFIG;
|
||||
spi_config[SPI5_INDEX].dma_rx = &spi5_dma_rx;
|
||||
#endif
|
||||
#ifdef BSP_SPI5_TX_USING_DMA
|
||||
spi_bus_obj[SPI5_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
|
||||
static struct dma_config spi5_dma_tx = SPI5_TX_DMA_CONFIG;
|
||||
spi_config[SPI5_INDEX].dma_tx = &spi5_dma_tx;
|
||||
#endif
|
||||
|
||||
#ifdef BSP_SPI6_RX_USING_DMA
|
||||
spi_bus_obj[SPI6_INDEX].spi_dma_flag |= SPI_USING_RX_DMA_FLAG;
|
||||
static struct dma_config spi6_dma_rx = SPI6_RX_DMA_CONFIG;
|
||||
spi_config[SPI6_INDEX].dma_rx = &spi6_dma_rx;
|
||||
#endif
|
||||
#ifdef BSP_SPI6_TX_USING_DMA
|
||||
spi_bus_obj[SPI6_INDEX].spi_dma_flag |= SPI_USING_TX_DMA_FLAG;
|
||||
static struct dma_config spi6_dma_tx = SPI6_TX_DMA_CONFIG;
|
||||
spi_config[SPI6_INDEX].dma_tx = &spi6_dma_tx;
|
||||
#endif
|
||||
}
|
||||
|
||||
#if defined(SOC_SERIES_STM32F0)
|
||||
void SPI1_DMA_RX_TX_IRQHandler(void)
|
||||
{
|
||||
#if defined(BSP_USING_SPI1) && defined(BSP_SPI1_TX_USING_DMA)
|
||||
SPI1_DMA_TX_IRQHandler();
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_SPI1) && defined(BSP_SPI1_RX_USING_DMA)
|
||||
SPI1_DMA_RX_IRQHandler();
|
||||
#endif
|
||||
}
|
||||
|
||||
void SPI2_DMA_RX_TX_IRQHandler(void)
|
||||
{
|
||||
#if defined(BSP_USING_SPI2) && defined(BSP_SPI2_TX_USING_DMA)
|
||||
SPI2_DMA_TX_IRQHandler();
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_SPI2) && defined(BSP_SPI2_RX_USING_DMA)
|
||||
SPI2_DMA_RX_IRQHandler();
|
||||
#endif
|
||||
}
|
||||
#endif /* SOC_SERIES_STM32F0 */
|
||||
|
||||
int rt_hw_spi_init(void)
|
||||
{
|
||||
stm32_get_dma_info();
|
||||
return rt_hw_spi_bus_init();
|
||||
}
|
||||
INIT_BOARD_EXPORT(rt_hw_spi_init);
|
||||
|
||||
#endif /* BSP_USING_SPI1 || BSP_USING_SPI2 || BSP_USING_SPI3 || BSP_USING_SPI4 || BSP_USING_SPI5 */
|
||||
#endif /* RT_USING_SPI */
|
||||
1399
drivers/drv_usart.c
Normal file
1399
drivers/drv_usart.c
Normal file
File diff suppressed because it is too large
Load Diff
277
drivers/drv_usbd.c
Normal file
277
drivers/drv_usbd.c
Normal file
@ -0,0 +1,277 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-04-10 ZYH first version
|
||||
* 2019-10-27 flybreak Compatible with the HS
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "board.h"
|
||||
|
||||
#ifdef BSP_USING_USBDEVICE
|
||||
|
||||
#include <rtdevice.h>
|
||||
#include <string.h>
|
||||
#include <drv_config.h>
|
||||
|
||||
static PCD_HandleTypeDef _stm_pcd;
|
||||
static struct udcd _stm_udc;
|
||||
static struct ep_id _ep_pool[] =
|
||||
{
|
||||
{0x0, USB_EP_ATTR_CONTROL, USB_DIR_INOUT, 64, ID_ASSIGNED },
|
||||
{0x1, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED},
|
||||
{0x1, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED},
|
||||
{0x2, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED},
|
||||
{0x2, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED},
|
||||
{0x3, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED},
|
||||
#if !defined(SOC_SERIES_STM32F1)
|
||||
{0x3, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED},
|
||||
#endif
|
||||
{0xFF, USB_EP_ATTR_TYPE_MASK, USB_DIR_MASK, 0, ID_ASSIGNED },
|
||||
};
|
||||
|
||||
void USBD_IRQ_HANDLER(void)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
HAL_PCD_IRQHandler(&_stm_pcd);
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *pcd)
|
||||
{
|
||||
/* open ep0 OUT and IN */
|
||||
HAL_PCD_EP_Open(pcd, 0x00, 0x40, EP_TYPE_CTRL);
|
||||
HAL_PCD_EP_Open(pcd, 0x80, 0x40, EP_TYPE_CTRL);
|
||||
rt_usbd_reset_handler(&_stm_udc);
|
||||
}
|
||||
|
||||
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
rt_usbd_ep0_setup_handler(&_stm_udc, (struct urequest *)hpcd->Setup);
|
||||
}
|
||||
|
||||
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
||||
{
|
||||
if (epnum == 0)
|
||||
{
|
||||
rt_usbd_ep0_in_handler(&_stm_udc);
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_usbd_ep_in_handler(&_stm_udc, 0x80 | epnum, hpcd->IN_ep[epnum].xfer_count);
|
||||
}
|
||||
}
|
||||
|
||||
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
rt_usbd_connect_handler(&_stm_udc);
|
||||
}
|
||||
|
||||
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
rt_usbd_sof_handler(&_stm_udc);
|
||||
}
|
||||
|
||||
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
rt_usbd_disconnect_handler(&_stm_udc);
|
||||
}
|
||||
|
||||
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
|
||||
{
|
||||
if (epnum != 0)
|
||||
{
|
||||
rt_usbd_ep_out_handler(&_stm_udc, epnum, hpcd->OUT_ep[epnum].xfer_count);
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_usbd_ep0_out_handler(&_stm_udc, hpcd->OUT_ep[0].xfer_count);
|
||||
}
|
||||
}
|
||||
|
||||
void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
|
||||
{
|
||||
if (state == 1)
|
||||
{
|
||||
#if defined(SOC_SERIES_STM32F1)
|
||||
rt_pin_mode(BSP_USB_CONNECT_PIN,PIN_MODE_OUTPUT);
|
||||
rt_pin_write(BSP_USB_CONNECT_PIN, BSP_USB_PULL_UP_STATUS);
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
#if defined(SOC_SERIES_STM32F1)
|
||||
rt_pin_mode(BSP_USB_CONNECT_PIN,PIN_MODE_OUTPUT);
|
||||
rt_pin_write(BSP_USB_CONNECT_PIN, !BSP_USB_PULL_UP_STATUS);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
static rt_err_t _ep_set_stall(rt_uint8_t address)
|
||||
{
|
||||
HAL_PCD_EP_SetStall(&_stm_pcd, address);
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t _ep_clear_stall(rt_uint8_t address)
|
||||
{
|
||||
HAL_PCD_EP_ClrStall(&_stm_pcd, address);
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t _set_address(rt_uint8_t address)
|
||||
{
|
||||
HAL_PCD_SetAddress(&_stm_pcd, address);
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t _set_config(rt_uint8_t address)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t _ep_enable(uep_t ep)
|
||||
{
|
||||
RT_ASSERT(ep != RT_NULL);
|
||||
RT_ASSERT(ep->ep_desc != RT_NULL);
|
||||
HAL_PCD_EP_Open(&_stm_pcd, ep->ep_desc->bEndpointAddress,
|
||||
ep->ep_desc->wMaxPacketSize, ep->ep_desc->bmAttributes);
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t _ep_disable(uep_t ep)
|
||||
{
|
||||
RT_ASSERT(ep != RT_NULL);
|
||||
RT_ASSERT(ep->ep_desc != RT_NULL);
|
||||
HAL_PCD_EP_Close(&_stm_pcd, ep->ep_desc->bEndpointAddress);
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_size_t _ep_read(rt_uint8_t address, void *buffer)
|
||||
{
|
||||
rt_size_t size = 0;
|
||||
RT_ASSERT(buffer != RT_NULL);
|
||||
return size;
|
||||
}
|
||||
|
||||
static rt_size_t _ep_read_prepare(rt_uint8_t address, void *buffer, rt_size_t size)
|
||||
{
|
||||
HAL_PCD_EP_Receive(&_stm_pcd, address, buffer, size);
|
||||
return size;
|
||||
}
|
||||
|
||||
static rt_size_t _ep_write(rt_uint8_t address, void *buffer, rt_size_t size)
|
||||
{
|
||||
HAL_PCD_EP_Transmit(&_stm_pcd, address, buffer, size);
|
||||
return size;
|
||||
}
|
||||
|
||||
static rt_err_t _ep0_send_status(void)
|
||||
{
|
||||
HAL_PCD_EP_Transmit(&_stm_pcd, 0x00, NULL, 0);
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t _suspend(void)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t _wakeup(void)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t _init(rt_device_t device)
|
||||
{
|
||||
PCD_HandleTypeDef *pcd;
|
||||
/* Set LL Driver parameters */
|
||||
pcd = (PCD_HandleTypeDef *)device->user_data;
|
||||
pcd->Instance = USBD_INSTANCE;
|
||||
memset(&pcd->Init, 0, sizeof pcd->Init);
|
||||
pcd->Init.dev_endpoints = 8;
|
||||
pcd->Init.speed = USBD_PCD_SPEED;
|
||||
pcd->Init.ep0_mps = DEP0CTL_MPS_64;
|
||||
#if !defined(SOC_SERIES_STM32F1)
|
||||
pcd->Init.phy_itface = USBD_PCD_PHY_MODULE;
|
||||
#endif
|
||||
/* Initialize LL Driver */
|
||||
HAL_PCD_Init(pcd);
|
||||
/* USB interrupt Init */
|
||||
HAL_NVIC_SetPriority(USBD_IRQ_TYPE, 2, 0);
|
||||
HAL_NVIC_EnableIRQ(USBD_IRQ_TYPE);
|
||||
#if !defined(SOC_SERIES_STM32F1)
|
||||
HAL_PCDEx_SetRxFiFo(pcd, 0x80);
|
||||
HAL_PCDEx_SetTxFiFo(pcd, 0, 0x40);
|
||||
HAL_PCDEx_SetTxFiFo(pcd, 1, 0x40);
|
||||
HAL_PCDEx_SetTxFiFo(pcd, 2, 0x40);
|
||||
HAL_PCDEx_SetTxFiFo(pcd, 3, 0x40);
|
||||
#else
|
||||
HAL_PCDEx_PMAConfig(pcd, 0x00, PCD_SNG_BUF, 0x18);
|
||||
HAL_PCDEx_PMAConfig(pcd, 0x80, PCD_SNG_BUF, 0x58);
|
||||
HAL_PCDEx_PMAConfig(pcd, 0x81, PCD_SNG_BUF, 0x98);
|
||||
HAL_PCDEx_PMAConfig(pcd, 0x01, PCD_SNG_BUF, 0x118);
|
||||
HAL_PCDEx_PMAConfig(pcd, 0x82, PCD_SNG_BUF, 0xD8);
|
||||
HAL_PCDEx_PMAConfig(pcd, 0x02, PCD_SNG_BUF, 0x158);
|
||||
HAL_PCDEx_PMAConfig(pcd, 0x83, PCD_SNG_BUF, 0x198);
|
||||
#endif
|
||||
HAL_PCD_Start(pcd);
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
const static struct udcd_ops _udc_ops =
|
||||
{
|
||||
_set_address,
|
||||
_set_config,
|
||||
_ep_set_stall,
|
||||
_ep_clear_stall,
|
||||
_ep_enable,
|
||||
_ep_disable,
|
||||
_ep_read_prepare,
|
||||
_ep_read,
|
||||
_ep_write,
|
||||
_ep0_send_status,
|
||||
_suspend,
|
||||
_wakeup,
|
||||
};
|
||||
|
||||
#ifdef RT_USING_DEVICE_OPS
|
||||
const static struct rt_device_ops _ops =
|
||||
{
|
||||
_init,
|
||||
RT_NULL,
|
||||
RT_NULL,
|
||||
RT_NULL,
|
||||
RT_NULL,
|
||||
RT_NULL,
|
||||
};
|
||||
#endif
|
||||
|
||||
int stm_usbd_register(void)
|
||||
{
|
||||
rt_memset((void *)&_stm_udc, 0, sizeof(struct udcd));
|
||||
_stm_udc.parent.type = RT_Device_Class_USBDevice;
|
||||
#ifdef RT_USING_DEVICE_OPS
|
||||
_stm_udc.parent.ops = &_ops;
|
||||
#else
|
||||
_stm_udc.parent.init = _init;
|
||||
#endif
|
||||
_stm_udc.parent.user_data = &_stm_pcd;
|
||||
_stm_udc.ops = &_udc_ops;
|
||||
/* Register endpoint infomation */
|
||||
_stm_udc.ep_pool = _ep_pool;
|
||||
_stm_udc.ep0.id = &_ep_pool[0];
|
||||
#ifdef BSP_USBD_SPEED_HS
|
||||
_stm_udc.device_is_hs = RT_TRUE;
|
||||
#endif
|
||||
rt_device_register((rt_device_t)&_stm_udc, "usbd", 0);
|
||||
rt_usb_device_init();
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_DEVICE_EXPORT(stm_usbd_register);
|
||||
#endif
|
||||
254
drivers/drv_usbh.c
Normal file
254
drivers/drv_usbh.c
Normal file
@ -0,0 +1,254 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2017-10-30 ZYH the first version
|
||||
* 2019-12-19 tyustli port to stm32 series
|
||||
*/
|
||||
#include "drv_usbh.h"
|
||||
#include "board.h"
|
||||
#include<rtthread.h>
|
||||
#include<rtdevice.h>
|
||||
|
||||
#ifdef BSP_USING_USBHOST
|
||||
|
||||
static HCD_HandleTypeDef stm32_hhcd_fs;
|
||||
static struct rt_completion urb_completion;
|
||||
static volatile rt_bool_t connect_status = RT_FALSE;
|
||||
|
||||
void OTG_FS_IRQHandler(void)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
HAL_HCD_IRQHandler(&stm32_hhcd_fs);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
|
||||
{
|
||||
uhcd_t hcd = (uhcd_t)hhcd->pData;
|
||||
if (!connect_status)
|
||||
{
|
||||
connect_status = RT_TRUE;
|
||||
RT_DEBUG_LOG(RT_DEBUG_USB, ("usb connected\n"));
|
||||
rt_usbh_root_hub_connect_handler(hcd, OTG_FS_PORT, RT_FALSE);
|
||||
}
|
||||
}
|
||||
|
||||
void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
|
||||
{
|
||||
uhcd_t hcd = (uhcd_t)hhcd->pData;
|
||||
if (connect_status)
|
||||
{
|
||||
connect_status = RT_FALSE;
|
||||
RT_DEBUG_LOG(RT_DEBUG_USB, ("usb disconnnect\n"));
|
||||
rt_usbh_root_hub_disconnect_handler(hcd, OTG_FS_PORT);
|
||||
}
|
||||
}
|
||||
|
||||
void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
|
||||
{
|
||||
rt_completion_done(&urb_completion);
|
||||
}
|
||||
|
||||
static rt_err_t drv_reset_port(rt_uint8_t port)
|
||||
{
|
||||
RT_DEBUG_LOG(RT_DEBUG_USB, ("reset port\n"));
|
||||
HAL_HCD_ResetPort(&stm32_hhcd_fs);
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static int drv_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes, int timeouts)
|
||||
{
|
||||
int timeout = timeouts;
|
||||
|
||||
while (1)
|
||||
{
|
||||
if (!connect_status)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
rt_completion_init(&urb_completion);
|
||||
HAL_HCD_HC_SubmitRequest(&stm32_hhcd_fs,
|
||||
pipe->pipe_index,
|
||||
(pipe->ep.bEndpointAddress & 0x80) >> 7,
|
||||
pipe->ep.bmAttributes,
|
||||
token,
|
||||
buffer,
|
||||
nbytes,
|
||||
0);
|
||||
rt_completion_wait(&urb_completion, timeout);
|
||||
rt_thread_mdelay(1);
|
||||
if (HAL_HCD_HC_GetState(&stm32_hhcd_fs, pipe->pipe_index) == HC_NAK)
|
||||
{
|
||||
RT_DEBUG_LOG(RT_DEBUG_USB, ("nak\n"));
|
||||
if (pipe->ep.bmAttributes == USB_EP_ATTR_INT)
|
||||
{
|
||||
rt_thread_delay((pipe->ep.bInterval * RT_TICK_PER_SECOND / 1000) > 0 ? (pipe->ep.bInterval * RT_TICK_PER_SECOND / 1000) : 1);
|
||||
}
|
||||
HAL_HCD_HC_Halt(&stm32_hhcd_fs, pipe->pipe_index);
|
||||
HAL_HCD_HC_Init(&stm32_hhcd_fs,
|
||||
pipe->pipe_index,
|
||||
pipe->ep.bEndpointAddress,
|
||||
pipe->inst->address,
|
||||
USB_OTG_SPEED_FULL,
|
||||
pipe->ep.bmAttributes,
|
||||
pipe->ep.wMaxPacketSize);
|
||||
continue;
|
||||
}
|
||||
else if (HAL_HCD_HC_GetState(&stm32_hhcd_fs, pipe->pipe_index) == HC_STALL)
|
||||
{
|
||||
RT_DEBUG_LOG(RT_DEBUG_USB, ("stall\n"));
|
||||
pipe->status = UPIPE_STATUS_STALL;
|
||||
if (pipe->callback != RT_NULL)
|
||||
{
|
||||
pipe->callback(pipe);
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
else if (HAL_HCD_HC_GetState(&stm32_hhcd_fs, pipe->pipe_index) == URB_ERROR)
|
||||
{
|
||||
RT_DEBUG_LOG(RT_DEBUG_USB, ("error\n"));
|
||||
pipe->status = UPIPE_STATUS_ERROR;
|
||||
if (pipe->callback != RT_NULL)
|
||||
{
|
||||
pipe->callback(pipe);
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
else if(URB_DONE == HAL_HCD_HC_GetURBState(&stm32_hhcd_fs, pipe->pipe_index))
|
||||
{
|
||||
RT_DEBUG_LOG(RT_DEBUG_USB, ("ok\n"));
|
||||
pipe->status = UPIPE_STATUS_OK;
|
||||
if (pipe->callback != RT_NULL)
|
||||
{
|
||||
pipe->callback(pipe);
|
||||
}
|
||||
size_t size = HAL_HCD_HC_GetXferCount(&stm32_hhcd_fs, pipe->pipe_index);
|
||||
if (pipe->ep.bEndpointAddress & 0x80)
|
||||
{
|
||||
return size;
|
||||
}
|
||||
else if (pipe->ep.bEndpointAddress & 0x00)
|
||||
{
|
||||
return size;
|
||||
}
|
||||
return nbytes;
|
||||
}
|
||||
|
||||
continue;
|
||||
}
|
||||
}
|
||||
|
||||
static rt_uint16_t pipe_index = 0;
|
||||
static rt_uint8_t drv_get_free_pipe_index(void)
|
||||
{
|
||||
rt_uint8_t idx;
|
||||
for (idx = 1; idx < 16; idx++)
|
||||
{
|
||||
if (!(pipe_index & (0x01 << idx)))
|
||||
{
|
||||
pipe_index |= (0x01 << idx);
|
||||
return idx;
|
||||
}
|
||||
}
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
static void drv_free_pipe_index(rt_uint8_t index)
|
||||
{
|
||||
pipe_index &= ~(0x01 << index);
|
||||
}
|
||||
|
||||
static rt_err_t drv_open_pipe(upipe_t pipe)
|
||||
{
|
||||
pipe->pipe_index = drv_get_free_pipe_index();
|
||||
HAL_HCD_HC_Init(&stm32_hhcd_fs,
|
||||
pipe->pipe_index,
|
||||
pipe->ep.bEndpointAddress,
|
||||
pipe->inst->address,
|
||||
USB_OTG_SPEED_FULL,
|
||||
pipe->ep.bmAttributes,
|
||||
pipe->ep.wMaxPacketSize);
|
||||
/* Set DATA0 PID token*/
|
||||
if (stm32_hhcd_fs.hc[pipe->pipe_index].ep_is_in)
|
||||
{
|
||||
stm32_hhcd_fs.hc[pipe->pipe_index].toggle_in = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
stm32_hhcd_fs.hc[pipe->pipe_index].toggle_out = 0;
|
||||
}
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t drv_close_pipe(upipe_t pipe)
|
||||
{
|
||||
HAL_HCD_HC_Halt(&stm32_hhcd_fs, pipe->pipe_index);
|
||||
drv_free_pipe_index(pipe->pipe_index);
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static struct uhcd_ops _uhcd_ops =
|
||||
{
|
||||
drv_reset_port,
|
||||
drv_pipe_xfer,
|
||||
drv_open_pipe,
|
||||
drv_close_pipe,
|
||||
};
|
||||
|
||||
static rt_err_t stm32_hcd_init(rt_device_t device)
|
||||
{
|
||||
HCD_HandleTypeDef *hhcd = (HCD_HandleTypeDef *)device->user_data;
|
||||
hhcd->Instance = USB_OTG_FS;
|
||||
hhcd->Init.Host_channels = 8;
|
||||
hhcd->Init.speed = HCD_SPEED_FULL;
|
||||
hhcd->Init.dma_enable = DISABLE;
|
||||
hhcd->Init.phy_itface = HCD_PHY_EMBEDDED;
|
||||
hhcd->Init.Sof_enable = DISABLE;
|
||||
RT_ASSERT(HAL_HCD_Init(hhcd) == HAL_OK);
|
||||
HAL_HCD_Start(hhcd);
|
||||
#ifdef USBH_USING_CONTROLLABLE_POWER
|
||||
rt_pin_mode(USBH_POWER_PIN, PIN_MODE_OUTPUT);
|
||||
rt_pin_write(USBH_POWER_PIN, PIN_LOW);
|
||||
#endif
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
int stm_usbh_register(void)
|
||||
{
|
||||
rt_err_t res = -RT_ERROR;
|
||||
|
||||
uhcd_t uhcd = (uhcd_t)rt_malloc(sizeof(struct uhcd));
|
||||
if (uhcd == RT_NULL)
|
||||
{
|
||||
rt_kprintf("uhcd malloc failed\r\n");
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
rt_memset((void *)uhcd, 0, sizeof(struct uhcd));
|
||||
|
||||
uhcd->parent.type = RT_Device_Class_USBHost;
|
||||
uhcd->parent.init = stm32_hcd_init;
|
||||
uhcd->parent.user_data = &stm32_hhcd_fs;
|
||||
|
||||
uhcd->ops = &_uhcd_ops;
|
||||
uhcd->num_ports = OTG_FS_PORT;
|
||||
stm32_hhcd_fs.pData = uhcd;
|
||||
|
||||
res = rt_device_register(&uhcd->parent, "usbh", RT_DEVICE_FLAG_DEACTIVATE);
|
||||
if (res != RT_EOK)
|
||||
{
|
||||
rt_kprintf("register usb host failed res = %d\r\n", res);
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
rt_usb_host_init();
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_DEVICE_EXPORT(stm_usbh_register);
|
||||
|
||||
#endif
|
||||
133
drivers/drv_wdt.c
Normal file
133
drivers/drv_wdt.c
Normal file
@ -0,0 +1,133 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-07 balanceTWK first version
|
||||
*/
|
||||
|
||||
#include <board.h>
|
||||
#include<rtthread.h>
|
||||
#include<rtdevice.h>
|
||||
|
||||
#ifdef RT_USING_WDT
|
||||
|
||||
//#define DRV_DEBUG
|
||||
#define LOG_TAG "drv.wdt"
|
||||
#include <drv_log.h>
|
||||
|
||||
struct stm32_wdt_obj
|
||||
{
|
||||
IWDG_HandleTypeDef hiwdg;
|
||||
rt_uint16_t is_start;
|
||||
};
|
||||
static struct stm32_wdt_obj stm32_wdt;
|
||||
static struct rt_watchdog_ops ops;
|
||||
static rt_watchdog_t watchdog;
|
||||
|
||||
static rt_err_t wdt_init(rt_watchdog_t *wdt)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
|
||||
{
|
||||
switch (cmd)
|
||||
{
|
||||
/* feed the watchdog */
|
||||
case RT_DEVICE_CTRL_WDT_KEEPALIVE:
|
||||
if(HAL_IWDG_Refresh(&stm32_wdt.hiwdg) != HAL_OK)
|
||||
{
|
||||
LOG_E("watch dog keepalive fail.");
|
||||
}
|
||||
break;
|
||||
/* set watchdog timeout */
|
||||
case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
|
||||
#if defined(LSI_VALUE)
|
||||
if(LSI_VALUE)
|
||||
{
|
||||
stm32_wdt.hiwdg.Init.Reload = (*((rt_uint32_t*)arg)) * LSI_VALUE / 256 ;
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_E("Please define the value of LSI_VALUE!");
|
||||
}
|
||||
if(stm32_wdt.hiwdg.Init.Reload > 0xFFF)
|
||||
{
|
||||
LOG_E("wdg set timeout parameter too large, please less than %ds",0xFFF * 256 / LSI_VALUE);
|
||||
return -RT_EINVAL;
|
||||
}
|
||||
#else
|
||||
#error "Please define the value of LSI_VALUE!"
|
||||
#endif
|
||||
if(stm32_wdt.is_start)
|
||||
{
|
||||
if (HAL_IWDG_Init(&stm32_wdt.hiwdg) != HAL_OK)
|
||||
{
|
||||
LOG_E("wdg set timeout failed.");
|
||||
return -RT_ERROR;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
|
||||
#if defined(LSI_VALUE)
|
||||
if(LSI_VALUE)
|
||||
{
|
||||
(*((rt_uint32_t*)arg)) = stm32_wdt.hiwdg.Init.Reload * 256 / LSI_VALUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_E("Please define the value of LSI_VALUE!");
|
||||
}
|
||||
#else
|
||||
#error "Please define the value of LSI_VALUE!"
|
||||
#endif
|
||||
break;
|
||||
case RT_DEVICE_CTRL_WDT_START:
|
||||
if (HAL_IWDG_Init(&stm32_wdt.hiwdg) != HAL_OK)
|
||||
{
|
||||
LOG_E("wdt start failed.");
|
||||
return -RT_ERROR;
|
||||
}
|
||||
stm32_wdt.is_start = 1;
|
||||
break;
|
||||
default:
|
||||
LOG_W("This command is not supported.");
|
||||
return -RT_ERROR;
|
||||
}
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
int rt_wdt_init(void)
|
||||
{
|
||||
#if defined(SOC_SERIES_STM32H7)
|
||||
stm32_wdt.hiwdg.Instance = IWDG1;
|
||||
#else
|
||||
stm32_wdt.hiwdg.Instance = IWDG;
|
||||
#endif
|
||||
stm32_wdt.hiwdg.Init.Prescaler = IWDG_PRESCALER_256;
|
||||
|
||||
stm32_wdt.hiwdg.Init.Reload = 0x00000FFF;
|
||||
#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7) \
|
||||
|| defined(SOC_SERIES_STM32H7)
|
||||
stm32_wdt.hiwdg.Init.Window = 0x00000FFF;
|
||||
#endif
|
||||
stm32_wdt.is_start = 0;
|
||||
|
||||
ops.init = &wdt_init;
|
||||
ops.control = &wdt_control;
|
||||
watchdog.ops = &ops;
|
||||
/* register watchdog device */
|
||||
if (rt_hw_watchdog_register(&watchdog, "wdt", RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK)
|
||||
{
|
||||
LOG_E("wdt device register failed.");
|
||||
return -RT_ERROR;
|
||||
}
|
||||
LOG_D("wdt device register success.");
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_BOARD_EXPORT(rt_wdt_init);
|
||||
|
||||
#endif /* RT_USING_WDT */
|
||||
72
drivers/include/config/adc_config.h
Normal file
72
drivers/include/config/adc_config.h
Normal file
@ -0,0 +1,72 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-07 zylx first version
|
||||
*/
|
||||
|
||||
#ifndef __ADC_CONFIG_H__
|
||||
#define __ADC_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_ADC1
|
||||
#ifndef ADC1_CONFIG
|
||||
#define ADC1_CONFIG \
|
||||
{ \
|
||||
.Instance = ADC1, \
|
||||
.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
|
||||
.Init.ScanConvMode = ADC_SCAN_DISABLE, \
|
||||
.Init.ContinuousConvMode = DISABLE, \
|
||||
.Init.NbrOfConversion = 1, \
|
||||
.Init.DiscontinuousConvMode = DISABLE, \
|
||||
.Init.NbrOfDiscConversion = 1, \
|
||||
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
|
||||
}
|
||||
#endif /* ADC1_CONFIG */
|
||||
#endif /* BSP_USING_ADC1 */
|
||||
|
||||
#ifdef BSP_USING_ADC2
|
||||
#ifndef ADC2_CONFIG
|
||||
#define ADC2_CONFIG \
|
||||
{ \
|
||||
.Instance = ADC2, \
|
||||
.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
|
||||
.Init.ScanConvMode = ADC_SCAN_DISABLE, \
|
||||
.Init.ContinuousConvMode = DISABLE, \
|
||||
.Init.NbrOfConversion = 1, \
|
||||
.Init.DiscontinuousConvMode = DISABLE, \
|
||||
.Init.NbrOfDiscConversion = 1, \
|
||||
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
|
||||
}
|
||||
#endif /* ADC2_CONFIG */
|
||||
#endif /* BSP_USING_ADC2 */
|
||||
|
||||
#ifdef BSP_USING_ADC3
|
||||
#ifndef ADC3_CONFIG
|
||||
#define ADC3_CONFIG \
|
||||
{ \
|
||||
.Instance = ADC3, \
|
||||
.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
|
||||
.Init.ScanConvMode = ADC_SCAN_DISABLE, \
|
||||
.Init.ContinuousConvMode = DISABLE, \
|
||||
.Init.NbrOfConversion = 1, \
|
||||
.Init.DiscontinuousConvMode = DISABLE, \
|
||||
.Init.NbrOfDiscConversion = 1, \
|
||||
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
|
||||
}
|
||||
#endif /* ADC3_CONFIG */
|
||||
#endif /* BSP_USING_ADC3 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ADC_CONFIG_H__ */
|
||||
127
drivers/include/config/dma_config.h
Normal file
127
drivers/include/config/dma_config.h
Normal file
@ -0,0 +1,127 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-01-02 SummerGift first version
|
||||
* 2019-01-08 SummerGift clean up the code
|
||||
*/
|
||||
|
||||
#ifndef __DMA_CONFIG_H__
|
||||
#define __DMA_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* DMA1 channel1 */
|
||||
/* DMA1 channel2 */
|
||||
#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
|
||||
#define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler
|
||||
#define SPI1_RX_DMA_RCC RCC_AHBENR_DMA1EN
|
||||
#define SPI1_RX_DMA_INSTANCE DMA1_Channel2
|
||||
#define SPI1_RX_DMA_IRQ DMA1_Channel2_IRQn
|
||||
#elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE)
|
||||
#define UART3_DMA_TX_IRQHandler DMA1_Channel2_IRQHandler
|
||||
#define UART3_TX_DMA_RCC RCC_AHBENR_DMA1EN
|
||||
#define UART3_TX_DMA_INSTANCE DMA1_Channel2
|
||||
#define UART3_TX_DMA_IRQ DMA1_Channel2_IRQn
|
||||
#endif
|
||||
|
||||
/* DMA1 channel3 */
|
||||
#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
|
||||
#define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler
|
||||
#define SPI1_TX_DMA_RCC RCC_AHBENR_DMA1EN
|
||||
#define SPI1_TX_DMA_INSTANCE DMA1_Channel3
|
||||
#define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn
|
||||
#elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
|
||||
#define UART3_DMA_RX_IRQHandler DMA1_Channel3_IRQHandler
|
||||
#define UART3_RX_DMA_RCC RCC_AHBENR_DMA1EN
|
||||
#define UART3_RX_DMA_INSTANCE DMA1_Channel3
|
||||
#define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn
|
||||
#endif
|
||||
|
||||
/* DMA1 channel4 */
|
||||
#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
|
||||
#define SPI2_DMA_RX_IRQHandler DMA1_Channel4_IRQHandler
|
||||
#define SPI2_RX_DMA_RCC RCC_AHBENR_DMA1EN
|
||||
#define SPI2_RX_DMA_INSTANCE DMA1_Channel4
|
||||
#define SPI2_RX_DMA_IRQ DMA1_Channel4_IRQn
|
||||
#elif defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
|
||||
#define UART1_DMA_TX_IRQHandler DMA1_Channel4_IRQHandler
|
||||
#define UART1_TX_DMA_RCC RCC_AHBENR_DMA1EN
|
||||
#define UART1_TX_DMA_INSTANCE DMA1_Channel4
|
||||
#define UART1_TX_DMA_IRQ DMA1_Channel4_IRQn
|
||||
#endif
|
||||
|
||||
/* DMA1 channel5 */
|
||||
#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
|
||||
#define SPI2_DMA_TX_IRQHandler DMA1_Channel5_IRQHandler
|
||||
#define SPI2_TX_DMA_RCC RCC_AHBENR_DMA1EN
|
||||
#define SPI2_TX_DMA_INSTANCE DMA1_Channel5
|
||||
#define SPI2_TX_DMA_IRQ DMA1_Channel5_IRQn
|
||||
|
||||
#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
|
||||
#define UART1_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler
|
||||
#define UART1_RX_DMA_RCC RCC_AHBENR_DMA1EN
|
||||
#define UART1_RX_DMA_INSTANCE DMA1_Channel5
|
||||
#define UART1_RX_DMA_IRQ DMA1_Channel5_IRQn
|
||||
#endif
|
||||
|
||||
/* DMA1 channel6 */
|
||||
#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
|
||||
#define UART2_DMA_RX_IRQHandler DMA1_Channel6_IRQHandler
|
||||
#define UART2_RX_DMA_RCC RCC_AHBENR_DMA1EN
|
||||
#define UART2_RX_DMA_INSTANCE DMA1_Channel6
|
||||
#define UART2_RX_DMA_IRQ DMA1_Channel6_IRQn
|
||||
#endif
|
||||
|
||||
/* DMA1 channel7 */
|
||||
#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
|
||||
#define UART2_DMA_TX_IRQHandler DMA1_Channel7_IRQHandler
|
||||
#define UART2_TX_DMA_RCC RCC_AHBENR_DMA1EN
|
||||
#define UART2_TX_DMA_INSTANCE DMA1_Channel7
|
||||
#define UART2_TX_DMA_IRQ DMA1_Channel7_IRQn
|
||||
#endif
|
||||
|
||||
/* DMA2 channel1 */
|
||||
#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
|
||||
#define SPI3_DMA_RX_IRQHandler DMA2_Channel1_IRQHandler
|
||||
#define SPI3_RX_DMA_RCC RCC_AHBENR_DMA2EN
|
||||
#define SPI3_RX_DMA_INSTANCE DMA2_Channel1
|
||||
#define SPI3_RX_DMA_IRQ DMA2_Channel1_IRQn
|
||||
#endif
|
||||
|
||||
/* DMA2 channel2 */
|
||||
#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
|
||||
#define SPI3_DMA_TX_IRQHandler DMA2_Channel2_IRQHandler
|
||||
#define SPI3_TX_DMA_RCC RCC_AHBENR_DMA2EN
|
||||
#define SPI3_TX_DMA_INSTANCE DMA2_Channel2
|
||||
#define SPI3_TX_DMA_IRQ DMA2_Channel2_IRQn
|
||||
#endif
|
||||
|
||||
/* DMA2 channel3 */
|
||||
#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
|
||||
#define UART4_DMA_RX_IRQHandler DMA2_Channel3_IRQHandler
|
||||
#define UART4_RX_DMA_RCC RCC_AHBENR_DMA2EN
|
||||
#define UART4_RX_DMA_INSTANCE DMA2_Channel3
|
||||
#define UART4_RX_DMA_IRQ DMA2_Channel3_IRQn
|
||||
#endif
|
||||
/* DMA2 channel4 */
|
||||
/* DMA2 channel5 */
|
||||
#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
|
||||
#define UART4_DMA_TX_IRQHandler DMA2_Channel4_5_IRQHandler
|
||||
#define UART4_TX_DMA_RCC RCC_AHBENR_DMA2EN
|
||||
#define UART4_TX_DMA_INSTANCE DMA2_Channel5
|
||||
#define UART4_TX_DMA_IRQ DMA2_Channel4_5_IRQn
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DMA_CONFIG_H__ */
|
||||
68
drivers/include/config/pulse_encoder_config.h
Normal file
68
drivers/include/config/pulse_encoder_config.h
Normal file
@ -0,0 +1,68 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-08-23 balanceTWK first version
|
||||
*/
|
||||
|
||||
#ifndef __PULSE_ENCODER_CONFIG_H__
|
||||
#define __PULSE_ENCODER_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER1
|
||||
#ifndef PULSE_ENCODER1_CONFIG
|
||||
#define PULSE_ENCODER1_CONFIG \
|
||||
{ \
|
||||
.tim_handler.Instance = TIM1, \
|
||||
.encoder_irqn = TIM1_UP_IRQn, \
|
||||
.name = "pulse1" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER1_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER1 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER2
|
||||
#ifndef PULSE_ENCODER2_CONFIG
|
||||
#define PULSE_ENCODER2_CONFIG \
|
||||
{ \
|
||||
.tim_handler.Instance = TIM2, \
|
||||
.encoder_irqn = TIM2_IRQn, \
|
||||
.name = "pulse2" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER2_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER2 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER3
|
||||
#ifndef PULSE_ENCODER3_CONFIG
|
||||
#define PULSE_ENCODER3_CONFIG \
|
||||
{ \
|
||||
.tim_handler.Instance = TIM3, \
|
||||
.encoder_irqn = TIM3_IRQn, \
|
||||
.name = "pulse3" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER3_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER3 */
|
||||
|
||||
#ifdef BSP_USING_PULSE_ENCODER4
|
||||
#ifndef PULSE_ENCODER4_CONFIG
|
||||
#define PULSE_ENCODER4_CONFIG \
|
||||
{ \
|
||||
.tim_handler.Instance = TIM4, \
|
||||
.encoder_irqn = TIM4_IRQn, \
|
||||
.name = "pulse4" \
|
||||
}
|
||||
#endif /* PULSE_ENCODER4_CONFIG */
|
||||
#endif /* BSP_USING_PULSE_ENCODER4 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __PULSE_ENCODER_CONFIG_H__ */
|
||||
68
drivers/include/config/pwm_config.h
Normal file
68
drivers/include/config/pwm_config.h
Normal file
@ -0,0 +1,68 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-13 zylx first version
|
||||
*/
|
||||
|
||||
#ifndef __PWM_CONFIG_H__
|
||||
#define __PWM_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PWM2
|
||||
#ifndef PWM2_CONFIG
|
||||
#define PWM2_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM2, \
|
||||
.name = "pwm2", \
|
||||
.channel = 0 \
|
||||
}
|
||||
#endif /* PWM2_CONFIG */
|
||||
#endif /* BSP_USING_PWM2 */
|
||||
|
||||
#ifdef BSP_USING_PWM3
|
||||
#ifndef PWM3_CONFIG
|
||||
#define PWM3_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM3, \
|
||||
.name = "pwm3", \
|
||||
.channel = 0 \
|
||||
}
|
||||
#endif /* PWM3_CONFIG */
|
||||
#endif /* BSP_USING_PWM3 */
|
||||
|
||||
#ifdef BSP_USING_PWM4
|
||||
#ifndef PWM4_CONFIG
|
||||
#define PWM4_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM4, \
|
||||
.name = "pwm4", \
|
||||
.channel = 0 \
|
||||
}
|
||||
#endif /* PWM4_CONFIG */
|
||||
#endif /* BSP_USING_PWM4 */
|
||||
|
||||
#ifdef BSP_USING_PWM5
|
||||
#ifndef PWM5_CONFIG
|
||||
#define PWM5_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM5, \
|
||||
.name = "pwm5", \
|
||||
.channel = 0 \
|
||||
}
|
||||
#endif /* PWM5_CONFIG */
|
||||
#endif /* BSP_USING_PWM5 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __PWM_CONFIG_H__ */
|
||||
42
drivers/include/config/sdio_config.h
Normal file
42
drivers/include/config/sdio_config.h
Normal file
@ -0,0 +1,42 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-13 BalanceTWK first version
|
||||
*/
|
||||
|
||||
#ifndef __SDIO_CONFIG_H__
|
||||
#define __SDIO_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "stm32f1xx_hal.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_SDIO
|
||||
#define SDIO_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = SDIO, \
|
||||
.dma_rx.dma_rcc = RCC_AHBENR_DMA2EN, \
|
||||
.dma_tx.dma_rcc = RCC_AHBENR_DMA2EN, \
|
||||
.dma_rx.Instance = DMA2_Channel4, \
|
||||
.dma_rx.dma_irq = DMA2_Channel4_IRQn, \
|
||||
.dma_tx.Instance = DMA2_Channel4, \
|
||||
.dma_tx.dma_irq = DMA2_Channel4_IRQn, \
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SDIO_CONFIG_H__ */
|
||||
|
||||
|
||||
|
||||
124
drivers/include/config/spi_config.h
Normal file
124
drivers/include/config/spi_config.h
Normal file
@ -0,0 +1,124 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-06 SummerGift first version
|
||||
* 2019-01-05 SummerGift modify DMA support
|
||||
*/
|
||||
|
||||
#ifndef __SPI_CONFIG_H__
|
||||
#define __SPI_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_SPI1
|
||||
#ifndef SPI1_BUS_CONFIG
|
||||
#define SPI1_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI1, \
|
||||
.bus_name = "spi1", \
|
||||
}
|
||||
#endif /* SPI1_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI1 */
|
||||
|
||||
#ifdef BSP_SPI1_TX_USING_DMA
|
||||
#ifndef SPI1_TX_DMA_CONFIG
|
||||
#define SPI1_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI1_TX_DMA_RCC, \
|
||||
.Instance = SPI1_TX_DMA_INSTANCE, \
|
||||
.dma_irq = SPI1_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI1_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI1_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI1_RX_USING_DMA
|
||||
#ifndef SPI1_RX_DMA_CONFIG
|
||||
#define SPI1_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI1_RX_DMA_RCC, \
|
||||
.Instance = SPI1_RX_DMA_INSTANCE, \
|
||||
.dma_irq = SPI1_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI1_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI1_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_SPI2
|
||||
#ifndef SPI2_BUS_CONFIG
|
||||
#define SPI2_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI2, \
|
||||
.bus_name = "spi2", \
|
||||
}
|
||||
#endif /* SPI2_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI2 */
|
||||
|
||||
#ifdef BSP_SPI2_TX_USING_DMA
|
||||
#ifndef SPI2_TX_DMA_CONFIG
|
||||
#define SPI2_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI2_TX_DMA_RCC, \
|
||||
.Instance = SPI2_TX_DMA_INSTANCE, \
|
||||
.dma_irq = SPI2_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI2_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI2_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI2_RX_USING_DMA
|
||||
#ifndef SPI2_RX_DMA_CONFIG
|
||||
#define SPI2_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI2_RX_DMA_RCC, \
|
||||
.Instance = SPI2_RX_DMA_INSTANCE, \
|
||||
.dma_irq = SPI2_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI2_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI2_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_SPI3
|
||||
#ifndef SPI3_BUS_CONFIG
|
||||
#define SPI3_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI3, \
|
||||
.bus_name = "spi3", \
|
||||
}
|
||||
#endif /* SPI3_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI3 */
|
||||
|
||||
#ifdef BSP_SPI3_TX_USING_DMA
|
||||
#ifndef SPI3_TX_DMA_CONFIG
|
||||
#define SPI3_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI3_TX_DMA_RCC, \
|
||||
.Instance = SPI3_TX_DMA_INSTANCE, \
|
||||
.dma_irq = SPI3_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI3_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI3_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI3_RX_USING_DMA
|
||||
#ifndef SPI3_RX_DMA_CONFIG
|
||||
#define SPI3_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI3_RX_DMA_RCC, \
|
||||
.Instance = SPI3_RX_DMA_INSTANCE, \
|
||||
.dma_irq = SPI3_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI3_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI3_RX_USING_DMA */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SPI_CONFIG_H__ */
|
||||
|
||||
|
||||
|
||||
78
drivers/include/config/tim_config.h
Normal file
78
drivers/include/config/tim_config.h
Normal file
@ -0,0 +1,78 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-11 zylx first version
|
||||
*/
|
||||
|
||||
#ifndef __TIM_CONFIG_H__
|
||||
#define __TIM_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef TIM_DEV_INFO_CONFIG
|
||||
#define TIM_DEV_INFO_CONFIG \
|
||||
{ \
|
||||
.maxfreq = 1000000, \
|
||||
.minfreq = 2000, \
|
||||
.maxcnt = 0xFFFF, \
|
||||
.cntmode = HWTIMER_CNTMODE_UP, \
|
||||
}
|
||||
#endif /* TIM_DEV_INFO_CONFIG */
|
||||
|
||||
#ifdef BSP_USING_TIM2
|
||||
#ifndef TIM2_CONFIG
|
||||
#define TIM2_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM2, \
|
||||
.tim_irqn = TIM2_IRQn, \
|
||||
.name = "timer2", \
|
||||
}
|
||||
#endif /* TIM2_CONFIG */
|
||||
#endif /* BSP_USING_TIM2 */
|
||||
|
||||
#ifdef BSP_USING_TIM3
|
||||
#ifndef TIM3_CONFIG
|
||||
#define TIM3_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM3, \
|
||||
.tim_irqn = TIM3_IRQn, \
|
||||
.name = "timer3", \
|
||||
}
|
||||
#endif /* TIM3_CONFIG */
|
||||
#endif /* BSP_USING_TIM3 */
|
||||
|
||||
#ifdef BSP_USING_TIM4
|
||||
#ifndef TIM4_CONFIG
|
||||
#define TIM4_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM4, \
|
||||
.tim_irqn = TIM4_IRQn, \
|
||||
.name = "timer4", \
|
||||
}
|
||||
#endif /* TIM4_CONFIG */
|
||||
#endif /* BSP_USING_TIM4 */
|
||||
|
||||
#ifdef BSP_USING_TIM5
|
||||
#ifndef TIM5_CONFIG
|
||||
#define TIM5_CONFIG \
|
||||
{ \
|
||||
.tim_handle.Instance = TIM5, \
|
||||
.tim_irqn = TIM5_IRQn, \
|
||||
.name = "timer5", \
|
||||
}
|
||||
#endif /* TIM5_CONFIG */
|
||||
#endif /* BSP_USING_TIM5 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __TIM_CONFIG_H__ */
|
||||
202
drivers/include/config/uart_config.h
Normal file
202
drivers/include/config/uart_config.h
Normal file
@ -0,0 +1,202 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-10-30 SummerGift first version
|
||||
* 2019-01-03 zylx modify dma support
|
||||
* 2020-06-03 chenyaxing modify uart config
|
||||
*/
|
||||
|
||||
#ifndef __UART_CONFIG_H__
|
||||
#define __UART_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <board.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_UART1)
|
||||
#ifndef UART1_CONFIG
|
||||
#define UART1_CONFIG \
|
||||
{ \
|
||||
.name = "uart1", \
|
||||
.Instance = USART1, \
|
||||
.irq_type = USART1_IRQn, \
|
||||
.tx_pin_name = BSP_UART1_TX_PIN, \
|
||||
.rx_pin_name = BSP_UART1_RX_PIN, \
|
||||
}
|
||||
#endif /* UART1_CONFIG */
|
||||
|
||||
#if defined(BSP_UART1_RX_USING_DMA)
|
||||
#ifndef UART1_DMA_RX_CONFIG
|
||||
#define UART1_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART1_RX_DMA_INSTANCE, \
|
||||
.dma_rcc = UART1_RX_DMA_RCC, \
|
||||
.dma_irq = UART1_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART1_DMA_RX_CONFIG */
|
||||
#endif /* BSP_UART1_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_UART1_TX_USING_DMA)
|
||||
#ifndef UART1_DMA_TX_CONFIG
|
||||
#define UART1_DMA_TX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART1_TX_DMA_INSTANCE, \
|
||||
.dma_rcc = UART1_TX_DMA_RCC, \
|
||||
.dma_irq = UART1_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART1_DMA_TX_CONFIG */
|
||||
#endif /* BSP_UART1_TX_USING_DMA */
|
||||
#endif /* BSP_USING_UART1 */
|
||||
|
||||
#if defined(BSP_USING_UART2)
|
||||
#ifndef UART2_CONFIG
|
||||
#define UART2_CONFIG \
|
||||
{ \
|
||||
.name = "uart2", \
|
||||
.Instance = USART2, \
|
||||
.irq_type = USART2_IRQn, \
|
||||
.tx_pin_name = BSP_UART2_TX_PIN, \
|
||||
.rx_pin_name = BSP_UART2_RX_PIN, \
|
||||
}
|
||||
#endif /* UART2_CONFIG */
|
||||
|
||||
#if defined(BSP_UART2_RX_USING_DMA)
|
||||
#ifndef UART2_DMA_RX_CONFIG
|
||||
#define UART2_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART2_RX_DMA_INSTANCE, \
|
||||
.dma_rcc = UART2_RX_DMA_RCC, \
|
||||
.dma_irq = UART2_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART2_DMA_RX_CONFIG */
|
||||
#endif /* BSP_UART2_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_UART2_TX_USING_DMA)
|
||||
#ifndef UART2_DMA_TX_CONFIG
|
||||
#define UART2_DMA_TX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART2_TX_DMA_INSTANCE, \
|
||||
.dma_rcc = UART2_TX_DMA_RCC, \
|
||||
.dma_irq = UART2_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART2_DMA_TX_CONFIG */
|
||||
#endif /* BSP_UART2_TX_USING_DMA */
|
||||
#endif /* BSP_USING_UART2 */
|
||||
|
||||
#if defined(BSP_USING_UART3)
|
||||
#ifndef UART3_CONFIG
|
||||
#define UART3_CONFIG \
|
||||
{ \
|
||||
.name = "uart3", \
|
||||
.Instance = USART3, \
|
||||
.irq_type = USART3_IRQn, \
|
||||
.tx_pin_name = BSP_UART3_TX_PIN, \
|
||||
.rx_pin_name = BSP_UART3_RX_PIN, \
|
||||
}
|
||||
#endif /* UART3_CONFIG */
|
||||
|
||||
#if defined(BSP_UART3_RX_USING_DMA)
|
||||
#ifndef UART3_DMA_RX_CONFIG
|
||||
#define UART3_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART3_RX_DMA_INSTANCE, \
|
||||
.dma_rcc = UART3_RX_DMA_RCC, \
|
||||
.dma_irq = UART3_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART3_DMA_RX_CONFIG */
|
||||
#endif /* BSP_UART3_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_UART3_TX_USING_DMA)
|
||||
#ifndef UART3_DMA_TX_CONFIG
|
||||
#define UART3_DMA_TX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART3_TX_DMA_INSTANCE, \
|
||||
.dma_rcc = UART3_TX_DMA_RCC, \
|
||||
.dma_irq = UART3_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART3_DMA_TX_CONFIG */
|
||||
#endif /* BSP_UART3_TX_USING_DMA */
|
||||
#endif /* BSP_USING_UART3 */
|
||||
|
||||
#if defined(BSP_USING_UART4)
|
||||
#ifndef UART4_CONFIG
|
||||
#define UART4_CONFIG \
|
||||
{ \
|
||||
.name = "uart4", \
|
||||
.Instance = UART4, \
|
||||
.irq_type = UART4_IRQn, \
|
||||
.tx_pin_name = BSP_UART4_TX_PIN, \
|
||||
.rx_pin_name = BSP_UART4_RX_PIN, \
|
||||
}
|
||||
#endif /* UART4_CONFIG */
|
||||
|
||||
#if defined(BSP_UART4_RX_USING_DMA)
|
||||
#ifndef UART4_DMA_RX_CONFIG
|
||||
#define UART4_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART4_RX_DMA_INSTANCE, \
|
||||
.dma_rcc = UART4_RX_DMA_RCC, \
|
||||
.dma_irq = UART4_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART4_DMA_RX_CONFIG */
|
||||
#endif /* BSP_UART4_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_UART4_TX_USING_DMA)
|
||||
#ifndef UART4_DMA_TX_CONFIG
|
||||
#define UART4_DMA_TX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART4_TX_DMA_INSTANCE, \
|
||||
.dma_rcc = UART4_TX_DMA_RCC, \
|
||||
.dma_irq = UART4_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART4_DMA_TX_CONFIG */
|
||||
#endif /* BSP_UART4_RX_USING_DMA */
|
||||
#endif /* BSP_USING_UART4 */
|
||||
|
||||
#if defined(BSP_USING_UART5)
|
||||
#ifndef UART5_CONFIG
|
||||
#define UART5_CONFIG \
|
||||
{ \
|
||||
.name = "uart5", \
|
||||
.Instance = UART5, \
|
||||
.irq_type = UART5_IRQn, \
|
||||
.tx_pin_name = BSP_UART5_TX_PIN, \
|
||||
.rx_pin_name = BSP_UART5_RX_PIN, \
|
||||
}
|
||||
#endif /* UART5_CONFIG */
|
||||
|
||||
#if defined(BSP_UART5_RX_USING_DMA)
|
||||
#ifndef UART5_DMA_RX_CONFIG
|
||||
#define UART5_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART5_RX_DMA_INSTANCE, \
|
||||
.dma_rcc = UART5_RX_DMA_RCC, \
|
||||
.dma_irq = UART5_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART5_DMA_RX_CONFIG */
|
||||
#endif /* BSP_UART5_RX_USING_DMA */
|
||||
|
||||
#if defined(BSP_UART5_TX_USING_DMA)
|
||||
#ifndef UART5_DMA_TX_CONFIG
|
||||
#define UART5_DMA_TX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART5_TX_DMA_INSTANCE, \
|
||||
.dma_rcc = UART5_TX_DMA_RCC, \
|
||||
.dma_irq = UART5_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* UART5_DMA_TX_CONFIG */
|
||||
#endif /* BSP_UART5_TX_USING_DMA */
|
||||
#endif /* BSP_USING_UART5 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
27
drivers/include/config/usbd_config.h
Normal file
27
drivers/include/config/usbd_config.h
Normal file
@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-04-10 ZYH first version
|
||||
* 2019-07-29 Chinese66 change from f4 to f1
|
||||
*/
|
||||
#ifndef __USBD_CONFIG_H__
|
||||
#define __USBD_CONFIG_H__
|
||||
|
||||
#define USBD_IRQ_TYPE USB_LP_CAN1_RX0_IRQn
|
||||
#define USBD_IRQ_HANDLER USB_LP_CAN1_RX0_IRQHandler
|
||||
#define USBD_INSTANCE USB
|
||||
#define USBD_PCD_SPEED PCD_SPEED_FULL
|
||||
#define USBD_PCD_PHY_MODULE PCD_PHY_EMBEDDED
|
||||
|
||||
#ifndef BSP_USB_CONNECT_PIN
|
||||
#define BSP_USB_CONNECT_PIN -1
|
||||
#endif
|
||||
|
||||
#ifndef BSP_USB_PULL_UP_STATUS
|
||||
#define BSP_USB_PULL_UP_STATUS 1
|
||||
#endif
|
||||
#endif
|
||||
58
drivers/include/drv_common.h
Normal file
58
drivers/include/drv_common.h
Normal file
@ -0,0 +1,58 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-7 SummerGift first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_COMMON_H__
|
||||
#define __DRV_COMMON_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
#include <board.h>
|
||||
#include <stm32f1xx.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
void _Error_Handler(char *s, int num);
|
||||
|
||||
#ifndef Error_Handler
|
||||
#define Error_Handler() _Error_Handler(__FILE__, __LINE__)
|
||||
#endif
|
||||
|
||||
#define DMA_NOT_AVAILABLE ((DMA_INSTANCE_TYPE *)0xFFFFFFFFU)
|
||||
|
||||
#define __STM32_PORT(port) GPIO##port##_BASE
|
||||
#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__STM32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x0400UL) )) + PIN)
|
||||
#define STM32_FLASH_START_ADRESS ROM_START
|
||||
#define STM32_FLASH_SIZE ROM_SIZE
|
||||
#define STM32_FLASH_END_ADDRESS ROM_END
|
||||
|
||||
#define STM32_SRAM1_SIZE RAM_SIZE
|
||||
#define STM32_SRAM1_START RAM_START
|
||||
#define STM32_SRAM1_END RAM_END
|
||||
|
||||
#if defined(__CC_ARM) || defined(__CLANG_ARM)
|
||||
extern int Image$RW_IRAM1$ZI$Limit;
|
||||
#define HEAP_BEGIN ((void *)&Image$RW_IRAM1$ZI$Limit)
|
||||
#elif __ICCARM__
|
||||
#pragma section="CSTACK"
|
||||
#define HEAP_BEGIN (__segment_end("CSTACK"))
|
||||
#else
|
||||
extern int __bss_end;
|
||||
#define HEAP_BEGIN ((void *)&__bss_end)
|
||||
#endif
|
||||
|
||||
#define HEAP_END STM32_SRAM1_END
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
122
drivers/include/drv_config.h
Normal file
122
drivers/include/drv_config.h
Normal file
@ -0,0 +1,122 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-10-30 SummerGift first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_CONFIG_H__
|
||||
#define __DRV_CONFIG_H__
|
||||
|
||||
#include <board.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(SOC_SERIES_STM32F0)
|
||||
#include "config/dma_config.h"
|
||||
#include "config/uart_config.h"
|
||||
#include "config/spi_config.h"
|
||||
#include "config/tim_config.h"
|
||||
#include "config/pwm_config.h"
|
||||
#include "config/adc_config.h"
|
||||
#elif defined(SOC_SERIES_STM32F1)
|
||||
#include "config/dma_config.h"
|
||||
#include "config/uart_config.h"
|
||||
#include "config/spi_config.h"
|
||||
#include "config/adc_config.h"
|
||||
#include "config/tim_config.h"
|
||||
#include "config/sdio_config.h"
|
||||
#include "config/pwm_config.h"
|
||||
#include "config/usbd_config.h"
|
||||
#include "config/pulse_encoder_config.h"
|
||||
#elif defined(SOC_SERIES_STM32F2)
|
||||
#include "config/dma_config.h"
|
||||
#include "config/uart_config.h"
|
||||
#include "config/spi_config.h"
|
||||
#include "config/adc_config.h"
|
||||
#include "config/tim_config.h"
|
||||
#include "config/sdio_config.h"
|
||||
#include "config/pwm_config.h"
|
||||
#elif defined(SOC_SERIES_STM32F4)
|
||||
#include "config/dma_config.h"
|
||||
#include "config/uart_config.h"
|
||||
#include "config/spi_config.h"
|
||||
#include "config/qspi_config.h"
|
||||
#include "config/usbd_config.h"
|
||||
#include "config/adc_config.h"
|
||||
#include "config/tim_config.h"
|
||||
#include "config/sdio_config.h"
|
||||
#include "config/pwm_config.h"
|
||||
#include "config/pulse_encoder_config.h"
|
||||
#elif defined(SOC_SERIES_STM32F7)
|
||||
#include "config/dma_config.h"
|
||||
#include "config/uart_config.h"
|
||||
#include "config/spi_config.h"
|
||||
#include "config/qspi_config.h"
|
||||
#include "config/adc_config.h"
|
||||
#include "config/tim_config.h"
|
||||
#include "config/sdio_config.h"
|
||||
#include "config/pwm_config.h"
|
||||
#elif defined(SOC_SERIES_STM32L0)
|
||||
#include "config/dma_config.h"
|
||||
#include "config/uart_config.h"
|
||||
#elif defined(SOC_SERIES_STM32L1)
|
||||
#include "config/dma_config.h"
|
||||
#include "config/uart_config.h"
|
||||
#include "config/spi_config.h"
|
||||
#include "config/adc_config.h"
|
||||
#include "config/tim_config.h"
|
||||
#include "config/sdio_config.h"
|
||||
#include "config/pwm_config.h"
|
||||
#include "config/usbd_config.h"
|
||||
#elif defined(SOC_SERIES_STM32L4)
|
||||
#include "config/dma_config.h"
|
||||
#include "config/uart_config.h"
|
||||
#include "config/spi_config.h"
|
||||
#include "config/qspi_config.h"
|
||||
#include "config/adc_config.h"
|
||||
#include "config/tim_config.h"
|
||||
#include "config/sdio_config.h"
|
||||
#include "config/pwm_config.h"
|
||||
#include "config/usbd_config.h"
|
||||
#elif defined(SOC_SERIES_STM32G0)
|
||||
#include "config/dma_config.h"
|
||||
#include "config/uart_config.h"
|
||||
#include "config/spi_config.h"
|
||||
#include "config/adc_config.h"
|
||||
#include "config/tim_config.h"
|
||||
#include "config/pwm_config.h"
|
||||
#elif defined(SOC_SERIES_STM32G4)
|
||||
#include "config/dma_config.h"
|
||||
#include "config/uart_config.h"
|
||||
#include "config/spi_config.h"
|
||||
#include "config/qspi_config.h"
|
||||
#include "config/usbd_config.h"
|
||||
#include "config/adc_config.h"
|
||||
#include "config/tim_config.h"
|
||||
#include "config/sdio_config.h"
|
||||
#include "config/pwm_config.h"
|
||||
#include "config/pulse_encoder_config.h"
|
||||
#elif defined(SOC_SERIES_STM32H7)
|
||||
#include "config/dma_config.h"
|
||||
#include "config/uart_config.h"
|
||||
#include "config/spi_config.h"
|
||||
#include "config/qspi_config.h"
|
||||
#include "config/adc_config.h"
|
||||
#include "config/tim_config.h"
|
||||
#include "config/sdio_config.h"
|
||||
#include "config/pwm_config.h"
|
||||
#include "config/usbd_config.h"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
47
drivers/include/drv_dma.h
Normal file
47
drivers/include/drv_dma.h
Normal file
@ -0,0 +1,47 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-10 SummerGift first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_DMA_H_
|
||||
#define __DRV_DMA_H_
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <board.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L0) \
|
||||
||defined(SOC_SERIES_STM32L1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)
|
||||
#define DMA_INSTANCE_TYPE DMA_Channel_TypeDef
|
||||
#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)\
|
||||
|| defined(SOC_SERIES_STM32H7)
|
||||
#define DMA_INSTANCE_TYPE DMA_Stream_TypeDef
|
||||
#endif /* defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) */
|
||||
|
||||
struct dma_config {
|
||||
DMA_INSTANCE_TYPE *Instance;
|
||||
rt_uint32_t dma_rcc;
|
||||
IRQn_Type dma_irq;
|
||||
|
||||
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
|
||||
rt_uint32_t channel;
|
||||
#endif
|
||||
|
||||
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)
|
||||
rt_uint32_t request;
|
||||
#endif
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__DRV_DMA_H_ */
|
||||
92
drivers/include/drv_eth.h
Normal file
92
drivers/include/drv_eth.h
Normal file
@ -0,0 +1,92 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-25 zylx first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_ETH_H__
|
||||
#define __DRV_ETH_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
#include <rtdevice.h>
|
||||
#include <board.h>
|
||||
|
||||
/* The PHY basic control register */
|
||||
#define PHY_BASIC_CONTROL_REG 0x00U
|
||||
#define PHY_RESET_MASK (1<<15)
|
||||
#define PHY_AUTO_NEGOTIATION_MASK (1<<12)
|
||||
|
||||
/* The PHY basic status register */
|
||||
#define PHY_BASIC_STATUS_REG 0x01U
|
||||
#define PHY_LINKED_STATUS_MASK (1<<2)
|
||||
#define PHY_AUTONEGO_COMPLETE_MASK (1<<5)
|
||||
|
||||
/* The PHY ID one register */
|
||||
#define PHY_ID1_REG 0x02U
|
||||
|
||||
/* The PHY ID two register */
|
||||
#define PHY_ID2_REG 0x03U
|
||||
|
||||
/* The PHY auto-negotiate advertise register */
|
||||
#define PHY_AUTONEG_ADVERTISE_REG 0x04U
|
||||
|
||||
#ifdef PHY_USING_LAN8720A
|
||||
/* The PHY interrupt source flag register. */
|
||||
#define PHY_INTERRUPT_FLAG_REG 0x1DU
|
||||
/* The PHY interrupt mask register. */
|
||||
#define PHY_INTERRUPT_MASK_REG 0x1EU
|
||||
#define PHY_LINK_DOWN_MASK (1<<4)
|
||||
#define PHY_AUTO_NEGO_COMPLETE_MASK (1<<6)
|
||||
|
||||
/* The PHY status register. */
|
||||
#define PHY_Status_REG 0x1FU
|
||||
#define PHY_10M_MASK (1<<2)
|
||||
#define PHY_100M_MASK (1<<3)
|
||||
#define PHY_FULL_DUPLEX_MASK (1<<4)
|
||||
#define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK)
|
||||
#define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK)
|
||||
#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK)
|
||||
#endif /* PHY_USING_LAN8720A */
|
||||
|
||||
#ifdef PHY_USING_DM9161CEP
|
||||
#define PHY_Status_REG 0x11U
|
||||
#define PHY_10M_MASK ((1<<12) || (1<<13))
|
||||
#define PHY_100M_MASK ((1<<14) || (1<<15))
|
||||
#define PHY_FULL_DUPLEX_MASK ((1<<15) || (1<<13))
|
||||
#define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK)
|
||||
#define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK)
|
||||
#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK)
|
||||
/* The PHY interrupt source flag register. */
|
||||
#define PHY_INTERRUPT_FLAG_REG 0x15U
|
||||
/* The PHY interrupt mask register. */
|
||||
#define PHY_INTERRUPT_MASK_REG 0x15U
|
||||
#define PHY_LINK_CHANGE_FLAG (1<<2)
|
||||
#define PHY_LINK_CHANGE_MASK (1<<9)
|
||||
#define PHY_INT_MASK 0
|
||||
|
||||
#endif /* PHY_USING_DM9161CEP */
|
||||
|
||||
#ifdef PHY_USING_DP83848C
|
||||
#define PHY_Status_REG 0x10U
|
||||
#define PHY_10M_MASK (1<<1)
|
||||
#define PHY_FULL_DUPLEX_MASK (1<<2)
|
||||
#define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK)
|
||||
#define PHY_Status_SPEED_100M(sr) (!PHY_Status_SPEED_10M(sr))
|
||||
#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK)
|
||||
/* The PHY interrupt source flag register. */
|
||||
#define PHY_INTERRUPT_FLAG_REG 0x12U
|
||||
#define PHY_LINK_CHANGE_FLAG (1<<13)
|
||||
/* The PHY interrupt control register. */
|
||||
#define PHY_INTERRUPT_CTRL_REG 0x11U
|
||||
#define PHY_INTERRUPT_EN ((1<<0)|(1<<1))
|
||||
/* The PHY interrupt mask register. */
|
||||
#define PHY_INTERRUPT_MASK_REG 0x12U
|
||||
#define PHY_INT_MASK (1<<5)
|
||||
#endif /* PHY_USING_DP83848C */
|
||||
|
||||
#endif /* __DRV_ETH_H__ */
|
||||
31
drivers/include/drv_flash.h
Normal file
31
drivers/include/drv_flash.h
Normal file
@ -0,0 +1,31 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-5 SummerGift first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_FLASH_H__
|
||||
#define __DRV_FLASH_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "rtdevice.h"
|
||||
#include <rthw.h>
|
||||
#include <drv_common.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
int stm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size);
|
||||
int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size);
|
||||
int stm32_flash_erase(rt_uint32_t addr, size_t size);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DRV_FLASH_H__ */
|
||||
27
drivers/include/drv_log.h
Normal file
27
drivers/include/drv_log.h
Normal file
@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-15 SummerGift first version
|
||||
*/
|
||||
|
||||
/*
|
||||
* NOTE: DO NOT include this file on the header file.
|
||||
*/
|
||||
|
||||
#ifndef LOG_TAG
|
||||
#define DBG_TAG "drv"
|
||||
#else
|
||||
#define DBG_TAG LOG_TAG
|
||||
#endif /* LOG_TAG */
|
||||
|
||||
#ifdef DRV_DEBUG
|
||||
#define DBG_LVL DBG_LOG
|
||||
#else
|
||||
#define DBG_LVL DBG_INFO
|
||||
#endif /* DRV_DEBUG */
|
||||
|
||||
#include <rtdbg.h>
|
||||
17
drivers/include/drv_qspi.h
Normal file
17
drivers/include/drv_qspi.h
Normal file
@ -0,0 +1,17 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-27 zylx first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_QSPI_H_
|
||||
#define __DRV_QSPI_H_
|
||||
#include <rtthread.h>
|
||||
|
||||
rt_err_t stm32_qspi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin, rt_uint8_t data_line_width, void (*enter_qspi_mode)(), void (*exit_qspi_mode)());
|
||||
|
||||
#endif
|
||||
200
drivers/include/drv_sdio.h
Normal file
200
drivers/include/drv_sdio.h
Normal file
@ -0,0 +1,200 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-12-13 BalanceTWK first version
|
||||
* 2019-06-11 WillianChan Add SD card hot plug detection
|
||||
*/
|
||||
|
||||
#ifndef _DRV_SDIO_H
|
||||
#define _DRV_SDIO_H
|
||||
#include <rtthread.h>
|
||||
#include "rtdevice.h"
|
||||
#include <rthw.h>
|
||||
#include <drv_common.h>
|
||||
#include "drv_dma.h"
|
||||
#include <string.h>
|
||||
#include <drivers/mmcsd_core.h>
|
||||
#include <drivers/sdio.h>
|
||||
|
||||
#ifdef BSP_USING_SDIO
|
||||
|
||||
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4)
|
||||
#define SDCARD_INSTANCE_TYPE SDIO_TypeDef
|
||||
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7)
|
||||
#define SDCARD_INSTANCE_TYPE SDMMC_TypeDef
|
||||
#endif /* defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F4) */
|
||||
|
||||
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4)
|
||||
#define SDCARD_INSTANCE SDIO
|
||||
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7)
|
||||
#define SDCARD_INSTANCE SDMMC1
|
||||
#endif /* defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F4) */
|
||||
|
||||
#define SDIO_BUFF_SIZE 4096
|
||||
#define SDIO_ALIGN_LEN 32
|
||||
|
||||
#ifndef SDIO_MAX_FREQ
|
||||
#define SDIO_MAX_FREQ (1000000)
|
||||
#endif
|
||||
|
||||
#ifndef SDIO_BASE_ADDRESS
|
||||
#define SDIO_BASE_ADDRESS (0x40012800U)
|
||||
#endif
|
||||
|
||||
#ifndef SDIO_CLOCK_FREQ
|
||||
#define SDIO_CLOCK_FREQ (48U * 1000 * 1000)
|
||||
#endif
|
||||
|
||||
#ifndef SDIO_BUFF_SIZE
|
||||
#define SDIO_BUFF_SIZE (4096)
|
||||
#endif
|
||||
|
||||
#ifndef SDIO_ALIGN_LEN
|
||||
#define SDIO_ALIGN_LEN (32)
|
||||
#endif
|
||||
|
||||
#ifndef SDIO_MAX_FREQ
|
||||
#define SDIO_MAX_FREQ (24 * 1000 * 1000)
|
||||
#endif
|
||||
|
||||
#define HW_SDIO_IT_CCRCFAIL (0x01U << 0)
|
||||
#define HW_SDIO_IT_DCRCFAIL (0x01U << 1)
|
||||
#define HW_SDIO_IT_CTIMEOUT (0x01U << 2)
|
||||
#define HW_SDIO_IT_DTIMEOUT (0x01U << 3)
|
||||
#define HW_SDIO_IT_TXUNDERR (0x01U << 4)
|
||||
#define HW_SDIO_IT_RXOVERR (0x01U << 5)
|
||||
#define HW_SDIO_IT_CMDREND (0x01U << 6)
|
||||
#define HW_SDIO_IT_CMDSENT (0x01U << 7)
|
||||
#define HW_SDIO_IT_DATAEND (0x01U << 8)
|
||||
#define HW_SDIO_IT_STBITERR (0x01U << 9)
|
||||
#define HW_SDIO_IT_DBCKEND (0x01U << 10)
|
||||
#define HW_SDIO_IT_CMDACT (0x01U << 11)
|
||||
#define HW_SDIO_IT_TXACT (0x01U << 12)
|
||||
#define HW_SDIO_IT_RXACT (0x01U << 13)
|
||||
#define HW_SDIO_IT_TXFIFOHE (0x01U << 14)
|
||||
#define HW_SDIO_IT_RXFIFOHF (0x01U << 15)
|
||||
#define HW_SDIO_IT_TXFIFOF (0x01U << 16)
|
||||
#define HW_SDIO_IT_RXFIFOF (0x01U << 17)
|
||||
#define HW_SDIO_IT_TXFIFOE (0x01U << 18)
|
||||
#define HW_SDIO_IT_RXFIFOE (0x01U << 19)
|
||||
#define HW_SDIO_IT_TXDAVL (0x01U << 20)
|
||||
#define HW_SDIO_IT_RXDAVL (0x01U << 21)
|
||||
#define HW_SDIO_IT_SDIOIT (0x01U << 22)
|
||||
|
||||
#define HW_SDIO_ERRORS \
|
||||
(HW_SDIO_IT_CCRCFAIL | HW_SDIO_IT_CTIMEOUT | \
|
||||
HW_SDIO_IT_DCRCFAIL | HW_SDIO_IT_DTIMEOUT | \
|
||||
HW_SDIO_IT_RXOVERR | HW_SDIO_IT_TXUNDERR)
|
||||
|
||||
#define HW_SDIO_POWER_OFF (0x00U)
|
||||
#define HW_SDIO_POWER_UP (0x02U)
|
||||
#define HW_SDIO_POWER_ON (0x03U)
|
||||
|
||||
#define HW_SDIO_FLOW_ENABLE (0x01U << 14)
|
||||
#define HW_SDIO_BUSWIDE_1B (0x00U << 11)
|
||||
#define HW_SDIO_BUSWIDE_4B (0x01U << 11)
|
||||
#define HW_SDIO_BUSWIDE_8B (0x02U << 11)
|
||||
#define HW_SDIO_BYPASS_ENABLE (0x01U << 10)
|
||||
#define HW_SDIO_IDLE_ENABLE (0x01U << 9)
|
||||
#define HW_SDIO_CLK_ENABLE (0x01U << 8)
|
||||
|
||||
#define HW_SDIO_SUSPEND_CMD (0x01U << 11)
|
||||
#define HW_SDIO_CPSM_ENABLE (0x01U << 10)
|
||||
#define HW_SDIO_WAIT_END (0x01U << 9)
|
||||
#define HW_SDIO_WAIT_INT (0x01U << 8)
|
||||
#define HW_SDIO_RESPONSE_NO (0x00U << 6)
|
||||
#define HW_SDIO_RESPONSE_SHORT (0x01U << 6)
|
||||
#define HW_SDIO_RESPONSE_LONG (0x03U << 6)
|
||||
|
||||
#define HW_SDIO_DATA_LEN_MASK (0x01FFFFFFU)
|
||||
|
||||
#define HW_SDIO_IO_ENABLE (0x01U << 11)
|
||||
#define HW_SDIO_RWMOD_CK (0x01U << 10)
|
||||
#define HW_SDIO_RWSTOP_ENABLE (0x01U << 9)
|
||||
#define HW_SDIO_RWSTART_ENABLE (0x01U << 8)
|
||||
#define HW_SDIO_DBLOCKSIZE_1 (0x00U << 4)
|
||||
#define HW_SDIO_DBLOCKSIZE_2 (0x01U << 4)
|
||||
#define HW_SDIO_DBLOCKSIZE_4 (0x02U << 4)
|
||||
#define HW_SDIO_DBLOCKSIZE_8 (0x03U << 4)
|
||||
#define HW_SDIO_DBLOCKSIZE_16 (0x04U << 4)
|
||||
#define HW_SDIO_DBLOCKSIZE_32 (0x05U << 4)
|
||||
#define HW_SDIO_DBLOCKSIZE_64 (0x06U << 4)
|
||||
#define HW_SDIO_DBLOCKSIZE_128 (0x07U << 4)
|
||||
#define HW_SDIO_DBLOCKSIZE_256 (0x08U << 4)
|
||||
#define HW_SDIO_DBLOCKSIZE_512 (0x09U << 4)
|
||||
#define HW_SDIO_DBLOCKSIZE_1024 (0x0AU << 4)
|
||||
#define HW_SDIO_DBLOCKSIZE_2048 (0x0BU << 4)
|
||||
#define HW_SDIO_DBLOCKSIZE_4096 (0x0CU << 4)
|
||||
#define HW_SDIO_DBLOCKSIZE_8192 (0x0DU << 4)
|
||||
#define HW_SDIO_DBLOCKSIZE_16384 (0x0EU << 4)
|
||||
#define HW_SDIO_DMA_ENABLE (0x01U << 3)
|
||||
#define HW_SDIO_STREAM_ENABLE (0x01U << 2)
|
||||
#define HW_SDIO_TO_HOST (0x01U << 1)
|
||||
#define HW_SDIO_DPSM_ENABLE (0x01U << 0)
|
||||
|
||||
#define HW_SDIO_DATATIMEOUT (0xF0000000U)
|
||||
|
||||
struct stm32_sdio
|
||||
{
|
||||
volatile rt_uint32_t power;
|
||||
volatile rt_uint32_t clkcr;
|
||||
volatile rt_uint32_t arg;
|
||||
volatile rt_uint32_t cmd;
|
||||
volatile rt_uint32_t respcmd;
|
||||
volatile rt_uint32_t resp1;
|
||||
volatile rt_uint32_t resp2;
|
||||
volatile rt_uint32_t resp3;
|
||||
volatile rt_uint32_t resp4;
|
||||
volatile rt_uint32_t dtimer;
|
||||
volatile rt_uint32_t dlen;
|
||||
volatile rt_uint32_t dctrl;
|
||||
volatile rt_uint32_t dcount;
|
||||
volatile rt_uint32_t sta;
|
||||
volatile rt_uint32_t icr;
|
||||
volatile rt_uint32_t mask;
|
||||
volatile rt_uint32_t reserved0[2];
|
||||
volatile rt_uint32_t fifocnt;
|
||||
volatile rt_uint32_t reserved1[13];
|
||||
volatile rt_uint32_t fifo;
|
||||
};
|
||||
|
||||
typedef rt_err_t (*dma_txconfig)(rt_uint32_t *src, rt_uint32_t *dst, int size);
|
||||
typedef rt_err_t (*dma_rxconfig)(rt_uint32_t *src, rt_uint32_t *dst, int size);
|
||||
typedef rt_uint32_t (*sdio_clk_get)(struct stm32_sdio *hw_sdio);
|
||||
|
||||
struct stm32_sdio_des
|
||||
{
|
||||
struct stm32_sdio *hw_sdio;
|
||||
dma_txconfig txconfig;
|
||||
dma_rxconfig rxconfig;
|
||||
sdio_clk_get clk_get;
|
||||
};
|
||||
|
||||
struct stm32_sdio_config
|
||||
{
|
||||
SDCARD_INSTANCE_TYPE *Instance;
|
||||
struct dma_config dma_rx, dma_tx;
|
||||
};
|
||||
|
||||
/* stm32 sdio dirver class */
|
||||
struct stm32_sdio_class
|
||||
{
|
||||
struct stm32_sdio_des *des;
|
||||
const struct stm32_sdio_config *cfg;
|
||||
struct rt_mmcsd_host host;
|
||||
struct
|
||||
{
|
||||
DMA_HandleTypeDef handle_rx;
|
||||
DMA_HandleTypeDef handle_tx;
|
||||
} dma;
|
||||
};
|
||||
|
||||
extern void stm32_mmcsd_change(void);
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* BSP_USING_SDIO */
|
||||
73
drivers/include/drv_soft_i2c.h
Normal file
73
drivers/include/drv_soft_i2c.h
Normal file
@ -0,0 +1,73 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-08 balanceTWK first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_I2C__
|
||||
#define __DRV_I2C__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
#ifdef RT_USING_I2C
|
||||
|
||||
/* stm32 config class */
|
||||
struct stm32_soft_i2c_config
|
||||
{
|
||||
rt_uint8_t scl;
|
||||
rt_uint8_t sda;
|
||||
const char *bus_name;
|
||||
};
|
||||
/* stm32 i2c dirver class */
|
||||
struct stm32_i2c
|
||||
{
|
||||
struct rt_i2c_bit_ops ops;
|
||||
struct rt_i2c_bus_device i2c2_bus;
|
||||
};
|
||||
|
||||
#ifdef BSP_USING_I2C1
|
||||
#define I2C1_BUS_CONFIG \
|
||||
{ \
|
||||
.scl = BSP_I2C1_SCL_PIN, \
|
||||
.sda = BSP_I2C1_SDA_PIN, \
|
||||
.bus_name = "i2c1", \
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_I2C2
|
||||
#define I2C2_BUS_CONFIG \
|
||||
{ \
|
||||
.scl = BSP_I2C2_SCL_PIN, \
|
||||
.sda = BSP_I2C2_SDA_PIN, \
|
||||
.bus_name = "i2c2", \
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_I2C3
|
||||
#define I2C3_BUS_CONFIG \
|
||||
{ \
|
||||
.scl = BSP_I2C3_SCL_PIN, \
|
||||
.sda = BSP_I2C3_SDA_PIN, \
|
||||
.bus_name = "i2c3", \
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_I2C4
|
||||
#define I2C4_BUS_CONFIG \
|
||||
{ \
|
||||
.scl = BSP_I2C4_SCL_PIN, \
|
||||
.sda = BSP_I2C4_SDA_PIN, \
|
||||
.bus_name = "i2c4", \
|
||||
}
|
||||
#endif
|
||||
int rt_hw_i2c_init(void);
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* RT_USING_I2C */
|
||||
62
drivers/include/drv_spi.h
Normal file
62
drivers/include/drv_spi.h
Normal file
@ -0,0 +1,62 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-5 SummerGift first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_SPI_H_
|
||||
#define __DRV_SPI_H_
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "rtdevice.h"
|
||||
#include <rthw.h>
|
||||
#include <drv_common.h>
|
||||
#include "drv_dma.h"
|
||||
|
||||
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef* cs_gpiox, uint16_t cs_gpio_pin);
|
||||
|
||||
struct stm32_hw_spi_cs
|
||||
{
|
||||
GPIO_TypeDef* GPIOx;
|
||||
uint16_t GPIO_Pin;
|
||||
};
|
||||
|
||||
struct stm32_spi_config
|
||||
{
|
||||
SPI_TypeDef *Instance;
|
||||
char *bus_name;
|
||||
struct dma_config *dma_rx, *dma_tx;
|
||||
};
|
||||
|
||||
struct stm32_spi_device
|
||||
{
|
||||
rt_uint32_t pin;
|
||||
char *bus_name;
|
||||
char *device_name;
|
||||
};
|
||||
|
||||
#define SPI_USING_RX_DMA_FLAG (1<<0)
|
||||
#define SPI_USING_TX_DMA_FLAG (1<<1)
|
||||
|
||||
/* stm32 spi dirver class */
|
||||
struct stm32_spi
|
||||
{
|
||||
SPI_HandleTypeDef handle;
|
||||
struct stm32_spi_config *config;
|
||||
struct rt_spi_configuration *cfg;
|
||||
|
||||
struct
|
||||
{
|
||||
DMA_HandleTypeDef handle_rx;
|
||||
DMA_HandleTypeDef handle_tx;
|
||||
} dma;
|
||||
|
||||
rt_uint8_t spi_dma_flag;
|
||||
struct rt_spi_bus spi_bus;
|
||||
};
|
||||
|
||||
#endif /*__DRV_SPI_H_ */
|
||||
21
drivers/include/drv_usbh.h
Normal file
21
drivers/include/drv_usbh.h
Normal file
@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2018, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2017-12-12 ZYH the first version
|
||||
* 2019-12-19 tyustli port to stm32 series
|
||||
*/
|
||||
#ifndef __DRV_USBH_H__
|
||||
#define __DRV_USBH_H__
|
||||
#include <rtthread.h>
|
||||
|
||||
#define OTG_FS_PORT 1
|
||||
|
||||
int stm_usbh_register(void);
|
||||
|
||||
#endif
|
||||
|
||||
/************* end of file ************/
|
||||
370
drivers/stm32f1xx_hal_conf.h
Normal file
370
drivers/stm32f1xx_hal_conf.h
Normal file
@ -0,0 +1,370 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx_hal_conf.h
|
||||
* @brief HAL configuration file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2018 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F1xx_HAL_CONF_H
|
||||
#define __STM32F1xx_HAL_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* ########################## Module Selection ############################## */
|
||||
/**
|
||||
* @brief This is the list of modules to be used in the HAL driver
|
||||
*/
|
||||
|
||||
#define HAL_MODULE_ENABLED
|
||||
#define HAL_ADC_MODULE_ENABLED
|
||||
/*#define HAL_CRYP_MODULE_ENABLED */
|
||||
/*#define HAL_CAN_MODULE_ENABLED */
|
||||
/*#define HAL_CEC_MODULE_ENABLED */
|
||||
/*#define HAL_CORTEX_MODULE_ENABLED */
|
||||
/*#define HAL_CRC_MODULE_ENABLED */
|
||||
/*#define HAL_DAC_MODULE_ENABLED */
|
||||
#define HAL_DMA_MODULE_ENABLED
|
||||
/*#define HAL_ETH_MODULE_ENABLED */
|
||||
/*#define HAL_FLASH_MODULE_ENABLED */
|
||||
#define HAL_GPIO_MODULE_ENABLED
|
||||
#define HAL_I2C_MODULE_ENABLED
|
||||
/*#define HAL_I2S_MODULE_ENABLED */
|
||||
/*#define HAL_IRDA_MODULE_ENABLED */
|
||||
/*#define HAL_IWDG_MODULE_ENABLED */
|
||||
/*#define HAL_NOR_MODULE_ENABLED */
|
||||
/*#define HAL_NAND_MODULE_ENABLED */
|
||||
/*#define HAL_PCCARD_MODULE_ENABLED */
|
||||
/*#define HAL_PCD_MODULE_ENABLED */
|
||||
/*#define HAL_HCD_MODULE_ENABLED */
|
||||
/*#define HAL_PWR_MODULE_ENABLED */
|
||||
/*#define HAL_RCC_MODULE_ENABLED */
|
||||
/*#define HAL_RTC_MODULE_ENABLED */
|
||||
/*#define HAL_SD_MODULE_ENABLED */
|
||||
/*#define HAL_MMC_MODULE_ENABLED */
|
||||
/*#define HAL_SDRAM_MODULE_ENABLED */
|
||||
/*#define HAL_SMARTCARD_MODULE_ENABLED */
|
||||
#define HAL_SPI_MODULE_ENABLED
|
||||
/*#define HAL_SRAM_MODULE_ENABLED */
|
||||
#define HAL_TIM_MODULE_ENABLED
|
||||
#define HAL_UART_MODULE_ENABLED
|
||||
/*#define HAL_USART_MODULE_ENABLED */
|
||||
/*#define HAL_WWDG_MODULE_ENABLED */
|
||||
#define HAL_EXTI_MODULE_ENABLED */
|
||||
|
||||
#define HAL_CORTEX_MODULE_ENABLED
|
||||
#define HAL_DMA_MODULE_ENABLED
|
||||
#define HAL_FLASH_MODULE_ENABLED
|
||||
#define HAL_GPIO_MODULE_ENABLED
|
||||
#define HAL_PWR_MODULE_ENABLED
|
||||
#define HAL_RCC_MODULE_ENABLED
|
||||
|
||||
/* ########################## Oscillator Values adaptation ####################*/
|
||||
/**
|
||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSE is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (HSE_STARTUP_TIMEOUT)
|
||||
#define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */
|
||||
#endif /* HSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI) value.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSI is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal Low Speed oscillator (LSI) value.
|
||||
*/
|
||||
#if !defined (LSI_VALUE)
|
||||
#define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */
|
||||
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
|
||||
The real value may vary depending on the variations
|
||||
in voltage and temperature. */
|
||||
|
||||
/**
|
||||
* @brief External Low Speed oscillator (LSE) value.
|
||||
* This value is used by the UART, RTC HAL module to compute the system frequency
|
||||
*/
|
||||
#if !defined (LSE_VALUE)
|
||||
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
|
||||
#endif /* LSE_VALUE */
|
||||
|
||||
#if !defined (LSE_STARTUP_TIMEOUT)
|
||||
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
|
||||
#endif /* LSE_STARTUP_TIMEOUT */
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||
=== you can define the HSE value in your toolchain compiler preprocessor. */
|
||||
|
||||
/* ########################### System Configuration ######################### */
|
||||
/**
|
||||
* @brief This is the HAL system configuration section
|
||||
*/
|
||||
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
|
||||
#define TICK_INT_PRIORITY ((uint32_t)0) /*!< tick interrupt priority (lowest by default) */
|
||||
#define USE_RTOS 0
|
||||
#define PREFETCH_ENABLE 1
|
||||
|
||||
/* ########################## Assert Selection ############################## */
|
||||
/**
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* HAL drivers code
|
||||
*/
|
||||
/* #define USE_FULL_ASSERT 1U */
|
||||
|
||||
/* ################## Ethernet peripheral configuration ##################### */
|
||||
|
||||
/* Section 1 : Ethernet peripheral configuration */
|
||||
|
||||
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
|
||||
#define MAC_ADDR0 2
|
||||
#define MAC_ADDR1 0
|
||||
#define MAC_ADDR2 0
|
||||
#define MAC_ADDR3 0
|
||||
#define MAC_ADDR4 0
|
||||
#define MAC_ADDR5 0
|
||||
|
||||
/* Definition of the Ethernet driver buffers size and count */
|
||||
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
|
||||
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
|
||||
#define ETH_RXBUFNB ((uint32_t)8) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
|
||||
#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
|
||||
|
||||
/* Section 2: PHY configuration section */
|
||||
|
||||
/* DP83848_PHY_ADDRESS Address*/
|
||||
#define DP83848_PHY_ADDRESS 0x01U
|
||||
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
|
||||
#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
|
||||
/* PHY Configuration delay */
|
||||
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
|
||||
|
||||
#define PHY_READ_TO ((uint32_t)0x0000FFFF)
|
||||
#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
|
||||
|
||||
/* Section 3: Common PHY Registers */
|
||||
|
||||
#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
|
||||
#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
|
||||
|
||||
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
|
||||
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
|
||||
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
|
||||
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
|
||||
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
|
||||
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
|
||||
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
|
||||
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
|
||||
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
|
||||
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
|
||||
|
||||
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
|
||||
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
|
||||
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
|
||||
|
||||
/* Section 4: Extended PHY Registers */
|
||||
#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */
|
||||
|
||||
#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */
|
||||
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Include module's header file
|
||||
*/
|
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_rcc.h"
|
||||
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_EXTI_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_exti.h"
|
||||
#endif /* HAL_EXTI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_gpio.h"
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_dma.h"
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ETH_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_eth.h"
|
||||
#endif /* HAL_ETH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CAN_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_can.h"
|
||||
#endif /* HAL_CAN_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CEC_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_cec.h"
|
||||
#endif /* HAL_CEC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_cortex.h"
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_adc.h"
|
||||
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_crc.h"
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_dac.h"
|
||||
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_flash.h"
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SRAM_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_sram.h"
|
||||
#endif /* HAL_SRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NOR_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_nor.h"
|
||||
#endif /* HAL_NOR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_i2c.h"
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2S_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_i2s.h"
|
||||
#endif /* HAL_I2S_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_iwdg.h"
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_pwr.h"
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RTC_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_rtc.h"
|
||||
#endif /* HAL_RTC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PCCARD_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_pccard.h"
|
||||
#endif /* HAL_PCCARD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SD_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_sd.h"
|
||||
#endif /* HAL_SD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_MMC_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_mmc.h"
|
||||
#endif /* HAL_MMC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NAND_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_nand.h"
|
||||
#endif /* HAL_NAND_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPI_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_spi.h"
|
||||
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_TIM_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_tim.h"
|
||||
#endif /* HAL_TIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_uart.h"
|
||||
#endif /* HAL_UART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_USART_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_usart.h"
|
||||
#endif /* HAL_USART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IRDA_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_irda.h"
|
||||
#endif /* HAL_IRDA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_smartcard.h"
|
||||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_wwdg.h"
|
||||
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_pcd.h"
|
||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HCD_MODULE_ENABLED
|
||||
#include "stm32f1xx_hal_hcd.h"
|
||||
#endif /* HAL_HCD_MODULE_ENABLED */
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F1xx_HAL_CONF_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
11764
libraries/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h
Normal file
11764
libraries/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h
Normal file
File diff suppressed because it is too large
Load Diff
220
libraries/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h
Normal file
220
libraries/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h
Normal file
@ -0,0 +1,220 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f1xx.h
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS STM32F1xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* The file is the unique include file that the application programmer
|
||||
* is using in the C source code, usually in main.c. This file contains:
|
||||
* - Configuration section that allows to select:
|
||||
* - The STM32F1xx device used in the target application
|
||||
* - To use or not the peripheral’s drivers in application code(i.e.
|
||||
* code will be based on direct access to peripheral’s registers
|
||||
* rather than drivers API), this option is controlled by
|
||||
* "#define USE_HAL_DRIVER"
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f1xx
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __STM32F1XX_H
|
||||
#define __STM32F1XX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @addtogroup Library_configuration_section
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief STM32 Family
|
||||
*/
|
||||
#if !defined (STM32F1)
|
||||
#define STM32F1
|
||||
#endif /* STM32F1 */
|
||||
|
||||
/* Uncomment the line below according to the target STM32L device used in your
|
||||
application
|
||||
*/
|
||||
|
||||
#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \
|
||||
!defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \
|
||||
!defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC)
|
||||
/* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */
|
||||
/* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */
|
||||
/* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */
|
||||
/* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */
|
||||
/* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */
|
||||
/* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */
|
||||
/* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */
|
||||
/* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */
|
||||
/* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */
|
||||
/* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */
|
||||
/* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */
|
||||
/* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */
|
||||
/* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */
|
||||
/* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */
|
||||
#endif
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to switch between these
|
||||
devices, you can define the device in your toolchain compiler preprocessor.
|
||||
*/
|
||||
|
||||
#if !defined (USE_HAL_DRIVER)
|
||||
/**
|
||||
* @brief Comment the line below if you will not use the peripherals drivers.
|
||||
In this case, these drivers will not be included and the application code will
|
||||
be based on direct access to peripherals registers
|
||||
*/
|
||||
/*#define USE_HAL_DRIVER */
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V4.3.1
|
||||
*/
|
||||
#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */
|
||||
#define __STM32F1_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
|
||||
#define __STM32F1_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
|
||||
#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\
|
||||
|(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
|
||||
|(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\
|
||||
|(__STM32F1_CMSIS_VERSION_RC))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Device_Included
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F100xB)
|
||||
#include "stm32f100xb.h"
|
||||
#elif defined(STM32F100xE)
|
||||
#include "stm32f100xe.h"
|
||||
#elif defined(STM32F101x6)
|
||||
#include "stm32f101x6.h"
|
||||
#elif defined(STM32F101xB)
|
||||
#include "stm32f101xb.h"
|
||||
#elif defined(STM32F101xE)
|
||||
#include "stm32f101xe.h"
|
||||
#elif defined(STM32F101xG)
|
||||
#include "stm32f101xg.h"
|
||||
#elif defined(STM32F102x6)
|
||||
#include "stm32f102x6.h"
|
||||
#elif defined(STM32F102xB)
|
||||
#include "stm32f102xb.h"
|
||||
#elif defined(STM32F103x6)
|
||||
#include "stm32f103x6.h"
|
||||
#elif defined(STM32F103xB)
|
||||
#include "stm32f103xb.h"
|
||||
#elif defined(STM32F103xE)
|
||||
#include "stm32f103xe.h"
|
||||
#elif defined(STM32F103xG)
|
||||
#include "stm32f103xg.h"
|
||||
#elif defined(STM32F105xC)
|
||||
#include "stm32f105xc.h"
|
||||
#elif defined(STM32F107xC)
|
||||
#include "stm32f107xc.h"
|
||||
#else
|
||||
#error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Exported_types
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RESET = 0,
|
||||
SET = !RESET
|
||||
} FlagStatus, ITStatus;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
DISABLE = 0,
|
||||
ENABLE = !DISABLE
|
||||
} FunctionalState;
|
||||
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
|
||||
|
||||
typedef enum
|
||||
{
|
||||
SUCCESS = 0U,
|
||||
ERROR = !SUCCESS
|
||||
} ErrorStatus;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup Exported_macros
|
||||
* @{
|
||||
*/
|
||||
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
|
||||
|
||||
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
|
||||
|
||||
#define READ_BIT(REG, BIT) ((REG) & (BIT))
|
||||
|
||||
#define CLEAR_REG(REG) ((REG) = (0x0))
|
||||
|
||||
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
|
||||
|
||||
#define READ_REG(REG) ((REG))
|
||||
|
||||
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
|
||||
|
||||
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (USE_HAL_DRIVER)
|
||||
#include "stm32f1xx_hal.h"
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __STM32F1xx_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,98 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32f10x.h
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f10x_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Define to prevent recursive inclusion
|
||||
*/
|
||||
#ifndef __SYSTEM_STM32F10X_H
|
||||
#define __SYSTEM_STM32F10X_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F10x_System_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup STM32F10x_System_Exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */
|
||||
extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F10x_System_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F10x_System_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F10x_System_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SYSTEM_STM32F10X_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,468 @@
|
||||
/**
|
||||
*************** (C) COPYRIGHT 2017 STMicroelectronics ************************
|
||||
* @file startup_stm32f103xe.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32F103xE Devices vector table for Atollic toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Configure the clock system
|
||||
* - Configure external SRAM mounted on STM3210E-EVAL board
|
||||
* to be used as data memory (optional, to be enabled by user)
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M3 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m3
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
|
||||
.equ BootRAM, 0xF1E0F85F
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
movs r1, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r3, =_sidata
|
||||
ldr r3, [r3, r1]
|
||||
str r3, [r0, r1]
|
||||
adds r1, r1, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
ldr r0, =_sdata
|
||||
ldr r3, =_edata
|
||||
adds r2, r0, r1
|
||||
cmp r2, r3
|
||||
bcc CopyDataInit
|
||||
ldr r2, =_sbss
|
||||
b LoopFillZerobss
|
||||
/* Zero fill the bss segment. */
|
||||
FillZerobss:
|
||||
movs r3, #0
|
||||
str r3, [r2], #4
|
||||
|
||||
LoopFillZerobss:
|
||||
ldr r3, = _ebss
|
||||
cmp r2, r3
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
/* bl __libc_init_array */
|
||||
/* Call the application's entry point.*/
|
||||
bl entry
|
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
.word WWDG_IRQHandler
|
||||
.word PVD_IRQHandler
|
||||
.word TAMPER_IRQHandler
|
||||
.word RTC_IRQHandler
|
||||
.word FLASH_IRQHandler
|
||||
.word RCC_IRQHandler
|
||||
.word EXTI0_IRQHandler
|
||||
.word EXTI1_IRQHandler
|
||||
.word EXTI2_IRQHandler
|
||||
.word EXTI3_IRQHandler
|
||||
.word EXTI4_IRQHandler
|
||||
.word DMA1_Channel1_IRQHandler
|
||||
.word DMA1_Channel2_IRQHandler
|
||||
.word DMA1_Channel3_IRQHandler
|
||||
.word DMA1_Channel4_IRQHandler
|
||||
.word DMA1_Channel5_IRQHandler
|
||||
.word DMA1_Channel6_IRQHandler
|
||||
.word DMA1_Channel7_IRQHandler
|
||||
.word ADC1_2_IRQHandler
|
||||
.word USB_HP_CAN1_TX_IRQHandler
|
||||
.word USB_LP_CAN1_RX0_IRQHandler
|
||||
.word CAN1_RX1_IRQHandler
|
||||
.word CAN1_SCE_IRQHandler
|
||||
.word EXTI9_5_IRQHandler
|
||||
.word TIM1_BRK_IRQHandler
|
||||
.word TIM1_UP_IRQHandler
|
||||
.word TIM1_TRG_COM_IRQHandler
|
||||
.word TIM1_CC_IRQHandler
|
||||
.word TIM2_IRQHandler
|
||||
.word TIM3_IRQHandler
|
||||
.word TIM4_IRQHandler
|
||||
.word I2C1_EV_IRQHandler
|
||||
.word I2C1_ER_IRQHandler
|
||||
.word I2C2_EV_IRQHandler
|
||||
.word I2C2_ER_IRQHandler
|
||||
.word SPI1_IRQHandler
|
||||
.word SPI2_IRQHandler
|
||||
.word USART1_IRQHandler
|
||||
.word USART2_IRQHandler
|
||||
.word USART3_IRQHandler
|
||||
.word EXTI15_10_IRQHandler
|
||||
.word RTC_Alarm_IRQHandler
|
||||
.word USBWakeUp_IRQHandler
|
||||
.word TIM8_BRK_IRQHandler
|
||||
.word TIM8_UP_IRQHandler
|
||||
.word TIM8_TRG_COM_IRQHandler
|
||||
.word TIM8_CC_IRQHandler
|
||||
.word ADC3_IRQHandler
|
||||
.word FSMC_IRQHandler
|
||||
.word SDIO_IRQHandler
|
||||
.word TIM5_IRQHandler
|
||||
.word SPI3_IRQHandler
|
||||
.word UART4_IRQHandler
|
||||
.word UART5_IRQHandler
|
||||
.word TIM6_IRQHandler
|
||||
.word TIM7_IRQHandler
|
||||
.word DMA2_Channel1_IRQHandler
|
||||
.word DMA2_Channel2_IRQHandler
|
||||
.word DMA2_Channel3_IRQHandler
|
||||
.word DMA2_Channel4_5_IRQHandler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word BootRAM /* @0x1E0. This is for boot in RAM mode for
|
||||
STM32F10x High Density devices. */
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_IRQHandler
|
||||
.thumb_set PVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMPER_IRQHandler
|
||||
.thumb_set TAMPER_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_IRQHandler
|
||||
.thumb_set RTC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel2_IRQHandler
|
||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel3_IRQHandler
|
||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_IRQHandler
|
||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel5_IRQHandler
|
||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel6_IRQHandler
|
||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel7_IRQHandler
|
||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC1_2_IRQHandler
|
||||
.thumb_set ADC1_2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USB_HP_CAN1_TX_IRQHandler
|
||||
.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak USB_LP_CAN1_RX0_IRQHandler
|
||||
.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX1_IRQHandler
|
||||
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_SCE_IRQHandler
|
||||
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_IRQHandler
|
||||
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBWakeUp_IRQHandler
|
||||
.thumb_set USBWakeUp_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_BRK_IRQHandler
|
||||
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_UP_IRQHandler
|
||||
.thumb_set TIM8_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_TRG_COM_IRQHandler
|
||||
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_CC_IRQHandler
|
||||
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC3_IRQHandler
|
||||
.thumb_set ADC3_IRQHandler,Default_Handler
|
||||
|
||||
.weak FSMC_IRQHandler
|
||||
.thumb_set FSMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDIO_IRQHandler
|
||||
.thumb_set SDIO_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM5_IRQHandler
|
||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_IRQHandler
|
||||
.thumb_set TIM6_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel1_IRQHandler
|
||||
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel2_IRQHandler
|
||||
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel3_IRQHandler
|
||||
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel4_5_IRQHandler
|
||||
.thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@ -0,0 +1,430 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32f1xx.c
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
|
||||
*
|
||||
* 1. This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
|
||||
* factors, AHB/APBx prescalers and Flash settings).
|
||||
* This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32f1xx_xx.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
* 2. After each device reset the HSI (8 MHz) is used as system clock source.
|
||||
* Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
|
||||
* configure the system clock before to branch to main program.
|
||||
*
|
||||
* 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
|
||||
* the product used), refer to "HSE_VALUE".
|
||||
* When HSE is used as system clock source, directly or through PLL, and you
|
||||
* are using different crystal you have to adapt the HSE value to your own
|
||||
* configuration.
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f1xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F1xx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32f1xx.h"
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F1xx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F1xx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE 8000000U /*!< Default value of the External oscillator in Hz.
|
||||
This value can be provided and adapted by the user application. */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE 8000000U /*!< Default value of the Internal oscillator in Hz.
|
||||
This value can be provided and adapted by the user application. */
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/*!< Uncomment the following line if you need to use external SRAM */
|
||||
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
|
||||
/* #define DATA_IN_ExtSRAM */
|
||||
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
|
||||
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F1xx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F1xx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* This variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
uint32_t SystemCoreClock = 16000000;
|
||||
const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
|
||||
#ifdef DATA_IN_ExtSRAM
|
||||
static void SystemInit_ExtMemCtl(void);
|
||||
#endif /* DATA_IN_ExtSRAM */
|
||||
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F1xx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system
|
||||
* Initialize the Embedded Flash Interface, the PLL and update the
|
||||
* SystemCoreClock variable.
|
||||
* @note This function should be used only after reset.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
|
||||
/* Set HSION bit */
|
||||
RCC->CR |= 0x00000001U;
|
||||
|
||||
/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
|
||||
#if !defined(STM32F105xC) && !defined(STM32F107xC)
|
||||
RCC->CFGR &= 0xF8FF0000U;
|
||||
#else
|
||||
RCC->CFGR &= 0xF0FF0000U;
|
||||
#endif /* STM32F105xC */
|
||||
|
||||
/* Reset HSEON, CSSON and PLLON bits */
|
||||
RCC->CR &= 0xFEF6FFFFU;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= 0xFFFBFFFFU;
|
||||
|
||||
/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
|
||||
RCC->CFGR &= 0xFF80FFFFU;
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
/* Reset PLL2ON and PLL3ON bits */
|
||||
RCC->CR &= 0xEBFFFFFFU;
|
||||
|
||||
/* Disable all interrupts and clear pending bits */
|
||||
RCC->CIR = 0x00FF0000U;
|
||||
|
||||
/* Reset CFGR2 register */
|
||||
RCC->CFGR2 = 0x00000000U;
|
||||
#elif defined(STM32F100xB) || defined(STM32F100xE)
|
||||
/* Disable all interrupts and clear pending bits */
|
||||
RCC->CIR = 0x009F0000U;
|
||||
|
||||
/* Reset CFGR2 register */
|
||||
RCC->CFGR2 = 0x00000000U;
|
||||
#else
|
||||
/* Disable all interrupts and clear pending bits */
|
||||
RCC->CIR = 0x009F0000U;
|
||||
#endif /* STM32F105xC */
|
||||
|
||||
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
|
||||
#ifdef DATA_IN_ExtSRAM
|
||||
SystemInit_ExtMemCtl();
|
||||
#endif /* DATA_IN_ExtSRAM */
|
||||
#endif
|
||||
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
|
||||
#else
|
||||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
* or HSI_VALUE(*) multiplied by the PLL factors.
|
||||
*
|
||||
* (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
|
||||
* 8 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
|
||||
* 8 MHz or 25 MHz, depending on the product used), user has to ensure
|
||||
* that HSE_VALUE is same as the real frequency of the crystal used.
|
||||
* Otherwise, this function may have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;
|
||||
|
||||
#if defined(STM32F105xC) || defined(STM32F107xC)
|
||||
uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;
|
||||
#endif /* STM32F105xC */
|
||||
|
||||
#if defined(STM32F100xB) || defined(STM32F100xE)
|
||||
uint32_t prediv1factor = 0U;
|
||||
#endif /* STM32F100xB or STM32F100xE */
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
tmp = RCC->CFGR & RCC_CFGR_SWS;
|
||||
|
||||
switch (tmp)
|
||||
{
|
||||
case 0x00U: /* HSI used as system clock */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
case 0x04U: /* HSE used as system clock */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
case 0x08U: /* PLL used as system clock */
|
||||
|
||||
/* Get PLL clock source and multiplication factor ----------------------*/
|
||||
pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
|
||||
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
|
||||
|
||||
#if !defined(STM32F105xC) && !defined(STM32F107xC)
|
||||
pllmull = ( pllmull >> 18U) + 2U;
|
||||
|
||||
if (pllsource == 0x00U)
|
||||
{
|
||||
/* HSI oscillator clock divided by 2 selected as PLL clock entry */
|
||||
SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
|
||||
}
|
||||
else
|
||||
{
|
||||
#if defined(STM32F100xB) || defined(STM32F100xE)
|
||||
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
|
||||
/* HSE oscillator clock selected as PREDIV1 clock entry */
|
||||
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
|
||||
#else
|
||||
/* HSE selected as PLL clock entry */
|
||||
if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
|
||||
{/* HSE oscillator clock divided by 2 */
|
||||
SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
|
||||
}
|
||||
else
|
||||
{
|
||||
SystemCoreClock = HSE_VALUE * pllmull;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#else
|
||||
pllmull = pllmull >> 18U;
|
||||
|
||||
if (pllmull != 0x0DU)
|
||||
{
|
||||
pllmull += 2U;
|
||||
}
|
||||
else
|
||||
{ /* PLL multiplication factor = PLL input clock * 6.5 */
|
||||
pllmull = 13U / 2U;
|
||||
}
|
||||
|
||||
if (pllsource == 0x00U)
|
||||
{
|
||||
/* HSI oscillator clock divided by 2 selected as PLL clock entry */
|
||||
SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
|
||||
}
|
||||
else
|
||||
{/* PREDIV1 selected as PLL clock entry */
|
||||
|
||||
/* Get PREDIV1 clock source and division factor */
|
||||
prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
|
||||
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
|
||||
|
||||
if (prediv1source == 0U)
|
||||
{
|
||||
/* HSE oscillator clock selected as PREDIV1 clock entry */
|
||||
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
|
||||
}
|
||||
else
|
||||
{/* PLL2 clock selected as PREDIV1 clock entry */
|
||||
|
||||
/* Get PREDIV2 division factor and PLL2 multiplication factor */
|
||||
prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;
|
||||
pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U;
|
||||
SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
|
||||
}
|
||||
}
|
||||
#endif /* STM32F105xC */
|
||||
break;
|
||||
|
||||
default:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Compute HCLK clock frequency ----------------*/
|
||||
/* Get HCLK prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
|
||||
/* HCLK clock frequency */
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
|
||||
/**
|
||||
* @brief Setup the external memory controller. Called in startup_stm32f1xx.s
|
||||
* before jump to __main
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
#ifdef DATA_IN_ExtSRAM
|
||||
/**
|
||||
* @brief Setup the external memory controller.
|
||||
* Called in startup_stm32f1xx_xx.s/.c before jump to main.
|
||||
* This function configures the external SRAM mounted on STM3210E-EVAL
|
||||
* board (STM32 High density devices). This SRAM will be used as program
|
||||
* data memory (including heap and stack).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit_ExtMemCtl(void)
|
||||
{
|
||||
__IO uint32_t tmpreg;
|
||||
/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
|
||||
required, then adjust the Register Addresses */
|
||||
|
||||
/* Enable FSMC clock */
|
||||
RCC->AHBENR = 0x00000114U;
|
||||
|
||||
/* Delay after an RCC peripheral clock enabling */
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
|
||||
|
||||
/* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
|
||||
RCC->APB2ENR = 0x000001E0U;
|
||||
|
||||
/* Delay after an RCC peripheral clock enabling */
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
|
||||
|
||||
(void)(tmpreg);
|
||||
|
||||
/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
|
||||
/*---------------- SRAM Address lines configuration -------------------------*/
|
||||
/*---------------- NOE and NWE configuration --------------------------------*/
|
||||
/*---------------- NE3 configuration ----------------------------------------*/
|
||||
/*---------------- NBL0, NBL1 configuration ---------------------------------*/
|
||||
|
||||
GPIOD->CRL = 0x44BB44BBU;
|
||||
GPIOD->CRH = 0xBBBBBBBBU;
|
||||
|
||||
GPIOE->CRL = 0xB44444BBU;
|
||||
GPIOE->CRH = 0xBBBBBBBBU;
|
||||
|
||||
GPIOF->CRL = 0x44BBBBBBU;
|
||||
GPIOF->CRH = 0xBBBB4444U;
|
||||
|
||||
GPIOG->CRL = 0x44BBBBBBU;
|
||||
GPIOG->CRH = 0x444B4B44U;
|
||||
|
||||
/*---------------- FSMC Configuration ---------------------------------------*/
|
||||
/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
|
||||
|
||||
FSMC_Bank1->BTCR[4U] = 0x00001091U;
|
||||
FSMC_Bank1->BTCR[5U] = 0x00110212U;
|
||||
}
|
||||
#endif /* DATA_IN_ExtSRAM */
|
||||
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
865
libraries/CMSIS/Include/cmsis_armcc.h
Normal file
865
libraries/CMSIS/Include/cmsis_armcc.h
Normal file
@ -0,0 +1,865 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_armcc.h
|
||||
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_ARMCC_H
|
||||
#define __CMSIS_ARMCC_H
|
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
|
||||
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
/* CMSIS compiler control architecture macros */
|
||||
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
|
||||
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#endif
|
||||
|
||||
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#endif
|
||||
|
||||
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#endif
|
||||
|
||||
/* __ARM_ARCH_8M_BASE__ not applicable */
|
||||
/* __ARM_ARCH_8M_MAIN__ not applicable */
|
||||
|
||||
|
||||
/* CMSIS compiler specific defines */
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE __inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static __inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE static __forceinline
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __declspec(noreturn)
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT __packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION __packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Enable IRQ Interrupts
|
||||
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __enable_irq(); */
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable IRQ Interrupts
|
||||
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __disable_irq(); */
|
||||
|
||||
/**
|
||||
\brief Get Control Register
|
||||
\details Returns the content of the Control Register.
|
||||
\return Control Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Control Register
|
||||
\details Writes the given value to the Control Register.
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get IPSR Register
|
||||
\details Returns the content of the IPSR Register.
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get APSR Register
|
||||
\details Returns the content of the APSR Register.
|
||||
\return APSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get xPSR Register
|
||||
\details Returns the content of the xPSR Register.
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Process Stack Pointer
|
||||
\details Returns the current value of the Process Stack Pointer (PSP).
|
||||
\return PSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Process Stack Pointer
|
||||
\details Assigns the given value to the Process Stack Pointer (PSP).
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Main Stack Pointer
|
||||
\details Returns the current value of the Main Stack Pointer (MSP).
|
||||
\return MSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Main Stack Pointer
|
||||
\details Assigns the given value to the Main Stack Pointer (MSP).
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Priority Mask
|
||||
\details Returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Priority Mask
|
||||
\details Assigns the given value to the Priority Mask Register.
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief Enable FIQ
|
||||
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable FIQ
|
||||
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Base Priority
|
||||
\details Returns the current value of the Base Priority register.
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority
|
||||
\details Assigns the given value to the Base Priority register.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority with condition
|
||||
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
||||
or the new value increases the BASEPRI priority level.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePriMax __ASM("basepri_max");
|
||||
__regBasePriMax = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Fault Mask
|
||||
\details Returns the current value of the Fault Mask register.
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Fault Mask
|
||||
\details Assigns the given value to the Fault Mask register.
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & (uint32_t)1U);
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
|
||||
/**
|
||||
\brief Get FPSCR
|
||||
\details Returns the current value of the Floating Point Status/Control register.
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set FPSCR
|
||||
\details Assigns the given value to the Floating Point Status/Control register.
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#else
|
||||
(void)fpscr;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief No Operation
|
||||
\details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Interrupt
|
||||
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Event
|
||||
\details Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/**
|
||||
\brief Send Event
|
||||
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/**
|
||||
\brief Instruction Synchronization Barrier
|
||||
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or memory,
|
||||
after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() do {\
|
||||
__schedule_barrier();\
|
||||
__isb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
\brief Data Synchronization Barrier
|
||||
\details Acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() do {\
|
||||
__schedule_barrier();\
|
||||
__dsb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
\brief Data Memory Barrier
|
||||
\details Ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() do {\
|
||||
__schedule_barrier();\
|
||||
__dmb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (32 bit)
|
||||
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right in unsigned value (32 bit)
|
||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
\param [in] op1 Value to rotate
|
||||
\param [in] op2 Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#define __ROR __ror
|
||||
|
||||
|
||||
/**
|
||||
\brief Breakpoint
|
||||
\details Causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __breakpoint(value)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse bit order of value
|
||||
\details Reverses the bit order of the given value.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
#define __RBIT __rbit
|
||||
#else
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
|
||||
|
||||
result = value; /* r will be reversed bits of v; first get LSB of v */
|
||||
for (value >>= 1U; value != 0U; value >>= 1U)
|
||||
{
|
||||
result <<= 1U;
|
||||
result |= value & 1U;
|
||||
s--;
|
||||
}
|
||||
result <<= s; /* shift when v's highest bits are zero */
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Count leading zeros
|
||||
\details Counts the number of leading zeros of a data value.
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (8 bit)
|
||||
\details Executes a exclusive LDR instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (16 bit)
|
||||
\details Executes a exclusive LDR instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (32 bit)
|
||||
\details Executes a exclusive LDR instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (8 bit)
|
||||
\details Executes a exclusive STR instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (16 bit)
|
||||
\details Executes a exclusive STR instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (32 bit)
|
||||
\details Executes a exclusive STR instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Remove the exclusive lock
|
||||
\details Removes the exclusive lock which is created by LDREX.
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right with Extend (32 bit)
|
||||
\details Moves each bit of a bitstring right by one bit.
|
||||
The carry input is shifted in at the left end of the bitstring.
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
rrx r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRBT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRHT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRT(value, ptr) __strt(value, ptr)
|
||||
|
||||
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if ((sat >= 1U) && (sat <= 32U))
|
||||
{
|
||||
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||
const int32_t min = -1 - max ;
|
||||
if (val > max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < min)
|
||||
{
|
||||
return min;
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if (sat <= 31U)
|
||||
{
|
||||
const uint32_t max = ((1U << sat) - 1U);
|
||||
if (val > (int32_t)max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < 0)
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
return (uint32_t)val;
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
#define __SADD8 __sadd8
|
||||
#define __QADD8 __qadd8
|
||||
#define __SHADD8 __shadd8
|
||||
#define __UADD8 __uadd8
|
||||
#define __UQADD8 __uqadd8
|
||||
#define __UHADD8 __uhadd8
|
||||
#define __SSUB8 __ssub8
|
||||
#define __QSUB8 __qsub8
|
||||
#define __SHSUB8 __shsub8
|
||||
#define __USUB8 __usub8
|
||||
#define __UQSUB8 __uqsub8
|
||||
#define __UHSUB8 __uhsub8
|
||||
#define __SADD16 __sadd16
|
||||
#define __QADD16 __qadd16
|
||||
#define __SHADD16 __shadd16
|
||||
#define __UADD16 __uadd16
|
||||
#define __UQADD16 __uqadd16
|
||||
#define __UHADD16 __uhadd16
|
||||
#define __SSUB16 __ssub16
|
||||
#define __QSUB16 __qsub16
|
||||
#define __SHSUB16 __shsub16
|
||||
#define __USUB16 __usub16
|
||||
#define __UQSUB16 __uqsub16
|
||||
#define __UHSUB16 __uhsub16
|
||||
#define __SASX __sasx
|
||||
#define __QASX __qasx
|
||||
#define __SHASX __shasx
|
||||
#define __UASX __uasx
|
||||
#define __UQASX __uqasx
|
||||
#define __UHASX __uhasx
|
||||
#define __SSAX __ssax
|
||||
#define __QSAX __qsax
|
||||
#define __SHSAX __shsax
|
||||
#define __USAX __usax
|
||||
#define __UQSAX __uqsax
|
||||
#define __UHSAX __uhsax
|
||||
#define __USAD8 __usad8
|
||||
#define __USADA8 __usada8
|
||||
#define __SSAT16 __ssat16
|
||||
#define __USAT16 __usat16
|
||||
#define __UXTB16 __uxtb16
|
||||
#define __UXTAB16 __uxtab16
|
||||
#define __SXTB16 __sxtb16
|
||||
#define __SXTAB16 __sxtab16
|
||||
#define __SMUAD __smuad
|
||||
#define __SMUADX __smuadx
|
||||
#define __SMLAD __smlad
|
||||
#define __SMLADX __smladx
|
||||
#define __SMLALD __smlald
|
||||
#define __SMLALDX __smlaldx
|
||||
#define __SMUSD __smusd
|
||||
#define __SMUSDX __smusdx
|
||||
#define __SMLSD __smlsd
|
||||
#define __SMLSDX __smlsdx
|
||||
#define __SMLSLD __smlsld
|
||||
#define __SMLSLDX __smlsldx
|
||||
#define __SEL __sel
|
||||
#define __QADD __qadd
|
||||
#define __QSUB __qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||
|
||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||
((int64_t)(ARG3) << 32U) ) >> 32U))
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#endif /* __CMSIS_ARMCC_H */
|
||||
1869
libraries/CMSIS/Include/cmsis_armclang.h
Normal file
1869
libraries/CMSIS/Include/cmsis_armclang.h
Normal file
File diff suppressed because it is too large
Load Diff
266
libraries/CMSIS/Include/cmsis_compiler.h
Normal file
266
libraries/CMSIS/Include/cmsis_compiler.h
Normal file
@ -0,0 +1,266 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Arm Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iccarm.h>
|
||||
|
||||
|
||||
/*
|
||||
* TI Arm Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
2085
libraries/CMSIS/Include/cmsis_gcc.h
Normal file
2085
libraries/CMSIS/Include/cmsis_gcc.h
Normal file
File diff suppressed because it is too large
Load Diff
935
libraries/CMSIS/Include/cmsis_iccarm.h
Normal file
935
libraries/CMSIS/Include/cmsis_iccarm.h
Normal file
@ -0,0 +1,935 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_iccarm.h
|
||||
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
|
||||
* @version V5.0.7
|
||||
* @date 19. June 2018
|
||||
******************************************************************************/
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
//
|
||||
// Copyright (c) 2017-2018 IAR Systems
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License")
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
|
||||
#ifndef __CMSIS_ICCARM_H__
|
||||
#define __CMSIS_ICCARM_H__
|
||||
|
||||
#ifndef __ICCARM__
|
||||
#error This file should only be compiled by ICCARM
|
||||
#endif
|
||||
|
||||
#pragma system_include
|
||||
|
||||
#define __IAR_FT _Pragma("inline=forced") __intrinsic
|
||||
|
||||
#if (__VER__ >= 8000000)
|
||||
#define __ICCARM_V8 1
|
||||
#else
|
||||
#define __ICCARM_V8 0
|
||||
#endif
|
||||
|
||||
#ifndef __ALIGNED
|
||||
#if __ICCARM_V8
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#elif (__VER__ >= 7080000)
|
||||
/* Needs IAR language extensions */
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#else
|
||||
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/* Define compiler macros for CPU architecture, used in CMSIS 5.
|
||||
*/
|
||||
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
|
||||
/* Macros already defined */
|
||||
#else
|
||||
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
|
||||
#define __ARM_ARCH_8M_MAIN__ 1
|
||||
#elif defined(__ARM8M_BASELINE__)
|
||||
#define __ARM_ARCH_8M_BASE__ 1
|
||||
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
|
||||
#if __ARM_ARCH == 6
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#elif __ARM_ARCH == 7
|
||||
#if __ARM_FEATURE_DSP
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#else
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#endif
|
||||
#endif /* __ARM_ARCH */
|
||||
#endif /* __ARM_ARCH_PROFILE == 'M' */
|
||||
#endif
|
||||
|
||||
/* Alternativ core deduction for older ICCARM's */
|
||||
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
|
||||
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
|
||||
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
|
||||
#define __ARM_ARCH_8M_BASE__ 1
|
||||
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
|
||||
#define __ARM_ARCH_8M_MAIN__ 1
|
||||
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
|
||||
#define __ARM_ARCH_8M_MAIN__ 1
|
||||
#else
|
||||
#error "Unknown target."
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
|
||||
#define __IAR_M0_FAMILY 1
|
||||
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
|
||||
#define __IAR_M0_FAMILY 1
|
||||
#else
|
||||
#define __IAR_M0_FAMILY 0
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
|
||||
#ifndef __NO_RETURN
|
||||
#if __ICCARM_V8
|
||||
#define __NO_RETURN __attribute__((__noreturn__))
|
||||
#else
|
||||
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED
|
||||
#if __ICCARM_V8
|
||||
#define __PACKED __attribute__((packed, aligned(1)))
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __PACKED __packed
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED_STRUCT
|
||||
#if __ICCARM_V8
|
||||
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __PACKED_STRUCT __packed struct
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED_UNION
|
||||
#if __ICCARM_V8
|
||||
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __PACKED_UNION __packed union
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
|
||||
#ifndef __FORCEINLINE
|
||||
#define __FORCEINLINE _Pragma("inline=forced")
|
||||
#endif
|
||||
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
|
||||
{
|
||||
return *(__packed uint16_t*)(ptr);
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
|
||||
{
|
||||
*(__packed uint16_t*)(ptr) = val;;
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
|
||||
{
|
||||
return *(__packed uint32_t*)(ptr);
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
|
||||
{
|
||||
*(__packed uint32_t*)(ptr) = val;;
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__packed struct __iar_u32 { uint32_t v; };
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
|
||||
#endif
|
||||
|
||||
#ifndef __USED
|
||||
#if __ICCARM_V8
|
||||
#define __USED __attribute__((used))
|
||||
#else
|
||||
#define __USED _Pragma("__root")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __WEAK
|
||||
#if __ICCARM_V8
|
||||
#define __WEAK __attribute__((weak))
|
||||
#else
|
||||
#define __WEAK _Pragma("__weak")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef __ICCARM_INTRINSICS_VERSION__
|
||||
#define __ICCARM_INTRINSICS_VERSION__ 0
|
||||
#endif
|
||||
|
||||
#if __ICCARM_INTRINSICS_VERSION__ == 2
|
||||
|
||||
#if defined(__CLZ)
|
||||
#undef __CLZ
|
||||
#endif
|
||||
#if defined(__REVSH)
|
||||
#undef __REVSH
|
||||
#endif
|
||||
#if defined(__RBIT)
|
||||
#undef __RBIT
|
||||
#endif
|
||||
#if defined(__SSAT)
|
||||
#undef __SSAT
|
||||
#endif
|
||||
#if defined(__USAT)
|
||||
#undef __USAT
|
||||
#endif
|
||||
|
||||
#include "iccarm_builtin.h"
|
||||
|
||||
#define __disable_fault_irq __iar_builtin_disable_fiq
|
||||
#define __disable_irq __iar_builtin_disable_interrupt
|
||||
#define __enable_fault_irq __iar_builtin_enable_fiq
|
||||
#define __enable_irq __iar_builtin_enable_interrupt
|
||||
#define __arm_rsr __iar_builtin_rsr
|
||||
#define __arm_wsr __iar_builtin_wsr
|
||||
|
||||
|
||||
#define __get_APSR() (__arm_rsr("APSR"))
|
||||
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
|
||||
#define __get_CONTROL() (__arm_rsr("CONTROL"))
|
||||
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
|
||||
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
#define __get_FPSCR() (__arm_rsr("FPSCR"))
|
||||
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
|
||||
#else
|
||||
#define __get_FPSCR() ( 0 )
|
||||
#define __set_FPSCR(VALUE) ((void)VALUE)
|
||||
#endif
|
||||
|
||||
#define __get_IPSR() (__arm_rsr("IPSR"))
|
||||
#define __get_MSP() (__arm_rsr("MSP"))
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
#define __get_MSPLIM() (0U)
|
||||
#else
|
||||
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
|
||||
#endif
|
||||
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
|
||||
#define __get_PSP() (__arm_rsr("PSP"))
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __get_PSPLIM() (0U)
|
||||
#else
|
||||
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
|
||||
#endif
|
||||
|
||||
#define __get_xPSR() (__arm_rsr("xPSR"))
|
||||
|
||||
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
|
||||
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
|
||||
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
|
||||
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
|
||||
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
#define __set_MSPLIM(VALUE) ((void)(VALUE))
|
||||
#else
|
||||
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
|
||||
#endif
|
||||
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
|
||||
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __set_PSPLIM(VALUE) ((void)(VALUE))
|
||||
#else
|
||||
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
|
||||
#endif
|
||||
|
||||
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
|
||||
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
|
||||
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
|
||||
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
|
||||
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
|
||||
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
|
||||
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
|
||||
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
|
||||
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
|
||||
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
|
||||
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
|
||||
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
|
||||
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
|
||||
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __TZ_get_PSPLIM_NS() (0U)
|
||||
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
|
||||
#else
|
||||
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
|
||||
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
|
||||
#endif
|
||||
|
||||
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
|
||||
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
|
||||
|
||||
#define __NOP __iar_builtin_no_operation
|
||||
|
||||
#define __CLZ __iar_builtin_CLZ
|
||||
#define __CLREX __iar_builtin_CLREX
|
||||
|
||||
#define __DMB __iar_builtin_DMB
|
||||
#define __DSB __iar_builtin_DSB
|
||||
#define __ISB __iar_builtin_ISB
|
||||
|
||||
#define __LDREXB __iar_builtin_LDREXB
|
||||
#define __LDREXH __iar_builtin_LDREXH
|
||||
#define __LDREXW __iar_builtin_LDREX
|
||||
|
||||
#define __RBIT __iar_builtin_RBIT
|
||||
#define __REV __iar_builtin_REV
|
||||
#define __REV16 __iar_builtin_REV16
|
||||
|
||||
__IAR_FT int16_t __REVSH(int16_t val)
|
||||
{
|
||||
return (int16_t) __iar_builtin_REVSH(val);
|
||||
}
|
||||
|
||||
#define __ROR __iar_builtin_ROR
|
||||
#define __RRX __iar_builtin_RRX
|
||||
|
||||
#define __SEV __iar_builtin_SEV
|
||||
|
||||
#if !__IAR_M0_FAMILY
|
||||
#define __SSAT __iar_builtin_SSAT
|
||||
#endif
|
||||
|
||||
#define __STREXB __iar_builtin_STREXB
|
||||
#define __STREXH __iar_builtin_STREXH
|
||||
#define __STREXW __iar_builtin_STREX
|
||||
|
||||
#if !__IAR_M0_FAMILY
|
||||
#define __USAT __iar_builtin_USAT
|
||||
#endif
|
||||
|
||||
#define __WFE __iar_builtin_WFE
|
||||
#define __WFI __iar_builtin_WFI
|
||||
|
||||
#if __ARM_MEDIA__
|
||||
#define __SADD8 __iar_builtin_SADD8
|
||||
#define __QADD8 __iar_builtin_QADD8
|
||||
#define __SHADD8 __iar_builtin_SHADD8
|
||||
#define __UADD8 __iar_builtin_UADD8
|
||||
#define __UQADD8 __iar_builtin_UQADD8
|
||||
#define __UHADD8 __iar_builtin_UHADD8
|
||||
#define __SSUB8 __iar_builtin_SSUB8
|
||||
#define __QSUB8 __iar_builtin_QSUB8
|
||||
#define __SHSUB8 __iar_builtin_SHSUB8
|
||||
#define __USUB8 __iar_builtin_USUB8
|
||||
#define __UQSUB8 __iar_builtin_UQSUB8
|
||||
#define __UHSUB8 __iar_builtin_UHSUB8
|
||||
#define __SADD16 __iar_builtin_SADD16
|
||||
#define __QADD16 __iar_builtin_QADD16
|
||||
#define __SHADD16 __iar_builtin_SHADD16
|
||||
#define __UADD16 __iar_builtin_UADD16
|
||||
#define __UQADD16 __iar_builtin_UQADD16
|
||||
#define __UHADD16 __iar_builtin_UHADD16
|
||||
#define __SSUB16 __iar_builtin_SSUB16
|
||||
#define __QSUB16 __iar_builtin_QSUB16
|
||||
#define __SHSUB16 __iar_builtin_SHSUB16
|
||||
#define __USUB16 __iar_builtin_USUB16
|
||||
#define __UQSUB16 __iar_builtin_UQSUB16
|
||||
#define __UHSUB16 __iar_builtin_UHSUB16
|
||||
#define __SASX __iar_builtin_SASX
|
||||
#define __QASX __iar_builtin_QASX
|
||||
#define __SHASX __iar_builtin_SHASX
|
||||
#define __UASX __iar_builtin_UASX
|
||||
#define __UQASX __iar_builtin_UQASX
|
||||
#define __UHASX __iar_builtin_UHASX
|
||||
#define __SSAX __iar_builtin_SSAX
|
||||
#define __QSAX __iar_builtin_QSAX
|
||||
#define __SHSAX __iar_builtin_SHSAX
|
||||
#define __USAX __iar_builtin_USAX
|
||||
#define __UQSAX __iar_builtin_UQSAX
|
||||
#define __UHSAX __iar_builtin_UHSAX
|
||||
#define __USAD8 __iar_builtin_USAD8
|
||||
#define __USADA8 __iar_builtin_USADA8
|
||||
#define __SSAT16 __iar_builtin_SSAT16
|
||||
#define __USAT16 __iar_builtin_USAT16
|
||||
#define __UXTB16 __iar_builtin_UXTB16
|
||||
#define __UXTAB16 __iar_builtin_UXTAB16
|
||||
#define __SXTB16 __iar_builtin_SXTB16
|
||||
#define __SXTAB16 __iar_builtin_SXTAB16
|
||||
#define __SMUAD __iar_builtin_SMUAD
|
||||
#define __SMUADX __iar_builtin_SMUADX
|
||||
#define __SMMLA __iar_builtin_SMMLA
|
||||
#define __SMLAD __iar_builtin_SMLAD
|
||||
#define __SMLADX __iar_builtin_SMLADX
|
||||
#define __SMLALD __iar_builtin_SMLALD
|
||||
#define __SMLALDX __iar_builtin_SMLALDX
|
||||
#define __SMUSD __iar_builtin_SMUSD
|
||||
#define __SMUSDX __iar_builtin_SMUSDX
|
||||
#define __SMLSD __iar_builtin_SMLSD
|
||||
#define __SMLSDX __iar_builtin_SMLSDX
|
||||
#define __SMLSLD __iar_builtin_SMLSLD
|
||||
#define __SMLSLDX __iar_builtin_SMLSLDX
|
||||
#define __SEL __iar_builtin_SEL
|
||||
#define __QADD __iar_builtin_QADD
|
||||
#define __QSUB __iar_builtin_QSUB
|
||||
#define __PKHBT __iar_builtin_PKHBT
|
||||
#define __PKHTB __iar_builtin_PKHTB
|
||||
#endif
|
||||
|
||||
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||
|
||||
#if __IAR_M0_FAMILY
|
||||
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
|
||||
#define __CLZ __cmsis_iar_clz_not_active
|
||||
#define __SSAT __cmsis_iar_ssat_not_active
|
||||
#define __USAT __cmsis_iar_usat_not_active
|
||||
#define __RBIT __cmsis_iar_rbit_not_active
|
||||
#define __get_APSR __cmsis_iar_get_APSR_not_active
|
||||
#endif
|
||||
|
||||
|
||||
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
|
||||
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
|
||||
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
|
||||
#endif
|
||||
|
||||
#ifdef __INTRINSICS_INCLUDED
|
||||
#error intrinsics.h is already included previously!
|
||||
#endif
|
||||
|
||||
#include <intrinsics.h>
|
||||
|
||||
#if __IAR_M0_FAMILY
|
||||
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
|
||||
#undef __CLZ
|
||||
#undef __SSAT
|
||||
#undef __USAT
|
||||
#undef __RBIT
|
||||
#undef __get_APSR
|
||||
|
||||
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
|
||||
{
|
||||
if (data == 0U) { return 32U; }
|
||||
|
||||
uint32_t count = 0U;
|
||||
uint32_t mask = 0x80000000U;
|
||||
|
||||
while ((data & mask) == 0U)
|
||||
{
|
||||
count += 1U;
|
||||
mask = mask >> 1U;
|
||||
}
|
||||
return count;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
|
||||
{
|
||||
uint8_t sc = 31U;
|
||||
uint32_t r = v;
|
||||
for (v >>= 1U; v; v >>= 1U)
|
||||
{
|
||||
r <<= 1U;
|
||||
r |= v & 1U;
|
||||
sc--;
|
||||
}
|
||||
return (r << sc);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm("MRS %0,APSR" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
|
||||
#undef __get_FPSCR
|
||||
#undef __set_FPSCR
|
||||
#define __get_FPSCR() (0)
|
||||
#define __set_FPSCR(VALUE) ((void)VALUE)
|
||||
#endif
|
||||
|
||||
#pragma diag_suppress=Pe940
|
||||
#pragma diag_suppress=Pe177
|
||||
|
||||
#define __enable_irq __enable_interrupt
|
||||
#define __disable_irq __disable_interrupt
|
||||
#define __NOP __no_operation
|
||||
|
||||
#define __get_xPSR __get_PSR
|
||||
|
||||
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
|
||||
|
||||
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
|
||||
{
|
||||
return __LDREX((unsigned long *)ptr);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
|
||||
{
|
||||
return __STREX(value, (unsigned long *)ptr);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
__IAR_FT uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
|
||||
return(result);
|
||||
}
|
||||
|
||||
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
|
||||
}
|
||||
|
||||
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
|
||||
}
|
||||
|
||||
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
|
||||
__IAR_FT uint32_t __get_MSPLIM(void)
|
||||
{
|
||||
uint32_t res;
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
res = 0U;
|
||||
#else
|
||||
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
|
||||
#endif
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __set_MSPLIM(uint32_t value)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
(void)value;
|
||||
#else
|
||||
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
|
||||
#endif
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __get_PSPLIM(void)
|
||||
{
|
||||
uint32_t res;
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
res = 0U;
|
||||
#else
|
||||
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
|
||||
#endif
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __set_PSPLIM(uint32_t value)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
(void)value;
|
||||
#else
|
||||
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
|
||||
#endif
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_SP_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,SP_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR SP_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
res = 0U;
|
||||
#else
|
||||
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
|
||||
#endif
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
(void)value;
|
||||
#else
|
||||
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
|
||||
#endif
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
|
||||
|
||||
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||
|
||||
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
|
||||
|
||||
#if __IAR_M0_FAMILY
|
||||
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if ((sat >= 1U) && (sat <= 32U))
|
||||
{
|
||||
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||
const int32_t min = -1 - max ;
|
||||
if (val > max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < min)
|
||||
{
|
||||
return min;
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if (sat <= 31U)
|
||||
{
|
||||
const uint32_t max = ((1U << sat) - 1U);
|
||||
if (val > (int32_t)max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < 0)
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
return (uint32_t)val;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
|
||||
|
||||
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||
return ((uint8_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||
return ((uint16_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
|
||||
|
||||
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint8_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint16_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
|
||||
{
|
||||
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
|
||||
{
|
||||
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
|
||||
{
|
||||
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint8_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint16_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
|
||||
|
||||
#undef __IAR_FT
|
||||
#undef __IAR_M0_FAMILY
|
||||
#undef __ICCARM_V8
|
||||
|
||||
#pragma diag_default=Pe940
|
||||
#pragma diag_default=Pe177
|
||||
|
||||
#endif /* __CMSIS_ICCARM_H__ */
|
||||
39
libraries/CMSIS/Include/cmsis_version.h
Normal file
39
libraries/CMSIS/Include/cmsis_version.h
Normal file
@ -0,0 +1,39 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.2
|
||||
* @date 19. April 2017
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
1918
libraries/CMSIS/Include/core_armv8mbl.h
Normal file
1918
libraries/CMSIS/Include/core_armv8mbl.h
Normal file
File diff suppressed because it is too large
Load Diff
2927
libraries/CMSIS/Include/core_armv8mml.h
Normal file
2927
libraries/CMSIS/Include/core_armv8mml.h
Normal file
File diff suppressed because it is too large
Load Diff
949
libraries/CMSIS/Include/core_cm0.h
Normal file
949
libraries/CMSIS/Include/core_cm0.h
Normal file
@ -0,0 +1,949 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cm0.h
|
||||
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
|
||||
* @version V5.0.5
|
||||
* @date 28. May 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM0_H_GENERIC
|
||||
#define __CORE_CM0_H_GENERIC
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||
Function definitions in header files are used to allow 'inlining'.
|
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Unions are used for effective representation of core registers.
|
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Function-like macros are used to allow more efficient code.
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\ingroup Cortex_M0
|
||||
@{
|
||||
*/
|
||||
|
||||
#include "cmsis_version.h"
|
||||
|
||||
/* CMSIS CM0 definitions */
|
||||
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_M (0U) /*!< Cortex-M Core */
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_PCS_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_CM0_H_DEPENDANT
|
||||
#define __CORE_CM0_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM0_REV
|
||||
#define __CM0_REV 0x0000U
|
||||
#warning "__CM0_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
/*@} end of group Cortex_M0 */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||
*/
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE Status and Control Registers
|
||||
\brief Core Register type definitions.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||
\brief Type definitions for the NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RSERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||
\brief Type definitions for the System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
uint32_t RESERVED0;
|
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED1;
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||
\brief Type definitions for the System Timer Registers.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||
Therefore they are not covered by the Cortex-M0 header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted value.
|
||||
*/
|
||||
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted bit field value.
|
||||
*/
|
||||
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||
|
||||
/*@} end of group CMSIS_core_bitfield */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_base Core Definitions
|
||||
\brief Definitions for base addresses, unions, and structures.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of Core Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||
@{
|
||||
*/
|
||||
|
||||
#ifdef CMSIS_NVIC_VIRTUAL
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||
|
||||
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
||||
|
||||
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under Armv6-M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||
|
||||
#define __NVIC_SetPriorityGrouping(X) (void)(X)
|
||||
#define __NVIC_GetPriorityGrouping() (0U)
|
||||
|
||||
/**
|
||||
\brief Enable Interrupt
|
||||
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Enable status
|
||||
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt is not enabled.
|
||||
\return 1 Interrupt is enabled.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable Interrupt
|
||||
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt
|
||||
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt
|
||||
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt
|
||||
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority
|
||||
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
\note The priority cannot be set for every processor exception.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority
|
||||
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority.
|
||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Encode Priority
|
||||
\details Encodes the priority for an interrupt with the given priority group,
|
||||
preemptive priority value, and subpriority value.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||
\param [in] PriorityGroup Used priority group.
|
||||
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [in] SubPriority Subpriority value (starting from 0).
|
||||
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
return (
|
||||
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Decode Priority
|
||||
\details Decodes an interrupt priority value with a given priority group to
|
||||
preemptive priority value and subpriority value.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||||
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
||||
\param [in] PriorityGroup Used priority group.
|
||||
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Vector
|
||||
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
Address 0 must be mapped to SRAM.
|
||||
\param [in] IRQn Interrupt number
|
||||
\param [in] vector Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)0x0U;
|
||||
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Vector
|
||||
\details Reads an interrupt vector from interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)0x0U;
|
||||
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief System Reset
|
||||
\details Initiates a system reset request to reset the MCU.
|
||||
*/
|
||||
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||
{
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
|
||||
/* ########################## FPU functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||
\brief Function that provides FPU type.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief get FPU type
|
||||
\details returns the FPU type
|
||||
\returns
|
||||
- \b 0: No FPU
|
||||
- \b 1: Single precision FPU
|
||||
- \b 2: Double + Single precision FPU
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||
{
|
||||
return 0U; /* No FPU */
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_FpuFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||
\brief Functions that configure the System.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||
|
||||
/**
|
||||
\brief System Tick Configuration
|
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||
{
|
||||
return (1UL); /* Reload value impossible */
|
||||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0UL); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0_H_DEPENDANT */
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
1083
libraries/CMSIS/Include/core_cm0plus.h
Normal file
1083
libraries/CMSIS/Include/core_cm0plus.h
Normal file
File diff suppressed because it is too large
Load Diff
976
libraries/CMSIS/Include/core_cm1.h
Normal file
976
libraries/CMSIS/Include/core_cm1.h
Normal file
@ -0,0 +1,976 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cm1.h
|
||||
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
|
||||
* @version V1.0.0
|
||||
* @date 23. July 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM1_H_GENERIC
|
||||
#define __CORE_CM1_H_GENERIC
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||
Function definitions in header files are used to allow 'inlining'.
|
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Unions are used for effective representation of core registers.
|
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Function-like macros are used to allow more efficient code.
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\ingroup Cortex_M1
|
||||
@{
|
||||
*/
|
||||
|
||||
#include "cmsis_version.h"
|
||||
|
||||
/* CMSIS CM1 definitions */
|
||||
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_M (1U) /*!< Cortex-M Core */
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_PCS_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM1_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_CM1_H_DEPENDANT
|
||||
#define __CORE_CM1_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM1_REV
|
||||
#define __CM1_REV 0x0100U
|
||||
#warning "__CM1_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
/*@} end of group Cortex_M1 */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||
*/
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE Status and Control Registers
|
||||
\brief Core Register type definitions.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||
\brief Type definitions for the NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RSERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||
\brief Type definitions for the System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
uint32_t RESERVED0;
|
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED1;
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
|
||||
\brief Type definitions for the System Control and ID Register not in the SCB
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control and ID Register not in the SCB.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t RESERVED0[2U];
|
||||
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
|
||||
} SCnSCB_Type;
|
||||
|
||||
/* Auxiliary Control Register Definitions */
|
||||
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
|
||||
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
|
||||
|
||||
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
|
||||
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCnotSCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||
\brief Type definitions for the System Timer Registers.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||
Therefore they are not covered by the Cortex-M1 header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted value.
|
||||
*/
|
||||
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted bit field value.
|
||||
*/
|
||||
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||
|
||||
/*@} end of group CMSIS_core_bitfield */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_base Core Definitions
|
||||
\brief Definitions for base addresses, unions, and structures.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of Core Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||
@{
|
||||
*/
|
||||
|
||||
#ifdef CMSIS_NVIC_VIRTUAL
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||
|
||||
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
||||
|
||||
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under Armv6-M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||
|
||||
#define __NVIC_SetPriorityGrouping(X) (void)(X)
|
||||
#define __NVIC_GetPriorityGrouping() (0U)
|
||||
|
||||
/**
|
||||
\brief Enable Interrupt
|
||||
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Enable status
|
||||
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt is not enabled.
|
||||
\return 1 Interrupt is enabled.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable Interrupt
|
||||
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt
|
||||
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt
|
||||
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt
|
||||
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority
|
||||
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
\note The priority cannot be set for every processor exception.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority
|
||||
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority.
|
||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Encode Priority
|
||||
\details Encodes the priority for an interrupt with the given priority group,
|
||||
preemptive priority value, and subpriority value.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||
\param [in] PriorityGroup Used priority group.
|
||||
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [in] SubPriority Subpriority value (starting from 0).
|
||||
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
return (
|
||||
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Decode Priority
|
||||
\details Decodes an interrupt priority value with a given priority group to
|
||||
preemptive priority value and subpriority value.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||||
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
||||
\param [in] PriorityGroup Used priority group.
|
||||
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Vector
|
||||
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
Address 0 must be mapped to SRAM.
|
||||
\param [in] IRQn Interrupt number
|
||||
\param [in] vector Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)0x0U;
|
||||
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Vector
|
||||
\details Reads an interrupt vector from interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)0x0U;
|
||||
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief System Reset
|
||||
\details Initiates a system reset request to reset the MCU.
|
||||
*/
|
||||
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||
{
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
|
||||
/* ########################## FPU functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||
\brief Function that provides FPU type.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief get FPU type
|
||||
\details returns the FPU type
|
||||
\returns
|
||||
- \b 0: No FPU
|
||||
- \b 1: Single precision FPU
|
||||
- \b 2: Double + Single precision FPU
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||
{
|
||||
return 0U; /* No FPU */
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_FpuFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||
\brief Functions that configure the System.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||
|
||||
/**
|
||||
\brief System Tick Configuration
|
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||
{
|
||||
return (1UL); /* Reload value impossible */
|
||||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0UL); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM1_H_DEPENDANT */
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
1993
libraries/CMSIS/Include/core_cm23.h
Normal file
1993
libraries/CMSIS/Include/core_cm23.h
Normal file
File diff suppressed because it is too large
Load Diff
1941
libraries/CMSIS/Include/core_cm3.h
Normal file
1941
libraries/CMSIS/Include/core_cm3.h
Normal file
File diff suppressed because it is too large
Load Diff
3002
libraries/CMSIS/Include/core_cm33.h
Normal file
3002
libraries/CMSIS/Include/core_cm33.h
Normal file
File diff suppressed because it is too large
Load Diff
2129
libraries/CMSIS/Include/core_cm4.h
Normal file
2129
libraries/CMSIS/Include/core_cm4.h
Normal file
File diff suppressed because it is too large
Load Diff
2671
libraries/CMSIS/Include/core_cm7.h
Normal file
2671
libraries/CMSIS/Include/core_cm7.h
Normal file
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user